A1210, A1211, A1212, A1213, and A1214

Continuous-Time Latch Family

FEATURES AND BENEFITS DESCRIPTION

• AEC-Q100 automotive qualified The Allegro™ A1210-A1214 Hall-effect latches are next
• Continuous-time operation generation replacements for the popular Allegro 317x and
□ Fast power-on time 318x lines of latching switches. The A121x family, produced
with BiCMOS technology, consists of devices that feature fast
□ Low noise
power-on time and low-noise operation. Device programming
• Stable operation over full operating temperature range is performed after packaging, to ensure increased switch point
• Reverse-battery protection accuracy by eliminating offsets that can be induced by package
• Solid-state reliability stress. Unique Hall element geometries and low-offset amplifiers
• Factory-programmed at end-of-line for optimum help to minimize noise and to reduce the residual offset voltage
performance normally caused by device overmolding, temperature excursions,
and thermal stress.
• Robust EMC performance
• High ESD rating The A1210-A1214 Hall-effect latches include the following on
• Regulator stability without a bypass capacitor a single silicon chip: voltage regulator, Hall-voltage generator,
small-signal amplifier, Schmitt trigger, and NMOS output
PACKAGES: transistor. The integrated voltage regulator permits operation from
Not to scale 3.8 to 24 V. The extensive on-board protection circuitry makes
possible a ±30 V absolute maximum voltage rating for superior
protection in automotive and industrial motor commutation
applications, without adding external components. All devices in
the family are identical except for magnetic switch point levels.
NOT FOR The small geometries of the BiCMOS process allow these
NEW DESIGN
devices to be provided in ultra small packages. The package
styles available provide magnetically optimized solutions for
most applications. Package LH is an SOT23W, a miniature low-
3-pin SOT23W profile surface-mount package, while package UA is a three-lead
(suffix LH)
ultra mini SIP for through-hole mounting. Each package is lead
3-pin SIP, 3-pin SIP,
matrix HD style chopper style
(Pb) free, with 100% matte-tin-plated leadframes.
(suffix UA) (suffix UA)

VCC

Regulator To all subcircuits

VOUT

Amp

Gain Offset

Trim
Control

GND

Functional Block Diagram

A1210-DS, Rev. 17 December 13, 2021

MCO-0000574
A1210, A1211,
A1212, A1213, Continuous-Time Latch Family
and A1214

SPECIFICATIONS

SELECTION GUIDE
Part Number Packing [1] Mounting Ambient, TA BRP (Min) BOP (Max)
A1210ELHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
–40°C to 85°C
A1210ELHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1210LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount –150 G 150 G
A1210LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount –40°C to 150°C
A1210LUA-T [2] Bulk, 500 pieces/bag 3-pin SIP through hole
A1211LUA-T [2] Bulk, 500 pieces/bag 3-pin SIP through hole –40°C to 150°C –180 G 180 G
A1212LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
A1212LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount –40°C to 150°C –175 G 175 G
A1212LUA-T [2] Bulk, 500 pieces/bag 3-pin SIP through hole
A1213LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
A1213LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount –40°C to 150°C –200 G 200 G
A1213LUA-T [2] Bulk, 500 pieces/bag 3-pin SIP through hole
A1214LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
A1214LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount –40°C to 150°C –300 G 300 G
A1214LUA-T [2] Bulk, 500 pieces/bag 3-pin SIP through hole

[1] Contact Allegro for additional packing options.

[2] The chopper-style UA package is not for new design; the matrix HD style UA package is recommended for new designs.

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Unit
Supply Voltage VCC 30 V
Reverse Supply Voltage VRCC –30 V
Output Off Voltage VOUT 30 V
Reverse Output Voltage VROUT –0.5 V
Output Current IOUTSINK 25 mA
Magnetic Flux Density B 1 G = 0.1 mT (millitesla) Unlimited G
Range E –40 to 85 °C
Operating Ambient Temperature TA
Range L –40 to 150 °C
Maximum Junction Temperature TJ(max) 165 °C
Storage Temperature Tstg –65 to 170 °C

2
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A1210, A1211,
A1212, A1213, Continuous-Time Latch Family
and A1214

PINOUT DIAGRAMS AND TERMINAL LIST TABLE

GND

1 2 1 2 3

VCC

VOUT
GND
VCC

VOUT

Package LH, 3-Pin SOT23W Pinout Diagram Package UA, 3-Pin SIP Pinout Diagram

Terminal List
Number
Name Description
Package LH Package UA
VCC 1 1 Connects power supply to chip
VOUT 2 3 Output from circuit
GND 3 2 Ground

3
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A1210, A1211,
A1212, A1213, Continuous-Time Latch Family
and A1214

OPERATING CHARACTERISTICS: Over full operating voltage and ambient temperature ranges, unless otherwise noted
Characteristic Symbol Test Conditions Min. Typ. Max. Units
ELECTRICAL CHARACTERISTICS
Supply Voltage [1] VCC Operating, TJ < 165°C 3.8 – 24 V
Output Leakage Current IOUTOFF VOUT = 24 V, B < BRP – – 10 µA
Output On Voltage VOUT(SAT) IOUT = 20 mA, B > BOP – 215 400 mV
Slew rate (dVCC/dt) < 2.5 V/μs, B > BOP + 5 G or B < BRP
Power-On Time [2] tPO – – 4 µs
–5G
Output Rise Time [3] tr VCC = 12 V, RLOAD = 820 Ω, CS = 12 pF – – 400 ns
Output Fall Time [3] tf VCC = 12 V, RLOAD = 820 Ω, CS = 12 pF – – 400 ns
ICCON B > BOP – 4.1 7.5 mA
Supply Current
ICCOFF B < BRP – 3.8 7.5 mA
Reverse Battery Current IRCC VRCC = –30 V – – –10 mA
Supply Zener Clamp Voltage VZ ICC = 10.5 mA; TA = 25°C 32 – – V
Supply Zener Current [4] IZ VZ = 32 V; TA = 25°C – – 10.5 mA
MAGNETIC CHARACTERISTICS [5]

A1210 25 78 150 G
A1211 15 87 180 G
South pole adjacent to branded face of
Operate Point BOP A1212 50 107 175 G
device
A1213 80 – 200 G
A1214 140 – 300 G
A1210 –150 –78 –25 G
A1211 –180 –95 –15 G
North pole adjacent to branded face of
Release Point BRP A1212 –175 –117 –50 G
device
A1213 –200 – –80 G
A1214 –300 – –140 G
A1210 50 155 – G
A1211 80 180 – G
Hysteresis BHYS A1212 BOP – BRP 100 225 350 G
A1213 160 – 400 G
A1214 280 – 600 G
[1] Maximum voltage must be adjusted for power dissipation and junction temperature, see Power Derating section.
[2] For VCC slew rates greater than 250 V/μs, and TA = 150°C, the Power-On Time can reach its maximum value.
[3] C =oscilloscope probe capacitance.
S
[4] Maximum current limit is equal to the maximum I
CC(max) + 3 mA.
[5] Magnetic flux density, B, is indicated as a negative value for north-polarity magnetic fields, and as a positive value for south-polarity magnetic
fields. This so-called algebraic convention supports arithmetic comparison of north and south polarity values, where the relative strength of the field
is indicated by the absolute value of B, and the sign indicates the polarity of the field (for example, a –100 G field and a 100 G field have equivalent
strength, but opposite polarity).
DEVICE QUALIFICATION PROGRAM
Contact Allegro for information.

EMC (Electromagnetic Compatibility) REQUIREMENTS

Contact Allegro for information.

4
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A1210, A1211,
A1212, A1213, Continuous-Time Latch Family
and A1214

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions Value Units
Package LH, on single layer, single-sided PCB with copper limited to
228 °C/W
solder pads
Package LH, on single layer, double-sided PCB with 0.926 in2 copper
Package Thermal Resistance RθJA 110 °C/W
area
Package UA on single layer, single-sided PCB with copper limited to
165 °C/W
solder pads

Power Derating Curve

TJ(max) = 165ºC; ICC = ICC(max)
25
24 VCC(max)
23
22
Maximum Allowable VCC (V)

21
20
19
18
17
16
15
14
13
12
Low-K PCB, Package LH
11 (RθJA = 110 ºC/W)
10
9 Minimum-K PCB, Package UA
8 (RθJA = 165 ºC/W)
7
6 Minimum-K PCB, Package LH
5 (RθJA = 228 ºC/W)
4 VCC(min)
3
2
20 40 60 80 100 120 140 160 180

Temperature
Power Dissipation (ºC)
versus Ambient Temperature

1900
1800
1700
1600
1500
1400
1300
Power Dissipation, PD (m W)

1200 Lo
1100 (R w-K
θJ PC
A =
1000 11 B, P
Min 0 º ac
900 C/ ka
800 (R imum W ge
) LH
θJA = -K
165 P C
700 B, P
ºC/ a cka
W)
600 ge
UA
500 Min
400 imu
(R m-K
P
300 θJA =
228 CB, Pa
ºC/W ckag
200 ) e LH
100
0
20 40 60 80 100 120 140 160 180
Temperature (°C)

5
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A1210, A1211,
A1212, A1213, Continuous-Time Latch Family
and A1214

CHARACTERISTIC DATA

Supply Current (On) versus Ambient Temperature Supply Current (On) versus Supply Voltage
(A1210/11/12/13/14) (A1210/11/12/13/14)

8.0 8.0
7.0 7.0
6.0 6.0 TA (°C)
VCC (V)
ICCON (mA)

ICCON (mA)
5.0 5.0 –40
24
4.0 4.0 25
3.8
150
3.0 3.0
2.0 2.0
1.0 1.0
0 0
–50 0 50 100 150 0 5 10 15 20 25
TA (°C) VCC (V)

Supply Current (Off) versus Ambient Temperature Supply Current (Off) versus Supply Voltage
(A1210/11/12/13/14) (A1210/11/12/13/14)

8.0 8.0
7.0 7.0
6.0 6.0 TA (°C)
VCC (V)
ICCOFF (mA)

ICCOFF (mA)

5.0 5.0 –40

24
4.0 4.0 25
3.8
150
3.0 3.0
2.0 2.0
1.0 1.0
0 0
–50 0 50 100 150 0 5 10 15 20 25
TA (°C) VCC (V)

Output Voltage (On) versus Ambient Temperature Output Voltage (On) versus Supply Voltage
(A1210/11/12/13/14) (A1210/11/12/13/14)
400 400
350 350
300 300
VOUT(SAT) (mV)

TA (°C)
VOUT(SAT) (mV)

250 VCC (V) 250

24 –40
200 200
3.8 25
150 150 150

100 100

50 50

0 0
–50 0 50 100 150 0 5 10 15 20 25
TA (°C) VCC (V)

6
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A1210, A1211,
A1212, A1213, Continuous-Time Latch Family
and A1214

Operate Point versus Ambient Temperature Operate Point versus Supply Voltage
(A1210) (A1210)

150 150

125 125
TA (°C)
VCC (V)
100 100 –40
BOP (G)

BOP (G)
24
25
3.8
75 75 150

50 50

25 25
–50 0 50 100 150 0 5 10 15 20 25
TA (°C) VCC (V)

Release Point versus Ambient Temperature Release Point versus Supply Voltage
(A1210) (A1210)

-25 -25

-50 -50
TA (°C)
VCC (V)
-75 -75 –40
BRP (G)

BRP (G)

24
25
3.8
-100 -100 150

-125 -125

-150 -150
–50 0 50 100 150 0 5 10 15 20 25
TA (°C) VCC (V)

Hysteresis versus Ambient Temperature Hysteresis versus Supply Voltage

(A1210) (A1210)
225 225

200 200

175 175
VCC (V) TA (°C)
BHYS (G)

BHYS (G)

150 150 –40

24
3.8 25
125 125
150
100 100

75 75

50 50
–50 0 50 100 150 0 5 10 15 20 25
TA (°C) VCC (V)

7
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955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1210, A1211,
A1212, A1213, Continuous-Time Latch Family
and A1214

Operate Point versus Ambient Temperature Operate Point versus Ambient Temperature
(A1211) (A1212)

175
165 150
140 125
VCC (V) 100 VCC (V)
BOP (G)

BOP (G)
115
24 75 24
90 3.8 50 3.8
25
65
0
40 -25
15 -50
–50 0 50 100 150 –50 0 50 100 150
TA (°C) TA (°C)

Release Point versus Ambient Temperature Release Point versus Ambient Temperature
(A1211) (A1212)

-30 -50

-55 -75
VCC (V) VCC (V)
-80
BRP (G)

BRP (G)

24 -100 24
-105 3.8 3.8
-125
-130

-155 -150

-180 -175
–50 0 50 100 150 –50 0 50 100 150
TA (°C) TA (°C)

Hysteresis versus Ambient Temperature Hysteresis versus Ambient Temperature

(A1211) (A1212)
240
350
220

200 300

180 VCC (V) VCC (V)

250
BHYS (G)

BHYS (G)

160 24 24
3.8 3.8
140 200

120
150
100

80 100
–50 0 50 100 150 –50 0 50 100 150
TA (°C) TA (°C)

8
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1210, A1211,
A1212, A1213, Continuous-Time Latch Family
and A1214

FUNCTIONAL DESCRIPTION

Operation Due to offsets generated during the IC packaging process,

continuous-time devices typically require programming after
The output of these devices switches low (turns on) when a
packaging to tighten magnetic parameter distributions. In con-
magnetic field perpendicular to the Hall element exceeds the
trast, chopper-stabilized switches employ an offset cancellation
operate point threshold, BOP. After turn-on, the output is capable
technique on the chip that eliminates these offsets without the
of sinking 25 mA and the output voltage is VOUT(SAT). Notice
need for after-packaging programming. The tradeoff is a longer
that the device latches; that is, a south pole of sufficient strength
towards the branded surface of the device turns the device on, settling time and reduced frequency response as a result of the
and the device remains on with removal of the south pole. When chopper-stabilization offset cancellation algorithm.
the magnetic field is reduced below the release point, BRP , The choice between continuous-time and chopper-stabilized
the device output goes high (turns off). The difference in the designs is solely determined by the application. Battery manage-
magnetic operate and release points is the hysteresis, Bhys, of ment is an example where continuous-time is often required. In
the device. This built-in hysteresis allows clean switching of the
these applications, VCC is chopped with a very small duty cycle
output, even in the presence of external mechanical vibration and
in order to conserve power (refer to figure 2). The duty cycle
electrical noise.
is controlled by the power-on time, tPO, of the device. Because
Powering-on the device in the hysteresis range, less than BOP continuous-time devices have the shorter power-on time, they
and higher than BRP, allows an indeterminate output state. The are the clear choice for such applications.
correct state is attained after the first excursion beyond BOP or
BRP. For more information on the chopper stabilization technique,
refer to Technical Paper STP 97-10, Monolithic Magnetic Hall
Continuous-Time Benefits Sensing Using Dynamic Quadrature Offset Cancellation and
Technical Paper STP 99-1, Chopper-Stabilized Amplifiers with a
Continuous-time devices, such as the A121x family, offer the Track-and-Hold Signal Demodulator.
fastest available power-on settling time and frequency response.

(A) (B)
VS
V+
VCC
VCC RL
Switch to High

Switch to Low

Output
VOUT

A121x VOUT

GND
VOUT(SAT)
0
B– 0 B+
BOP
BRP

BHYS

Figure 1: Switching Behavior of Latches

On the horizontal axis, the B+ direction indicates increasing south polarity magnetic field strength, and the B– direction indicates decreasing
south polarity field strength (including the case of increasing north polarity). This behavior can be exhibited when using a circuit such as that
shown in Panel B.

9
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A1210, A1211,
A1212, A1213, Continuous-Time Latch Family
and A1214

Additional Application Information

Extensive applications information for Hall-effect devices is
available in:
• Hall-Effect IC Applications Guide, Application Note 27701
• Hall-Effect Devices: Gluing, Potting, Encapsulating, Lead
Welding and Lead Forming, Application Note 27703.1
• Soldering Methods for Allegro’s Products – SMT and
Through-Hole, Application Note 26009
All are provided on the Allegro website, www.allegromicro.com.

1 2 3 4 5

VCC

VOUT
t

Output Sampled
tPO(max)

Figure 2: Continuous-Time Application, B < BRP

This figure illustrates the use of a quick cycle for chopping VCC in order to conserve battery power. Position 1, power is applied to the
device. Position 2, the output assumes the correct state at a time prior to the maximum Power-On Time, tPO(max). The case shown is where
the correct output state is HIGH . Position 3, tPO(max) has elapsed. The device output is valid. Position 4, after the output is valid, a control unit
reads the output. Position 5, power is removed from the device.

10
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A1210, A1211,
A1212, A1213, Continuous-Time Latch Family
and A1214

POWER DERATING

Power Derating  PD = VCC × ICC = 12 V × 4 mA = 48 mW

The device must be operated below the maximum junction ΔT = PD × RθJA = 48 mW × 140°C/W = 7°C
temperature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating sup-  TJ = TA + ΔT = 25°C + 7°C = 32°C
plied power or improving the heat dissipation properties of the
A worst-case estimate, PD(max), represents the maximum allow-
application. This section presents a procedure for correlating
able power level (VCC(max), ICC(max)), without exceeding TJ(max),
factors affecting operating TJ. (Thermal data is also available on
at a selected RθJA and TA.
the Allegro MicroSystems Web site.)
Example: Reliability for VCC at TA = 150°C, package UA, using
The Package Thermal Resistance, RθJA, is a figure of merit sum-
minimum-K PCB.
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air. Observe the worst-case ratings for the device, specifically:
Its primary component is the Effective Thermal Conductivity, RθJA = 165°C/W, TJ(max)  = 165°C, VCC(max) = 24 V, and
K, of the printed circuit board, including adjacent devices and ICC(max)  = 7.5 mA.
traces. Radiation from the die through the device case, RθJC, is
Calculate the maximum allowable power level, PD(max). First,
relatively small component of RθJA. Ambient air temperature,
invert equation 3:
TA, and air motion are significant external factors, damped by
overmolding.
ΔTmax = TJ(max) – TA = 165°C – 150°C = 15 °C
The effect of varying power levels (Power Dissipation, PD), can This provides the allowable increase to TJ resulting from internal
be estimated. The following formulas represent the fundamental power dissipation. Then, invert equation 2:
relationships used to estimate TJ, at PD. 
PD(max) = ΔTmax ÷ RθJA = 15°C ÷ 165°C/W = 91 mW
PD = VIN × IIN (1)
Finally, invert equation 1 with respect to voltage:
ΔT = PD × RθJA (2)
VCC(est) = PD(max) ÷  ICC(max) = 91 mW ÷ 7.5 mA = 12.1 V
TJ = TA + ΔT (3) The result indicates that, at TA, the application and device can
For example, given common conditions such as: TA= 25°C, dissipate adequate amounts of heat at voltages ≤VCC(est).
VCC = 12 V, ICC = 4 mA, and RθJA = 140°C/W, then: Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reli-
able operation between VCC(est) and VCC(max) requires enhanced
RθJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and
VCC(max) is reliable under these conditions.

11
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A1210, A1211,
A1212, A1213, Continuous-Time Latch Family
and A1214

PACKAGE OUTLINE DRAWINGS

For Reference Only – Not for Tooling Use

(Reference Allegro DWG-0000628, Rev. 1)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.125
2.975 –0.075
D
1.49
4°±4°
A
3
+0.020
0.180
–0.053

0.96 D

+0.10 +0.19 2.40

2.90 1.91
–0.20 –0.06
0.25 MIN 0.70
D
0.38 NOM

1.00

1 2
0.55 REF
0.25 BSC 0.95
Seating Plane
Gauge Plane
B PCB Layout Reference View
Branded Face
8× 10° ±5°

0.57 ±0.04
3× 1.00 ±0.13 C

0.10 C 0.41 ±0.04

SEATING NNN NNT
PLANE
+0.10
0.05 –0.05

0.95 BSC 0.40 ±0.10

N = Last three digits of device part number N = Last two digits of device part number
A Active Area Depth, 0.28 ±0.04 mm T = Temperature code
B Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
C Standard Branding Reference View
to meet application process requirements and PCB layout tolerances
C Branding scale and appearance at supplier discretion

D Hall elements, not to scale

Figure 3: Package LH, 3-Pin SOT-23W

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A1210, A1211,
A1212, A1213, Continuous-Time Latch Family
and A1214

For Reference Only – Not For Tooling Use

(Reference Allegro DWG-0000404, Rev. 1)
NOT TO SCALE
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
NNN

Ejector pin flash Mold gate and tie bar

protrusion protrusion zone
1
R0.25 MAX (2×) 5° (2×) 0.56 MAX
= Supplier emblem
N = Last three digits of device part number

45° (2×) 1.52 ±0.05 1.68 MAX

0.10 MAX
5° (2×) NNT

+0.08
4.09 –0.05 1

3.00 ±0.05 = Supplier emblem

N = Last two digits of device part number
T = Temperature code
2.04
Mold gate and tie bar
protrusion zone 0.15 MAX

Ejector pin +0.05 0.50 ±0.08 Active Area Depth

(far side) 0.08 –0.00
Including gate and
tie bar burrs
Ejector pin flash
protrusion
1.44
3.10 MAX +0.08
3.02 –0.05
45°
10° (3×)
Hall element
(not to scale)
1.02 MAX 0.79 REF

0.51 REF

0.05 NOM
0.05 NOM

14.99 ±0.25 +0.03

0.41 –0.06

0.10 MAX

0.10 MAX
Dambar Trim Detail

1.27 NOM (2×) +0.05

0.43 –0.07 (3×)

Figure 4: Package UA, 3-Pin SIP, Matrix Style

13
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A1210, A1211,
A1212, A1213, Continuous-Time Latch Family
and A1214

+0.08
4.09 –0.05

45°
B
C
E
2.04
1.52 ±0.05

1.44 E
Mold Ejector
+0.08 Pin Indent
3.02 –0.05
E
Branded 45°
Face
2.16
MAX D Standard Branding Reference View
0.79 REF

0.51
REF
A
NOT FOR NNN

NEW DESIGN
1 2 3

1
= Supplier emblem
+0.03 N = Last two digits of device part number
0.41 –0.06
15.75 ±0.51 T = Temperature code

For Reference Only; not for tooling use (reference DWG-9049)

Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

A Dambar removal protrusion (6X)

B Gate burr area
C Active Area Depth, 0.50 mm REF
D Branding scale and appearance at supplier discretion
E Hall element, not to scale

+0.05 1.27 NOM

0.43 –0.07

Figure 5: Package UA, 3-Pin SIP, Chopper Style

14
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A1210, A1211,
A1212, A1213, Continuous-Time Latch Family
and A1214

Revision History
Number Date Description
10 May 29, 2012 Update UA package drawing
11 August 20, 2014 Revised Selection Guide, reformatted datasheet
12 January 1, 2015 Added LX option to Selection Guide
13 September 22, 2015 Corrected LH package Active Area Depth value; added AEC-Q100 qualification under
Features and Benefits
14 November 4, 2016 Chopper-style UA package designated as not for new design
15 February 4, 2019 Updated Active Area Depth for UA matrix-style package, and minor editorial updates
16 February 12, 2020 Minor editorial updates
17 December 13, 2021 Updated package drawings and minor editorial updates

Copyright 2021, Allegro MicroSystems.

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.

For the latest version of this document, visit our website:

www.allegromicro.com

15
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com