Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd Logo
Upload

Welcome to Scribd!

  • 40 views

    3A DDR Bus Termination Regulator: Features General Description

    Uploaded by

    ale barraza
    The G2992 is a linear regulator designed to provide termination voltages for DDR I, DDR II, DDR III, and DDR IIIL SDRAM. It can source and sink 3A of current to meet JEDEC specifications. It requires only a 20uF ceramic output capacitor and has low power consumption of 750uA at 3.3V with shutdown and suspend-to-RAM functionality. The G2992 supports termination voltages from 1.2V to 3.6V with an input voltage range of 3.3V to 5.5V in an 8-pin SOP package.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    3A DDR Bus Termination Regulator: Features General Description

    Uploaded by

    ale barraza
    40 views1 page
    The G2992 is a linear regulator designed to provide termination voltages for DDR I, DDR II, DDR III, and DDR IIIL SDRAM. It can source and sink 3A of current to meet JEDEC specifications. It requires only a 20uF ceramic output capacitor and has low power consumption of 750uA at 3.3V with shutdown and suspend-to-RAM functionality. The G2992 supports termination voltages from 1.2V to 3.6V with an input voltage range of 3.3V to 5.5V in an 8-pin SOP package.

    Original Title

    G2992

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    The G2992 is a linear regulator designed to provide termination voltages for DDR I, DDR II, DDR III, and DDR IIIL SDRAM. It can source and sink 3A of current to meet JEDEC specifications. It requires only a 20uF ceramic output capacitor and has low power consumption of 750uA at 3.3V with shutdown and suspend-to-RAM functionality. The G2992 supports termination voltages from 1.2V to 3.6V with an input voltage range of 3.3V to 5.5V in an 8-pin SOP package.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    40 views1 page

    3A DDR Bus Termination Regulator: Features General Description

    Uploaded by

    ale barraza
    The G2992 is a linear regulator designed to provide termination voltages for DDR I, DDR II, DDR III, and DDR IIIL SDRAM. It can source and sink 3A of current to meet JEDEC specifications. It requires only a 20uF ceramic output capacitor and has low power consumption of 750uA at 3.3V with shutdown and suspend-to-RAM functionality. The G2992 supports termination voltages from 1.2V to 3.6V with an input voltage range of 3.3V to 5.5V in an 8-pin SOP package.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    You are on page 1of 1

    Global Mixed-mode Technology G2992

    3A DDR Bus Termination Regulator


    Features General Description
    „ VCNTL Supply Voltage: 3.3V to 5.5V The G2992 is a linear regulator designed to meet the
    „ Termination Supply Voltage: 1.2V to 3.6V JEDEC SSTL-18, SSTL-2 and SSTL-3 (Series Stub
    „ Support DDR I(1.25VTT), DDR II (0.9 VTT), DDR III Termination Logic) specifications for termination of DDR
    (0.75VTT), and DDR IIIL (0.675VTT) Requirements I/II/III/IIIL -SDRAM. It contains a high-speed operational
    „ Requires Only 20µF Ceramic Output Capacitor amplifier that provides excellent response to the load
    „ Low Output Offset transients. This device can deliver 3A continuous cur-
    „ 3A Source and Sink Current rent in the application such as required for DDR I/II/III
    „ Low External Component Count /IIIL SDRAM termination. The G2992 can easily provide
    „ No Inductor Required the accurate VTT voltage with two external resistors
    „ Thermal Shutdown Protection generating reference voltage. The quiescent current is
    „ Over Current Protection as low as 750µA @ VCNTL = 3.3V. So the power con-
    „ Suspend to RAM (STR) Function with sumption can meet the low power consumption applica-
    High-impedance output tions. The G2992 also has a shutdown function by set-
    „ SOP-8 (FD) Package
    ting VREF smaller than 0.2V, that provides Suspend to
    RAM (STR) functionality. When in the shutdown mode,
    Applications the VTT output (on VOUT pin) will be tri-state providing a
    „ DDR-SDRAM Termination Voltage high impendence. A power saving advantage can be
    „ DDR I / DDR II / DDR III / DDR IIIL Termination obtained in this mode through lowering the quiescent
    Voltage
    current to 50μA @ VCNTL = 3.3V.
    „ SSTL-18
    „ SSTL-2
    „ SSTL-3

    Ordering Information
    ORDER TEMP. PACKAGE
    MARKING
    NUMBER RANGE (Green)
    G2992F1U G2992 -40°C to +85°C SOP-8 (FD)
    Note: F1: SOP-8 (FD)
    U: Tape & Reel

    Pin Configuration
    G2992 DDR II
    VCNTL=3.3V
    VIN 1 8 NC
    VIN=1.8V RTT
    GND 2 7 NC CIN CCNTL
    Thermal R1
    VIN VCNTL
    Pad
    VREF 3 6 VCNTL
    VREF VOUT
    2N7002
    VOUT 4 5 NC CSS COUT RDUMMY
    EN R2 GND

    SOP-8 (FD)
    Note: Recommend connecting the Thermal Pad to
    the Ground for excellent power dissipation.

    Typical Application Circuit

    DDR I DDR III*


    VCNTL=3.3V VCNTL=3.3V

    VIN=2.5V RTT VIN=1.5V RTT


    R1 CIN CCNTL R1 CIN CCNTL
    VIN VCNTL VIN VCNTL

    VREF VOUT VREF VOUT


    2N7002 2N7002
    CSS COUT RDUMMY CSS COUT R
    EN R2 GND EN R2 GND DUMMY

    * Recommended VCTRL =3.3V

    Ver: 1.7 TEL: 886-3-5788833


    Jun 26, 2012 http://www.gmt.com.tw
    1

    You might also like