RT9624F Richtek

®
RT9624F
Single Phase Synchronous Rectified Buck MOSFET Driver
General Description Features
The RT9624F is a high frequency, synchronous rectified,  Drive Two N-MOSFETs
single phase MOSFET driver designed for normal MOSFET  Shoot Through Protection
driving applications and high performance CPU VR driving  Embedded Bootstrap Diode
capabilities.  Support High Switching Frequency
 Fast Output Rising Time
The RT9624F can be supplied from 4.5V to 13.2V. The
 Tri-State PWM Input for Output Shutdown
applicable power stage VIN range is from 5V to 24V. The
 8-Lead WDFN Package
IC also builds in an internal power switch to replace
 RoHS Compliant and Halogen Free
external bootstrap diode.
The RT9624F can support switching frequency efficiently
Applications
up to 500kHz. The IC has both UGATE and LGATE driving
 Core Voltage Supplies for Desktop, Motherboard CPU
circuits for synchronous rectified DC/DC converter
 High Frequency Low Profile DC/DC Converters
applications. The shoot through protection mechanism is
 High Current Low Voltage DC/DC Converters
designed to prevent shoot through between high-side and
 Core Voltage Supplies for GFX Card
low-side power MOSFETs. The RT9624F has tri-state
PWM input with shutdown function, which can force driver
to output low UGATE and LGATE signals. Ordering Information
RT9624F
The RT9624F is available in a small footprint WDFN-8L
3x3 package. Package Type
QW : WDFN-8L 3x3 (W-Type)
Lead Plating System
Marking Information G : Green (Halogen Free and Pb Free)
4P= : Product Code Note :
4P=YM YMDNN : Date Code Richtek products are :
DNN  RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
 Suitable for use in SnPb or Pb-free soldering processes.
Simplified Application Circuit
RT9624F VIN
R1 R2
12V VCC BOOT C5 C6
C1 CBOOT
UGATE Q1
R3 L1
PWM PHASE VOUT
PWM
+
Controller R5
R4 C3 C4
GND LGATE Q2
C2
Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
DS9624F-02 July 2015 www.richtek.com

1
RT9624F
Pin Configurations
(TOP VIEW)
PWM 1 8 BOOT
GND
GND 2 7 UGATE
NC 3 6 PHASE
VCC 4 9 5 LGATE
WDFN-8L 3x3
Function Pin Description

Pin No. Pin Name Pin Function
1 PWM PWM Signal Input. Connect this pin to the PWM output of the controller.
2, Ground. The exposed pad must be soldered to a large PCB and connected to
GND
9 (Exposed Pad) GND for maximum power dissipation.
3 NC No Internal Connection.
4 VCC Supply Voltage Input.
Low-Side Gate Driver Output. Connect this pin to the Gate of low-side power
5 LGATE
N-MOSFET.
Connect this pin to the Source of the high-side N-MOSFET and the Drain of the
6 PHASE
low-side N-MOSFET.
High-Side Gate Drive Output. Connect this pin to the Gate of high-side power
7 UGATE
N-MOSFET.
8 BOOT Bootstrap Supply for High-Side Gate Drive.
Function Block Diagram

VCC
Bootstrap
POR Control
Internal BOOT
VDD
Shoot-Through
UGATE
Protection
Tri-State
PWM
Detect Turn Off
PHASE
Detection
VCC
Shoot-Through
Protection LGATE
GND
www.richtek.com DS9624F-02 July 2015

2
RT9624F
Operation
POR (Power On Reset) Turn-Off Detection
The POR block detects the voltage the VCC pin. When The turn-off detection block detects whether high-side
the VCC pin voltage is higher than POR rising threshold, MOSFET is turned off by monitoring the PHASE pin
the POR block output is high. The POR output is low voltage. To avoid shoot through between high-side and
when VCC is not less than POR rising threshold. When low-side MOSFETs, low-side MOSFET can be turned on
the POR block output is high, UGATE and LGATE can be only after high-side MOSFET is effectively turned off.
controlled by PWM input voltage. If the POR block output
is low, both UGATE and LGATE will be pulled to low. Shoot-Through Protection
The shoot-through protection block implements the dead
Tri-State Detect time when both high-side and low-side MOSFETs are
When both POR block output and EN pin voltages are turned off. With shoot-through protection block, high-side
high, UGATE and LGATE can be controlled by PWM input. and low-side MOSFET are never turned on simultaneously.
There are three PWM input modes, which are high, low, Thus, shoot through between high-side and low-side
and shutdown state. If PWM input is within the shutdown MOSFETs is prevented.
window, both UGATE and LGATE output are low. When
PWM input is higher than its rising threshold, UGATE is
high and LGATE is low. When PWM input is lower than
its falling threshold, UGATE is low and LGATE is high.
Bootstrap Control
The Bootstrap control block controls the integrated
bootstrap switch. When LGATE is high (low-side MOSFET
is turned on), the bootstrap switch is turned on to charge
the bootstrap capacitor connected to BOOT pin. When
LGATE is low (low-side MOSFET is turned off), the
bootstrap switch is turned off to disconnect VCC pin and
BOOT pin.

3
RT9624F
Absolute Maximum Ratings (Note 1)
 Supply Voltage, VCC -------------------------------------------------------------------------------- −0.3V to 15V
 BOOT to PHASE ------------------------------------------------------------------------------------- −0.3V to 15V
 PHASE to GND
DC -------------------------------------------------------------------------------------------------------- −0.3V to 30V
< 100ns ------------------------------------------------------------------------------------------------- −10V to 35V
 LGATE to GND
DC -------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)
< 100ns ------------------------------------------------------------------------------------------------- −2V to (VCC + 0.3V)
 UGATE to GND
DC -------------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V)
< 100ns ------------------------------------------------------------------------------------------------- (VPHASE − 2V) to (VBOOT + 0.3V)
 PWM to GND ------------------------------------------------------------------------------------------ −0.3V to 7V
 Power Dissipation, PD @ TA = 25°C
WDFN-8L 3x3 ----------------------------------------------------------------------------------------- 3.22W
 Package Thermal Resistance (Note 2)
WDFN-8L 3x3, θJA ------------------------------------------------------------------------------------ 31°C/W
WDFN-8L 3x3, θJC ------------------------------------------------------------------------------------ 8°C/W
 Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------- 260°C
 Junction Temperature -------------------------------------------------------------------------------- 150°C
 Storage Temperature Range ----------------------------------------------------------------------- −65°C to 150°C
 ESD Susceptibility (Note 3)
HBM (Human Body Model) ------------------------------------------------------------------------- 2kV
Recommended Operating Conditions (Note 4)

 Supply Voltage, VCC -------------------------------------------------------------------------------- 4.5V to 13.2V
 Input Voltage, (VIN + VCC) ------------------------------------------------------------------------- < 35V
 Junction Temperature Range ----------------------------------------------------------------------- −40°C to 125°C
 Ambient Temperature Range ----------------------------------------------------------------------- −40°C to 85°C

4
RT9624F
Electrical Characteristics
(VCC = 12V, TA = 25°C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Power Supply
Power Supply Voltage VCC 4.5 -- 13.2 V
Power Supply Current IVCC VBOOT = 12V, PWM Input Floating -- 120 -- A
Power On Reset (POR)
POR Rising Threshold VPOR_r VCC Rising -- 4 4.4 V
POR Falling Threshold VPOR_ f VCC Falling 3 3.5 -- V
PWM Input
Maximum Input Current IPWM PWM = 0V or 5V -- 160 -- A
PWM Floating Voltage VPWM_fl PWM = Open -- 1.8 -- V
PWM Rising Threshold VPWM_rth 2.3 2.8 3.2 V
PWM Falling Threshold VPWM_fth 0.7 1.1 1.4 V
Timing
UGATE Rising Time tUGATEr 3nF Load -- 25 -- ns
UGATE Falling Time tUGATEf 3nF Load -- 12 -- ns
LGATE Rising Time tLGATEr 3nF Load -- 24 -- ns
LGATE Falling Time tLGATEf 3nF Load -- 10 -- ns
tUGATEpdh VBOOT  VPHASE = 12V -- 60 --
UGATE Propagation Delay ns
tUGATEpdl See Timing Diagram -- 22 --
tLGATEpdh See Timing Diagram -- 30 --
LGATE Propagation Delay ns
tLGATEpdl See Timing Diagram -- 8 --
Output
UGATE Drive Source RUGATEsr VBOOT  VPHASE = 12V, ISource = 100mA -- 1.7 -- 
UGATE Drive Sink RUGATEsk VBOOT  VPHASE = 12V, ISink = 100mA -- 1.4 -- 
LGATE Drive Source RLGATEsr ISource = 100mA -- 1.6 -- 
LGATE Drive Sink RLGATEsk ISink = 100mA -- 1.1 -- 
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

5
RT9624F
Typical Application Circuit
R1 RT9624F R2
2.2 1 VIN
4 VCC
12V BOOT 8 CBOOT 12V
1µF C5 C6
C1 R3 1000µF 10µF
1µF x3 x4
7 2.2
UGATE Q1 L1
1µH
PWM 1 6 VOUT
PWM PHASE
Controller
+
R4 R5
0 2.2 C3 C4
2, 9 (Exposed Pad) 5 2200µF 10µF
GND LGATE Q2
C2 x2 x2
3.3nF
Timing Diagram
PWM
tLGATEpdl
LGATE 90%
tUGATEpdl
1.5V 1.5V
90%
1.5V 1.5V
UGATE
tUGATEpdh tLGATEpdh

6
RT9624F
Typical Operating Characteristics
PWM Rising Edge PWM Falling Edge
PWM PWM
(10V/Div) (10V/Div)
UGATE UGATE
(20V/Div) (20V/Div)
LGATE LGATE
(10V/Div) (10V/Div)
PHASE PHASE
(10V/Div) (10V/Div)
Time (20ns/Div) Time (20ns/Div)
Dead Time Dead Time
UGATE UGATE
PHASE PHASE
LGATE LGATE
(5V/Div) (5V/Div)
Full Load Full Load
Dead Time Dead Time
UGATE UGATE
PHASE PHASE
LGATE LGATE
(5V/Div) (5V/Div)
No Load No Load

7
RT9624F
Short Pulse
UGATE
LGATE PHASE
(5V/Div)
UGATE − PHASE
No Load
Time (20ns/Div)

8
RT9624F
Application Information
The RT9624F is a high frequency, synchronous rectified, Internal Bootstrap Power Switch
single phase dual MOSFET driver containing Richtek's The RT9624F builds in an internal bootstrap power switch
advanced MOSFET driver technologies. The RT9624F is to replace external bootstrap diode, and this can facilitate
designed to be able to adapt from normal MOSFET driving PCB design and reduce total BOM cost of the system.
applications to high performance CPU VR driving Hence, no external bootstrap diode is required in real
capabilities. applications.
Supply Voltage and Power On Reset Non-overlap Control

The RT9624F can be utilized under both VCC = 5V or VCC To prevent the overlap of the gate drivers during the UGATE
= 12V applications which may happen in different fields of pull low and the LGATE pull high, the non-overlap circuit
electronics application circuits. In terms of efficiency, monitors the voltages at the PHASE node and high-side
higher VCC equals higher driving voltage of UGATE/LGATE gate drive (UGATE-PHASE). When the PWM input signal
which may result in higher switching loss and lower goes low, UGATE begins to pull low (after propagation
conduction loss of power MOSFETs. The choice of VCC = delay). Before LGATE is pulled high, the non-overlap
12V or VCC = 5V can be a tradeoff to optimize system protection circuit ensures that the monitored voltages have
efficiency. gone below 1.1V. Once the monitored voltages fall below
The RT9624F is designed to drive both high-side and low- 1.1V, LGATE begins to turn high. By waiting for the
side N-MOSFET through external input PWM control voltages of the PHASE pin and high-side gate driver to fall
signal. It has power on protection function which held below 1.1V, the non-overlap protection circuit ensures that
UGATE and LGATE low before the VCC voltage rises to UGATE is low before LGATE pulls high.
higher than rising threshold voltage. Also to prevent the overlap of the gate drivers during
LGATE pull low and UGATE pull high, the non-overlap
Tri-state PWM Input
circuit monitors the LGATE voltage. When LGATE goes
After the initialization, the PWM signal takes the control. below 1.1V, UGATE goes high after propagation delay.
The rising PWM signal first forces the LGATE signal to
turn low then UGATE signal is allowed to go high just Driving Power MOSFETs
after a non-overlapping time to avoid shoot through current. The DC input impedance of the power MOSFET is
The falling of PWM signal first forces UGATE to go low. extremely high. When Vgs1 or Vgs2 is at 12V or 5V, the
When UGATE and PHASE signal reach a predetermined gate draws the current only for few nano-amperes. Thus
low level, LGATE signal is allowed to turn high. once the gate has been driven up to “ON” level, the
The PWM signal is acted as “High” if the signal is above current could be negligible.
the rising threshold and acted as “Low” if the signal is However, the capacitance at the gate to source terminal
below the falling threshold. When PWM signal level enters should be considered. It requires relatively large currents
and remains within the shutdown window, the output drivers to drive the gate up and down 12V (or 5V) rapidly. It is
are disabled and both MOSFET gates are pulled and held also required to switch drain current on and off with the
low. If the PWM signal is left floating, the pin will be kept required speed. The required gate drive currents are
around 1.8V by the internal divider and provide the PWM calculated as follows.
controller with a recognizable level.

9
RT9624F
D1 dV 12
Igd1 = Cgd1 = Cgd1 (3)
d1 s1 VPHASE L dt tr1
VIN VOUT
Cgd1 Cgs1 Before the low-side MOSFET is turned on, the Cgd2 have
been charged to VIN. Thus, as Cgd2 reverses its polarity
Igd1 Igs1 Cgd2 d2 and g2 is charged up to 12V, the required current is
Ig1 dV VIN  12
Ig2 Igd2 Igd2  Cgd2  Cgd2 (4)
g1 g2 D2 dt tr2
Igs2
It is helpful to calculate these currents in a typical case.
Cgs2 s2
Assume a synchronous rectified Buck converter, input
GND voltage VIN = 12V, Vgs1 = 12V, Vgs2 = 12V. The high-side
Vg1
MOSFET is PHB83N03LT whose C iss = 1660pF,
VPHASE +12V
Crss = 380pF, and tr = 14ns. The low-side MOSFET is
PHB95N03LT whose Ciss = 2200pF, Crss = 500pF and
tr = 30ns, from the equation (1) and (2) we can obtain
1660 x 10-12 x 12
t Igs1   1.428 (A) (5)
Vg2
12V 14 x 10-9
2200 x 10-12 x 12
Igs2   0.88 (A) (6)
t 30 x 10-9
Figure 1. Equivalent Circuit and Waveforms (VCC = 12V) from equation. (3) and (4)
In Figure 1, the current Ig1 and Ig2 are required to move the 380 x 10-12 x 12
Igd1   0.326 (A) (7)
gate up to 12V. The operation consists of charging Cgd1, 14 x 10-9
Cgd2 , Cgs1 and Cgs2. Cgs1 and Cgs2 are the capacitors from
500 x 10-12 x 12+12 
gate to source of the high-side and the low-side power Igd2   0.4 (A) (8)
MOSFETs, respectively. In general data sheets, the Cgs1 30 x 10-9
and C gs2 are referred as “Ciss” which are the input the total current required from the gate driving source can
capacitors. Cgd1 and Cgd2 are the capacitors from gate to be calculated as the following equations.
drain of the high-side and the low-side power MOSFETs, Ig1  Igs1  Igd1  1.428  0.326   1.754 (A) (9)
respectively and referred to the data sheets as “Crss” the
reverse transfer capacitance. For example, tr1 and tr2 are Ig2  Igs2  Igd2   0.88  0.4   1.28 (A) (10)
the rising time of the high-side and the low-side power
MOSFETs respectively, the required current Igs1 and Igs2, By a similar calculation, we can also get the sink current
are shown as below : required from the turned off MOSFET.
dVg1 Cgs1 x 12
Igs1  Cgs1  (1) Select the Bootstrap Capacitor
dt tr1
Figure 2 shows part of the bootstrap circuit of the RT9624F.
dVg2 Cgs1 x 12 The VCB (the voltage difference between BOOT and
Igs2  Cgs1  (2)
dt tr2 PHASE on RT9624F) provides a voltage to the gate of the
Before driving the gate of the high-side MOSFET up to high-side power MOSFET. This supply needs to be
12V, the low-side MOSFET has to be off; and the high- ensured that the MOSFET can be driven. For this, the
side MOSFET will be turned off before the low-side is capacitance CBOOT has to be selected properly. It is
turned on. From Figure 1, the body diode “D2” will be determined by the following constraints.
turned on before high-side MOSFETs turn on.

10
RT9624F
VIN Figure 4 shows the power dissipation of the RT9624F as
BOOT a function of frequency and load capacitance when VCC =
+
12V. The value of CU and CL are the same and the frequency
CBOOT
UGATE is varied from 100kHz to 1MHz.
VCB
PHASE - Power Dissipation vs. Frequency
1000
VCC
900
LGATE CU = CL = 3nF
Power Dissipation (mW)

800
GND 700
600
CU = CL = 2nF
500
Figure 2. Part of Bootstrap Circuit of RT9624F
400
300
In practice, a low value capacitor CBOOT will lead to the CU = CL = 1nF
200
over charging that could damage the IC. Therefore, to
100
minimize the risk of overcharging and to reduce the ripple VCC = 12V
0
on VCB, the bootstrap capacitor should not be smaller than 0 200 400 600 800 1000
0.1μF, and the larger the better. In general design, using Frequency (kHz)
1μF can provide better performance. At least one low-ESR Figure 4. Power Dissipation vs. Frequency
capacitor should be used to provide good local de-coupling.
The operating junction temperature can be calculated from
It is recommended to adopt a ceramic or tantalum
the power dissipation curves (Figure 4). Assume
capacitor.
VCC = 12V, operating frequency is 200kHz and CU = CL =
Power Dissipation 1nF which emulate the input capacitances of the high-
To prevent driving the IC beyond the maximum side and low-side power MOSFETs. From Figure 4, the
recommended operating junction temperature of 125°C, power dissipation is 100mW. Thus, for example, the
it is necessary to calculate the power dissipation package thermal resistance θJA is 120°C/W. The operating
appropriately. This dissipation is a function of switching junction temperature is then calculated as :
frequency and total gate charge of the selected MOSFET. TJ = (120°C/W x 100mW) + 25°C = 37°C (11)
Figure 3 shows the power dissipation test circuit. CL and where the ambient temperature is 25°C.
C U are the UGATE and LGATE load capacitors,
respectively. The bootstrap capacitor value is 1μF. Thermal Considerations
CBOOT For continuous operation, do not exceed absolute
1µF
12V maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
10 BOOT package, PCB layout, rate of surrounding airflow, and
12V VCC UGATE 2N7002
difference between junction and ambient temperature. The
1µF CU
RT9624F 3nF
maximum power dissipation can be calculated by the
PHASE following formula :
2N7002
PWM PWN PD(MAX) = (TJ(MAX) − TA) / θJA
LGATE 20
GND CL where TJ(MAX) is the maximum junction temperature, TA is
3nF
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
Figure 3. Power Dissipation Test Circuit

11
RT9624F
For recommended operating condition specifications, the Layout Consideration
maximum junction temperature is 125°C. The junction to Figure 6 shows the schematic circuit of a synchronous
ambient thermal resistance, θJA, is layout dependent. For Buck converter to implement the RT9624F. The converter
WDFN-8L 3x3 package, the thermal resistance, θJA, is operates from 5V to 12V of input Voltage.
31°C/W on a standard JEDEC 51-7 four-layer thermal test
For the PCB layout, it should be very careful. The power
board. The maximum power dissipation at TA = 25°C can
circuit section is the most critical one. If not configured
be calculated by the following formulas :
properly, it will generate a large amount of EMI. The location
P D(MAX) = (125°C − 25°C) / (31°C/W) = 3.22W for of Q1, Q2, L1 should be very close.
WDFN-8L 3x3 package
Next, the trace from UGATE, and LGATE should also be
The maximum power dissipation depends on the operating short to decrease the noise of the driver output signals.
ambient temperature for fixed T J(MAX) and thermal PHASE signals from the junction of the power MOSFET,
resistance, θJA. The derating curve in Figure 5 allow the carrying the large gate drive current pulses, should be as
designer to see the effect of rising ambient temperature heavy as the gate drive trace. The bypass capacitor C1
on the maximum power dissipation. should be connected to GND directly. Furthermore, the
3.5 bootstrap capacitors (CBOOT) should always be placed as
Maximum Power Dissipation (W)1
Four-Layer PCB
close to the pins of the IC as possible.
3.0
VIN
2.5 12V
L2
12V
2.0
+
C6
C5 R1
1.5 BOOT
CBOOT VCC
1.0 C1
VCORE Q1 UGATE
RT9624F
L1
0.5
PHASE PWM PWM
PHB83N03LT
+
0.0 C3
0 25 50 75 100 125 Q2 PHB95N03LT LGATE GND
Ambient Temperature (°C)
Figure 5. Derating Curve of Maximum Power Dissipation

Figure 6. Synchronous Buck Converter Circuit

12
RT9624F
Outline Dimension
D2
D
E E2
SEE DETAIL A
1
e
b 2 1 2 1
A
A3
A1 DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.
Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.200 0.300 0.008 0.012
D 2.950 3.050 0.116 0.120
D2 2.100 2.350 0.083 0.093
E 2.950 3.050 0.116 0.120
E2 1.350 1.600 0.053 0.063
e 0.650 0.026
L 0.425 0.525 0.017 0.021
W-Type 8L DFN 3x3 Package
Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

13

RT9624F Richtek

Uploaded by

Copyright:

Available Formats

RT9624F Richtek

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

RT9624F Richtek

Uploaded by

Copyright:

Available Formats

®

Simplified Application Circuit

DS9624F-02 July 2015 www.richtek.com

Function Pin Description

Function Block Diagram

www.richtek.com DS9624F-02 July 2015

DS9624F-02 July 2015 www.richtek.com

Recommended Operating Conditions (Note 4)

www.richtek.com DS9624F-02 July 2015

DS9624F-02 July 2015 www.richtek.com

www.richtek.com DS9624F-02 July 2015

Time (20ns/Div) Time (20ns/Div)

Dead Time Dead Time

Full Load Full Load

Time (20ns/Div) Time (20ns/Div)

Dead Time Dead Time

Time (20ns/Div) Time (20ns/Div)

DS9624F-02 July 2015 www.richtek.com

www.richtek.com DS9624F-02 July 2015

Supply Voltage and Power On Reset Non-overlap Control

DS9624F-02 July 2015 www.richtek.com

www.richtek.com DS9624F-02 July 2015

Power Dissipation (mW)

DS9624F-02 July 2015 www.richtek.com

Figure 5. Derating Curve of Maximum Power Dissipation

www.richtek.com DS9624F-02 July 2015

Note : The configuration of the Pin #1 identifier is optional,

Dimensions In Millimeters Dimensions In Inches

W-Type 8L DFN 3x3 Package

Richtek Technology Corporation

DS9624F-02 July 2015 www.richtek.com

You might also like