3A, 18V, 340Khz Synchronous Step-Down Converter: General Description Features

®
RT7257A
3A, 18V, 340kHz Synchronous Step-Down Converter

General Description Features
The RT7257A is a high efficiency, monolithic synchronous z ±1.5% High Accuracy Reference Voltage
step-down DC/DC converter that can deliver up to 3A z 4.5V to 18V Input Voltage Range
output current from a 4.5V to 18V input supply. The z 3A Output Current
RT7257A's current mode architecture and external z Integrated N-MOSFET Switches
compensation allow the transient response to be z Current Mode Control
optimized over a wide input range and loads. Cycle-by- z Fixed Frequency Operation : 340kHz
cycle current limit provides protection against shorted z Output Adjustable from 0.8V to 15V
outputs, and soft-start eliminates input current surge during z Up to 95% Efficiency
start-up. The RT7257A also provides under voltage z Programmable Soft-Start
protection and thermal shutdown protection. The low z Stable with Low ESR Ceramic Output Capacitors
current (<3μA) shutdown mode provides output z Cycle-by-Cycle Over Current Protection
disconnection, enabling easy power management in z Input Under Voltage Lockout
battery-powered systems. The RT7257A is available in z Output Under Voltage Protection
an SOP-8 (Exposed Pad) package. z Thermal Shutdown Protection
z RoHS Compliant and Halogen Free
Ordering Information
RT7257A Applications
z Wireless AP/Router
Package Type
SP : SOP-8 (Exposed Pad-Option 1) z Set-Top-Box
Lead Plating System z Industrial and Commercial Low Power Systems
Z : ECO (Ecological Element with z LCD Monitors and TVs
Halogen Free and Pb free) z Green Electronics/Appliances
H : UVP Hiccup z Point of Load Regulation of High-Performance DSPs
L : UVP Latch-Off
Note : Pin Configurations
Richtek products are : (TOP VIEW)
` RoHS compliant and compatible with the current require-
BOOT 8 SS
ments of IPC/JEDEC J-STD-020.
VIN 2 7 EN
GND
` Suitable for use in SnPb or Pb-free soldering processes. SW 3 6 COMP
9
GND 4 5 FB
Marking Information SOP-8 (Exposed Pad)

RT7257AxZSP : Product Number
RT7257Ax x : H or L
ZSPYMDNN
YMDNN : Date Code
Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
DS7257A-03 December 2012 www.richtek.com

1
RT7257A
Typical Application Circuit
VIN 2 1
VIN BOOT
4.5V to 18V CIN CBOOT L
10µF x 2 RT7257A 0.1µF 10µH
VOUT
SW 3
3.3V
REN 100k 7 EN R1
75k
8 SS COUT
FB 5 22µF x 2
CSS CC RC
4.7nF R2
0.1µF 4, 9 (Exposed Pad) 6 12k 24k
GND COMP
CP
Open
Table 1. Suggested Components Selection

VOUT (V) R1 (kΩ) R2 (kΩ) R C (kΩ) CC (nF) L (μH) COUT (μF)
8 27 3 24 4.7 22 22 x 2
5 62 11.8 18 4.7 15 22 x 2
3.3 75 24 12 4.7 10 22 x 2
2.5 25.5 12 8.2 4.7 6.8 22 x 2
1.5 10.5 12 3.6 4.7 3.6 22 x 2
1.2 12 24 3 4.7 3.6 22 x 2
1 3 12 2.7 4.7 3.6 22 x 2
Functional Pin Description

Pin No. Pin Name Pin Function
Bootstrap for High Side Gate Driver. Connect a 0.1μF or greater ceramic
1 BOOT
capacitor from BOOT to SW pins.
Input Supply Voltage, 4.5V to 18V. Must bypass with a suitable large ceramic
2 VIN
capacitor.
3 SW Switch Node. Connect this pin to an external L-C filter.
4, Ground. The exposed pad must be soldered to a large PCB and connected to
GND
9 (Exposed Pad) GND for maximum power dissipation.
Feedback Input. It is used to regulate the output of the converter to a set value
5 FB
via an external resistive voltage divider.
Compensation Node. COMP is used to compensate the regulation control
6 COMP loop. Connect a series RC network from COMP to GND. In some cases, an
additional capacitor from COMP to GND is required.
Enable Input Pin. A logic high enables the converter; a logic low forces the
7 EN RT7257A into shutdown mode reducing the supply current to less than 3μA.
Attach this pin to VIN with a 100kΩ pull up resistor for automatic startup.
Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor
8 SS from SS to GND to set the soft-start period. A 0.1μF capacitor sets the
soft-start period to 13.5ms.
www.richtek.com DS7257A-03 December 2012

2
RT7257A
Function Block Diagram
VIN
Internal
Regulator Oscillator
Current Sense
Shutdown Slope Comp Amplifier
Comparator VA VCC +
Foldback RSENSE VA
1.2V + Control -
-
0.4V + BOOT
Lockout -
Comparator UV S Q 110mΩ
5kΩ Comparator SW
EN - +
R Q 90mΩ
2.5V + -
Current GND
Comparator
VCC
6µA
0.8V +
SS +EA
-
FB COMP

3
RT7257A
Absolute Maximum Ratings (Note 1)
z Supply Input Voltage, VIN ----------------------------------------------------------------------------------------- −0.3V to 20V
z Switch Voltage, SW ------------------------------------------------------------------------------------------------ −0.3V to (VIN + 0.3V)
<10ns ------------------------------------------------------------------------------------------------------------------ −5V to 25V
z VBOOT − VSW ---------------------------------------------------------------------------------------------------------- −0.3V to 6V
z Other Pins Voltage ------------------------------------------------------------------------------------------------- −0.3V to 20V
z Power Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) --------------------------------------------------------------------------------------------- 1.333W
z Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------------- 75°C/W
SOP-8 (Exposed Pad), θJC --------------------------------------------------------------------------------------- 15°C/W
z Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------- 260°C
z Junction Temperature ----------------------------------------------------------------------------------------------- 150°C
z Storage Temperature Range -------------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions (Note 4)

z Supply Input Voltage, VIN ----------------------------------------------------------------------------------------- 4.5V to 18V
z Junction Temperature Range -------------------------------------------------------------------------------------- −40°C to 125°C
z Ambient Temperature Range -------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 12V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Shutdown Supply Current VEN = 0V -- 0.5 3 μA
Supply Current VEN = 3 V, VFB = 0.9V -- 0.8 1.2 mA
Reference Voltage VREF 4.5V ≤ VIN ≤ 18V 0.788 0.8 0.812 V
Error Amplifier
GEA ΔIC = ±10μA -- 940 -- μA/V
Transconductance
High Side Switch
RDS(ON)1 -- 110 -- mΩ
On-Resistance
Low Side Switch
RDS(ON)2 -- 90 -- mΩ
On-Resistance
High Side Switch Leakage
VEN = 0V, VSW = 0V -- 0 10 μA
Current
Upper Switch Current Limit Min. Duty Cycle, VBOOT − VSW = 4.8V -- 5.1 -- A
COMP to Current Sense
GCS -- 4.7 -- A/V
Transconductance
Oscillation Frequency fOSC1 300 340 380 kHz
Short Circuit Oscillation
fOSC2 VFB = 0V -- 100 -- kHz
Frequency
Maximum Duty Cycle DMAX VFB = 0.7V -- 93 -- %
Minimum On Time tON -- 100 -- ns

4
RT7257A
Parameter Symbol Test Conditions Min Typ Max Unit
Logic-High VIH 2.7 -- 18
EN Input Voltage V
Logic-Low VIL -- -- 0.4
Input Under Voltage Lockout Threshold VUVLO VIN Rising 3.8 4.2 4.5 V
Input Under Voltage Lockout Hysteresis ΔVUVLO -- 320 -- mV
Soft-Start Current ISS VSS = 0V -- 6 -- μA
Soft-Start Period tSS CSS = 0.1μF -- 13.5 -- ms
Thermal Shutdown TSD -- 150 -- °C
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

5
RT7257A
Typical Operating Characteristics
Efficiency vs. Load Current Output Voltage vs. Input Voltage
100 3.34
90 3.33
80 VIN = 4.5V 3.32
Output Voltage (V)

70 VIN = 12V
Efficiency (%)
VIN = 17V 3.31

60
50 3.30
40 3.29
30
3.28
20
10 3.27
VOUT = 3.3V VIN = 4.5V to 17V, VOUT = 3.3V, IOUT = 1A
0 3.26
0.01 0.1 1 10 4 6 8 10 12 14 16 18
Load Current (A) Input Voltage (V)
Output Voltage vs. Temperature Output Voltage vs. Output Current

3.34 3.50
3.33 3.45
3.32
Output Voltage (V)
3.40
Output Voltage (V)
VIN = 4.5V
3.31 3.35 VIN = 12V
VIN = 17V
3.30 3.30
3.29 3.25
3.28 3.20
3.27 3.15
VIN = 12V, VOUT = 3.3V, IOUT = 1A VOUT = 3.3V
3.26 3.10
-50 -25 0 25 50 75 100 125 0 0.5 1 1.5 2 2.5 3
Temperature (°C) Output Current (A)
Switching Frequency vs. Input Voltage Switching Frequency vs. Temperature

380 370
Switching Frequency (kHz)1
370
Switching Frequency (kHz)1
360
360
350
350
340
340
330
330
320
320
310 310
VOUT = 3.3V, IOUT = 0.5A VIN = 12V, VOUT = 3.3V, IOUT = 0.5A
300 300
4.5 7 9.5 12 14.5 17 -50 -25 0 25 50 75 100 125
Input Voltage (V) Temperature (°C)

6
RT7257A
Current Limit vs. Temperature Load Transient Response

8
7
VOUT
(100mV/Div)
Current Limit (A)
4
IOUT
(2A/Div)
3
VIN = 12V, VOUT = 3.3V VIN = 12V, VOUT = 3.3V, IOUT = 0.2A to 3A
2
-50 -25 0 25 50 75 100 125 Time (250μs/Div)
Temperature (°C)
Load Transient Response Switching
VOUT
(10mV/Div)
VOUT
(100mV/Div)
VSW
(10V/Div)
IOUT
(2A/Div)
IL
VIN = 12V, VOUT = 3.3V, IOUT = 1.5A to 3A (2A/Div) VIN = 12V, VOUT = 3.3V, IOUT = 3A
Time (250μs/Div) Time (1μs/Div)
Power On from VIN Power Off from VIN
VIN VIN
(5V/Div) (5V/Div)
VOUT VOUT
(2V/Div) (2V/Div)
IL IL
(2A/Div) VIN = 12V, VOUT = 3.3V, IOUT = 3A (2A/Div) VIN = 12V, VOUT = 3.3V, IOUT = 3A
Time (5ms/Div) Time (5ms/Div)

7
RT7257A
Power On from EN Power Off from EN
VEN VEN
(5V/Div) (5V/Div)
VOUT VOUT
(2V/Div) (2V/Div)
IL IL
(2A/Div) (2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (5ms/Div) Time (5ms/Div)

8
RT7257A
Application Information
Output Voltage Setting Soft-Start
The resistive divider allows the FB pin to sense the output The RT7257A provides soft-start function. The soft-start
voltage as shown in Figure 1. function is used to prevent large inrush current while
VOUT converter is being powered-up. The soft-start timing can
be programmed by the external capacitor between SS and
R1 GND. An internal current source ISS (6μA) charges an
FB external capacitor to build a soft-start ramp voltage. The
RT7257A R2 VFB voltage will track the internal ramp voltage during soft-
GND start interval. The typical soft start time is calculated as
follows :
Figure 1. Output Voltage Setting 0.8 × CSS
Soft-Start time tSS = , if CSS capacitor
ISS
0.8 × 0.1μ
The output voltage is set by an external resistive voltage is 0.1μF, then soft-start time = ≒ 13.5ms
divider according to the following equation : 6μ
VOUT = VREF ⎛⎜ 1+ R1 ⎞⎟ Chip Enable Operation

⎝ R2 ⎠
The EN pin is the chip enable input. Pulling the EN pin
Where VREF is the reference voltage (0.8V typ.).
low (<0.4V) will shutdown the device. During shutdown
mode, the RT7257A quiescent current drops to lower than
External Bootstrap Diode
3μA. Driving the EN pin high (>2.5V, < 18V) will turn on
Connect a 0.1μF low ESR ceramic capacitor between the the device again. For external timing control, the EN pin
BOOT pin and SW pin. This capacitor provides the gate can also be externally pulled high by adding a REN resistor
driver voltage for the high side MOSFET. and CEN capacitor from the VIN pin (see Figure 3).
It is recommended to add an external bootstrap diode EN
REN
between an external 5V and BOOT pin for efficiency VIN EN
improvement when input voltage is lower than 5.5V or duty RT7257A
CEN
ratio is higher than 65% .The bootstrap diode can be a
GND
low cost one such as IN4148 or BAT54. The external 5V
can be a 5V fixed input from system or a 5V output of the Figure 3. Enable Timing Control
RT7257A. Note that the external boot voltage must be
An external MOSFET can be added to implement digital
lower than 5.5V
5V
control on the EN pin when no system voltage above 2.5V
is available, as shown in Figure 4. In this case, a 100kΩ
pull-up resistor, REN, is connected between VIN and the
BOOT EN pin. MOSFET Q1 will be under logic control to pull
RT7257A 100nF down the EN pin.
SW REN
100k
VIN EN
EN Q1 RT7257A
Figure 2. External Bootstrap Diode
GND
Figure 4. Digital Enable Control Circuit

9
RT7257A
Under Voltage Protection Over Temperature Protection
The RT7257A features an Over Temperature Protection
Hiccup Mode
(OTP) circuitry to prevent from overheating due to
For the RT7257AH, it provides Hiccup Mode Under Voltage
excessive power dissipation. The OTP will shut down
Protection (UVP). When the VFB voltage drops below 0.4V,
switching operation when junction temperature exceeds
the UVP function will be triggered to shut down switching
150°C. Once the junction temperature cools down by
operation. If the UVP condition remains for a period, the
approximately 20°C, the converter will resume operation.
RT7257AH will retry automatically. When the UVP
To maintain continuous operation, the maximum junction
condition is removed, the converter will resume operation.
temperature should be lower than 125°C.
The UVP is disabled during soft-start period.
Hiccup Mode Inductor Selection
The inductor value and operating frequency determine the
ripple current according to a specific input and output
voltage. The ripple current ΔIL increases with higher VIN
VOUT
(2V/Div) and decreases with higher inductance.
ΔIL = ⎡⎢ OUT ⎤⎥ × ⎡⎢1− OUT ⎤⎥
V V
⎣ f ×L ⎦ ⎣ VIN ⎦
Having a lower ripple current reduces not only the ESR
ILX
losses in the output capacitors but also the output voltage
(2A/Div)
ripple. High frequency with small ripple current can achieve
IOUT = Short the highest efficiency operation. However, it requires a
large inductor to achieve this goal.
Time (50ms/Div)
Figure 5. Hiccup Mode Under Voltage Protection For the ripple current selection, the value of ΔIL = 0.24(IMAX)
will be a reasonable starting point. The largest ripple
Latch-Off Mode current occurs at the highest VIN. To guarantee that the
For the RT7257AL, it provides Latch-Off Mode Under ripple current stays below the specified maximum, the
Voltage Protection (UVP). When the FB voltage drops inductor value should be chosen according to the following
below half of the feedback reference voltage, VFB, UVP equation :
will be triggered and the RT7257AL will shutdown in Latch- ⎡ VOUT ⎤ ⎡ VOUT ⎤
L =⎢
f × Δ I ⎥ × ⎢1 − VIN(MAX) ⎥
Off Mode. In shutdown condition, the RT7257AL can be ⎣ L(MAX) ⎦ ⎣ ⎦
reset by EN pin or power input VIN.
The inductor's current rating (caused a 40°C temperature
Latch-Off Mode
rising from 25°C ambient) should be greater than the
maximum load current and its saturation current should
be greater than the short circuit peak current limit. Please
VOUT see Table 2 for the inductor selection reference.
(2V/Div)
Table 2. Suggested Inductors for Typical
Application Circuit
Component Dimensions
ILX Series
Supplier (mm)
(2A/Div)
TDK VLF10045 10 x 9.7 x 4.5
IOUT = Short TDK SLF12565 12.5 x 12.5 x 6.5
TAIYO
Time (250μs/Div) NR8040 8x8x4
YUDEN
Figure 6. Latch-Off Mode Under Voltage Protection

10
RT7257A
CIN and COUT Selection Thermal Considerations
The input capacitance, C IN, is needed to filter the For continuous operation, do not exceed the maximum
trapezoidal current at the source of the high side MOSFET. operation junction temperature 125°C. The maximum
To prevent large ripple current, a low ESR input capacitor power dissipation depends on the thermal resistance of
sized for the maximum RMS current should be used. The IC package, PCB layout, the rate of surroundings airflow
approximate RMS current equation is given : and temperature difference between junction to ambient.
V VIN The maximum power dissipation can be calculated by
IRMS = IOUT(MAX) OUT −1
VIN VOUT following formula :
This formula has a maximum at VIN = 2VOUT, where
PD(MAX) = (TJ(MAX) − TA ) / θJA
IRMS = IOUT / 2. This simple worst case condition is
commonly used for design because even significant Where T J(MAX) is the maximum operation junction
deviations do not offer much relief. temperature , TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
Choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to For recommended operating conditions specification of
meet size or height requirements in the design. RT7257A, the maximum junction temperature is 125°C.
The junction to ambient thermal resistance θJA is layout
For the input capacitor, two 10μF low ESR ceramic
dependent. For SOP-8 (Exposed Pad) package, the
capacitors are suggested. For the suggested capacitor,
thermal resistance θJA is 75°C/W on the standard JEDEC
please refer to Table 3 for more details.
51-7 four-layers thermal test board. The maximum power
The selection of COUT is determined by the required ESR dissipation at TA = 25°C can be calculated by following
to minimize voltage ripple. formula :
Moreover, the amount of bulk capacitance is also a key P D(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
for COUT selection to ensure that the control loop is stable. (min.copper area PCB layout)
Loop stability can be checked by viewing the load transient
P D(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W
response as described in a later section.
(70mm2copper area PCB layout)
The output ripple, ΔVOUT , is determined by :
The thermal resistance θJA of SOP-8 (Exposed Pad) is
ΔVOUT ≤ ΔIL ⎡⎢ESR + 1 ⎤
⎣ 8fCOUT ⎥⎦ determined by the package architecture design and the
The output ripple will be the highest at the maximum input PCB layout design. However, the package architecture
voltage since ΔIL increases with input voltage. Multiple design had been designed. If possible, it's useful to
capacitors placed in parallel may be needed to meet the increase thermal performance by the PCB layout copper
ESR and RMS current handling requirement. Higher values, design. The thermal resistance θJA can be decreased by
lower cost ceramic capacitors are now becoming available adding copper area under the exposed pad of SOP-8
in smaller case sizes. Their high ripple current, high voltage (Exposed Pad) package.
rating and low ESR make them ideal for switching regulator As shown in Figure 7, the amount of copper area to which
applications. However, care must be taken when these the SOP-8 (Exposed Pad) is mounted affects thermal
capacitors are used at input and output. When a ceramic performance. When mounted to the standard
capacitor is used at the input and the power is supplied SOP-8 (Exposed Pad) pad (Figure 7.a), θJA is 75°C/W.
by a wall adapter through long wires, a load step at the Adding copper area of pad under the SOP-8 (Exposed
output can induce ringing at the input, VIN. At best, this Pad) (Figure 7.b) reduces the θJA to 64°C/W. Even further,
ringing can couple to the output and be mistaken as loop increasing the copper area of pad to 70mm2 (Figure 7.e)
instability. At worst, a sudden inrush of current through reduces the θJA to 49°C/W.
the long wires can potentially cause a voltage spike at
VIN large enough to damage the part.

11
RT7257A
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
resistance θJA. The Figure 8 of derating curves allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation allowed.
2.2
2.0
Four-Layer PCB (a) Copper Area = (2.3 x 2.3) mm2, θJA = 75°C/W
1.8
Power Dissipation (W)
1.6 Copper Area

70mm2
1.4
50mm2
1.2 30mm2
1.0 10mm2
Min.Layout
0.8
0.6
0.4
0.2 (b) Copper Area = 10mm2, θJA = 64°C/W
0.0
0 25 50 75 100 125
Ambient Temperature (°C)
Figure 8. Derating Curve of Maximum Power Dissipation
(c) Copper Area = 30mm2 , θJA = 54°C/W
(d) Copper Area = 50mm2 , θJA = 51°C/W
(e) Copper Area = 70mm2 , θJA = 49°C/W
Figure 7. Themal Resistance vs. Copper Area Layout

Design

12
RT7257A
Layout Consideration ` SW node is with high frequency voltage swing and
Follow the PCB layout guidelines for optimal performance should be kept at small area. Keep analog components
of the RT7257A. away from the SW node to prevent stray capacitive noise
pick-up.
` Keep the traces of the main current paths as short and
wide as possible. ` Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
` Put the input capacitor as close as possible to the device
components near the RT7257A.
pins (VIN and GND).
` An example of PCB layout guide is shown in Figure 9
for reference.
GND VIN SW GND VIN The feedback components

must be connected as close
CBOOT REN to the device as possible.
Input capacitor must CSS
CIN CC
be placed as close
BOOT 8 SS
to the IC as possible.
VIN 2 7 EN CP RC
L GND
VOUT SW 3 6 COMP
9 R1
GND 4 5 FB
R2
VOUT
COUT
GND
SW node is with high frequency voltage swing and should
be kept at small area. Keep analog components away from
the SW node to prevent stray capacitive noise pick-up
Figure 9. PCB Layout Guide
Table 3. Suggested Capacitors for CIN and COUT

Location Component Supplier Part No. Capacitance (μF) Case Size
CIN MURATA GRM31CR61E106K 10 1206
CIN TDK C3225X5R1E106K 10 1206
CIN TAIYO YUDEN TMK316BJ106ML 10 1206
COUT MURATA GRM31CR60J476M 47 1206
COUT TDK C3225X5R0J476M 47 1210
COUT MURATA GRM32ER71C226M 22 1210
COUT TDK C3225X5R1C22M 22 1210

13
RT7257A
Outline Dimension
H
A
EXPOSED THERMAL PAD Y

(Bottom of Package)
J X B
C
I
D
Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 4.000 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.510 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010
I 0.000 0.152 0.000 0.006
J 5.791 6.200 0.228 0.244
M 0.406 1.270 0.016 0.050
X 2.000 2.300 0.079 0.091
Option 1
Y 2.000 2.300 0.079 0.091
X 2.100 2.500 0.083 0.098
Option 2
Y 3.000 3.500 0.118 0.138
8-Lead SOP (Exposed Pad) Plastic Package
Richtek Technology Corporation

5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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3A, 18V, 340kHz Synchronous Step-Down Converter

Marking Information SOP-8 (Exposed Pad)

DS7257A-03 December 2012 www.richtek.com

Table 1. Suggested Components Selection

Functional Pin Description

www.richtek.com DS7257A-03 December 2012

DS7257A-03 December 2012 www.richtek.com

Recommended Operating Conditions (Note 4)

www.richtek.com DS7257A-03 December 2012

DS7257A-03 December 2012 www.richtek.com

Output Voltage (V)

VIN = 17V 3.31

Output Voltage vs. Temperature Output Voltage vs. Output Current

Switching Frequency vs. Input Voltage Switching Frequency vs. Temperature

www.richtek.com DS7257A-03 December 2012

Current Limit vs. Temperature Load Transient Response

Load Transient Response Switching

Time (250μs/Div) Time (1μs/Div)

Power On from VIN Power Off from VIN

Time (5ms/Div) Time (5ms/Div)

DS7257A-03 December 2012 www.richtek.com

Power On from EN Power Off from EN

Time (5ms/Div) Time (5ms/Div)

www.richtek.com DS7257A-03 December 2012

VOUT = VREF ⎛⎜ 1+ R1 ⎞⎟ Chip Enable Operation

Figure 4. Digital Enable Control Circuit

DS7257A-03 December 2012 www.richtek.com

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DS7257A-03 December 2012 www.richtek.com

1.6 Copper Area

Ambient Temperature (°C)

Figure 8. Derating Curve of Maximum Power Dissipation

(c) Copper Area = 30mm2 , θJA = 54°C/W

(d) Copper Area = 50mm2 , θJA = 51°C/W

(e) Copper Area = 70mm2 , θJA = 49°C/W

Figure 7. Themal Resistance vs. Copper Area Layout

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GND VIN SW GND VIN The feedback components

Figure 9. PCB Layout Guide

Table 3. Suggested Capacitors for CIN and COUT

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EXPOSED THERMAL PAD Y

Dimensions In Millimeters Dimensions In Inches

8-Lead SOP (Exposed Pad) Plastic Package

Richtek Technology Corporation

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