Ci RT3606 Placa PC

®
RT3606BC
Dual Channel PWM Controller with Integrated Driver for IMVP8

CPU Core Power Supply
General Description Features
The RT3606BC is an IMVP8 compliant CPU power  Intel IMVP8 Serial VID Interface Compatible Power
controller which includes two voltage rails : a 3/2/1 phase Management States
synchronous Buck controller, the CORE VR and a 2/1  3/2/1 Phase (CORE VR) + 2/1 Phase (AXG VR) PWM
phase synchronous Buck controller, the AXG VR. The Controller
RT3606BC adopts G-NAVPTM (Green Native AVP) which  2 Embedded MOSFET Drivers at the CORE VR, 1
is Richtek's proprietary topology derived from finite DC Embedded MOSFET Driver at the AXG VR
gain of EA amplifier with current mode control, making it  G-NAVP TM (Green Native Adaptive Voltage
easy to set the droop to meet all Intel CPU requirements Positioning) Topology
of AVP (Adaptive Voltage Positioning). Based on the G-  0.5% DAC Accuracy
NAVPTM topology, the RT3606BC also features a quick  Differential Remote Voltage Sensing
response mechanism for optimized AVP performance  Built-in ADC for Platform Programming
during load transient. The RT3606BC supports mode  Accurate Current Balance
transition function with various operating states. A serial  System Thermal Compensated AVP
VID (SVID) interface is built in the RT3606BC to  Diode Emulation Mode at Light Load Condition for
communicate with Intel IMVP8 compliant CPU. The Single Phase Operation
RT3606BC supports VID on-the-fly function with three  Fast Transient Response
different slew rates : Fast, Slow and Decay. By utilizing  VR Ready Indicator
the G-NAVPTM topology, the operating frequency of the  Thermal Throttling
RT3606BC varies with VID, load and input voltage to further  Current Monitor Output
enhance the efficiency even in CCM. Moreover, the G-  OVP, OCP, NVP, UVLO
NAVPTM with CCRCOT (Constant Current Ripple COT)  Slew Rate Setting/Address Flip Function
technology provides superior output voltage ripple over  Rail Address Flexibility
the entire input/output range. The built-in high accuracy  DVID Enhancement
DAC converts the SVID code ranging from 0.25V to 1.52V
with 5mV per step. The RT3606BC integrates a high Applications
accuracy ADC for platform setting functions, such as quick  IMVP8 Intel Core Supply
response trigger level or over-current level. Besides, the  Notebook/ Desktop Computer/ Servers Multi-phase CPU
setting function also supports this two rails address Core Supply
exchange. The RT3606BC provides VR ready output  AVP Step-Down Converter
signals. It also features complete fault protection functions
including over-voltage (OV), negative voltage (NV), over- Simplified Application Circuit
current (OC) and under-voltage lockout (UVLO). The
RT3606BC is available in the WQFN-60L 7x7 small foot RT3606BC
To PCH PGOOD PHASE1 MOSFET VCORE
print package.
VR_HOT PHASE2 MOSFET
VCLK PWM3 Driver MOSFET
To CPU
VDIO PHASEA1 MOSFET
ALERT PWMA2 Driver MOSFET VAXG
Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
DS3606BC-00 October 2015 www.richtek.com

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RT3606BC
Ordering Information Pin Configurations
RT3606BC (TOP VIEW)
Package Type
UGATEA1
PHASEA1
LGATEA1
BOOTA1
UGATE1
UGATE2
PHASE1
PHASE2
LGATE1
LGATE2
PWMA2
BOOT1
BOOT2
QW : WQFN-60L 7x7 (W-Type)
PVCC
NC
Lead Plating System
G : Green (Halogen Free and Pb Free) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46
PWM3 1 45 PS4_Dr
Note : PGOOD 2 44 DVD
Richtek products are : TONSET 3 43 TONSETA
TSEN 4 42 TSENA
 RoHS compliant and compatible with the current require- ISEN3P 5 41 ISENA1N
ISEN3N 6 40 ISENA1P
ments of IPC/JEDEC J-STD-020.
ISEN1N 7 39 NC
 Suitable for use in SnPb or Pb-free soldering processes. ISEN1P 8 GND 38 ISENA2P
ISEN2P 9 37 ISENA2N
ISEN2N 10 36 FBA
FB 11 35 COMPA
Marking Information COMP 12 34 VSENA
RT3606BCGQW : Product Number VSEN 13 33 RGNDA
RGND 14 61 32 IBIAS
RT3606BC YMDNN : Date Code
SET1 15 31 NC
GQW 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
YMDNN
SET2
SET3
SETA1
SETA2
IMONA
VDIO
VCLK
OFSA/PSYS
IMON
VREF
VR_HOT
ALERT
EN
VCC
OFSM
WQFN-60L 7x7
Functional Pin Description

Pin No Pin Name Pin Function
1 PWM3 PWM Output for CORE rail VR of Channel 3.
2 PGOOD VR Ready Indicator.
CORE rail VR On-time Setting. An on-time setting resistor is connected from this pin
3 TONSET
to input voltage.
4 TSEN Thermal Sense Input for CORE rail VR.
8, 9, 5 ISEN[1:3]P Positive Current Sense Inputs of Multi-Phase CORE rail VR Channel 1, 2 and 3.
7, 10, 6 ISEN[1:3]N Negative Current Sense Inputs of Multi-Phase CORE rail VR Channel 1, 2 and 3.
Negative Input of the Error Amplifier. This pin is for CORE rail VR output voltage
11 FB
feedback to controller.
12 COMP CORE rail VR Compensation. This pin is the error amplifier output pin.
CORE rail VR Voltage Sense Input. This pin is connected to the terminal of CORE
13 VSEN
rail VR output voltage.
Return Ground for CORE rail VR. This pin is the negative node of the differential
14 RGND
remote voltage sensing.
1st Platform Setting. Platform can use this pin to set OCS, DVID threshold and
15 SET1
ICCMAX for CORE rail VR.
2nd Platform Setting. Platform can use this pin to set RSET, QRTH, QRWIDTH and
DVID width for CORE rail VR. Moreover, SET2 pin features a special function for
16 SET2 users to confirm the soldering condition of the controller under zero VBOOT
condition. Connect the SET2 pin to 5V and turn on the EN pin, if the soldering is
good, both rails will output 0.8V.
www.richtek.com DS3606BC-00 October 2015

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RT3606BC
rd
3 Platform setting. Platform can use this pin to set VR address, Zero load-line, Anti-
overshoot function and behavior, AI gain, Disable DVID compensation, Decrease
17 SET3
GTU and SA ramp (only in maximum phase = 1-phase), high frequency ramp, DVID
slew rate, and PSYS function for CORE VR and AXG VR.
1st Platform Setting. Platform can use this pin to set OCS, DVID threshold and
18 SETA1
ICCMAX for AXG rail VR.
2nd Platform Setting. Platform can use this pin to set RSET, QRTH, QRWIDTH and
19 SETA2
DVID width for AXG rail VR.
CORE rail VR Current Monitor Output. This pin outputs a voltage proportional to the
20 IMON
loading current.
Fixed 0.6V Output Reference Voltage. This voltage is only used to offset the output
21 VREF voltage of IMON pin. Between this pin and GND must be placed a RC circuit with R
= 1 and C = 0.47F.
AXG rail VR Current Monitor Output. This pin outputs a voltage proportional to the
22 IMONA
loading current.
23 VR_HOT Thermal Monitor Output, this Pin is Active Low.
24 ALERT SVID Alert. (Active low)
25 VDIO VR and CPU Data Transmission Interface.
26 VCLK Synchronous Clock from the CPU.
27 EN VR Enable Control Input.
28 OFSM Output Voltage Offset Setting for CORE rail VR.
29 OFSA/PSYS Output Voltage Offset Setting for AXG rail VR / System Input Power Monitor.
Controller Power Supply. Connect this pin to 5V and place a decoupling capacitor
30 VCC
2.2F at least. The decoupling capacitor is placed as close VR controller as possible.
31, 39, 46 NC No Internal Connection.

Internal Bias Current Setting. Connect a 100k resistor from this pin tied to GND to
32 IBIAS
set the internal current. Don’t connect a bypass pass capacitor from this pin to GND.
Return Ground for AXG rail VR. This pin is the negative node of the differential
33 RGNDA
remote voltage sensing.
AXG rail VR Voltage Sense Input. This pin is connected to the terminal of AXG rail
34 VSENA
VR output voltage.
35 COMPA AXG rail VR Compensation. This pin is the error amplifier output pin.
Negative Input of the Error Amplifier. This pin is for AXG rail VR output voltage
36 FBA
feedback to controller.
40, 38 ISENA[1:2]P Positive Current Sense Input of Multi-Phase AXG rail VR Channel 1, 2.
41, 37 ISENA[1:2]N Negative Current Sense Input of Multi-Phase AXG rail VR Channel 1, 2.
42 TSENA Thermal Sense Input for AXG rail VR.
AXG rail VR On-time Setting. An on-time setting resistor is connected from this pin
43 TONSETA
to input voltage.
Divided Input Voltage Detection of Power Stage. Connect this pin to a voltage divider
44 DVD
from input voltage of power stage to detect input voltage.

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RT3606BC
Dr.MOS Enable Control. Connecting to Dr.MOS PS4 function pin. As received PS4
45 PS4_Dr command, this pin will be floating. If the Dr. MOS needs active low to enter PS4 or
use discrete MOSFET, please reserve a 100k resistor to GND.
47 PWMA2 PWM Output for AXG rail VR Channel 2.
48 BOOTA1 Bootstrap Supply for High-Side Gate MOSFET Driver for AXG rail VR.
High-Side Drive Outputs for AXG rail VR. Connect the pin to the gate of high-side
49 UGATEA1
MOSFET.
Switch Node of High-Side Driver for AXG rail VR. Connect the pin to high-side
50 PHASEA1
MOSFE source together with the low-side MOSFET drain and inductor.
Low-Side Driver Output for AXG rail VR. This pin drives the gate of low-side
51 LGATEA1
MOSFET.
Driver Power Supply Input. Connect this pin to GND by a minimum 2.2F ceramic
52 PVCC
Capacitor.
Low-Side Driver Output for CORE rail VR. This pin drives the gate of low-side
57, 53 LGATE[1:2]
MOSFET.
Switch Node of High-Side Driver for CORE rail VR. Connect the pin to high-side
58, 54 PHASE[1:2]
MOSFE source together with the low-side MOSFET drain and inductor.
High-Side Drive Outputs for CORE rail VR. Connect the pin to the gate of high-side
59, 55 UGATE[1:2]
MOSFET.
60, 56 BOOT[1:2] Bootstrap Supply for High-Side Gate MOSFET Driver for CORE rail VR.
61 Ground. The exposed pad must be soldered to a large PCB and connected to GND
GND
(Exposed Pad) for maximum power dissipation.

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RT3606BC
Function Block Diagram
OFSA/PSYS
VR_HOT
PGOOD
VSENM
PS4_Dr
VSENA
TSENA
ALERT
SETA1
SETA2
OFSM
TSEN
VCLK
SET1
SET2
SET3
VDIO
DVD
VCC
EN
IMONI_M
IMONI_A UVLO
GND
MUX MUX
ADC ADC
SVID Interface
Configuration Registers IC1_M Loop Control Protection
Control Logic IC2_M Logic
IC3_M
Current Mirror DAC IC4_M
VID_M VID_A IC1_A
2V +
IBIASI IC2_A PS_M PS_A
IBIAS - DVIDTH_X VR address
IC3_A
DVIDWIDTH_X H/L fSW ramp OV_X/NV_X/
OCS_M
QR_X DVID SR OC_PER_X/OC_SUM_X
OCS_A
QRWIDTH_X Disable DVID compensation
OCS_TH_X Decrease GTV/SA ramp (only in 1-phase)
From Control Logic DVID SR RSET_X Zero load-line
DVIDTH_M ICCMAX_X Anti-OVS TONSET
RGND DVIDWIDTH_M OCP_PER_X Anti-OVS behavior
DAC
AI gain PWM3
ERROR PSYS function
Soft-Start & Slew Rate VSET_M AMP PWM
Control + Offset CMP
+
FB - Cancellation PWM1 PVCC
+ - PS_M TON
COMP GEN BOOT1
QRTH_M PWM2
Current Mirror UGATE1
QRWIDTH_M
ISEN1P + 1/3 PHASE1
IC1_M
ISEN1N - +
IB1_M GM LGATE1
VREF -
Current Mirror RSET_M BOOT2
ISEN2P + Current Balance Driver UGATE2
IC2_M
ISEN2N - PHASE2
IB2_M IMON Filter IMONI_M
IB1_M IB2_M IB3_M LGATE2
Current Mirror
ISEN3P + PWMA1 BOOTA1
IC3_M
ISEN3N - Anti-OVS UGATEA1
IB3_M
+ PHASEA1
OCS_M
IMON OCS_TH_M - Anti-OVS behavior LGATEA1
From Control Logic DVID SR

DVIDTH_A TONSETA
RGNDA DVIDWIDTH_A
DAC
ERROR
Soft-Start & Slew Rate VSET_A AMP PWM
Control + Offset CMP
+ TON
FBA - Cancellation
+ - GEN
PS_A
COMPA PWMA2
Current Mirror QRTH_A
ISENA1P + 1/3 QRWIDTH_A
IC1_A
ISENA1N - +
IB1_A GM
-
Current Mirror RSET_A
Current Balance
ISENA2P +
IC2_A
ISENA2N - IB1_A IB2_A
IB2_A IMON Filter IMONI_A
IMONA +
OCS_A
OCS_TH_A -
VREFI +
-
VREF

5
RT3606BC
Operation
The RT3606BC adopts G-NAVPTM (Green Native AVP) Current Balance
which is Richtek's proprietary topology derived from finite Each phase current sense signal is sent to the current
DC gain of EA amplifier with current mode control, making balance circuit which adjusts the on-time of each phase
it easy to set the droop to meet all Intel CPU requirements to optimize current sharing.
of AVP (Adaptive Voltage Positioning).
Offset Cancellation
The G-NAVPTM controller is one type of current mode
constant on-time control with DC offset cancellation. The Cancel the current/voltage ripple issue to get the accurate
approach can not only improve DC offset problem for VSEN.
increasing system accuracy but also provide fast transient
UVLO
response. When current feedback signal reaches COMP
Detect the DVD and VCC voltage and issue POR signal as
signal, the RT3606BC generates an on-time width to
they are high enough.
achieve PWM modulation.
DAC
TON GEN/Driver Interface
Generate an analog signal according to the digital code
Generate the PWM1 to PWM3 sequentially according to
generated by Control Logic.
the phase control signal from the Loop Control/Protection
Logic. Pulse width is determined by current balance result Soft-Start & Slew Rate Control
and TONSET pin setting. Once quick response mechanism
Control the Dynamic VID slew rate of DAC according to
is triggered, VR will allow all PWM to turn on at the same
the SetVID fast or SetVID slow.
time. PWM status is also controlled by Protection Logic.
Different protections may cause different PWM status Error Amp
(Both High-Z or LG turn-on).
Error amplifier generates COMP/COMPA signal by the
difference between VSEN/VSENA and FB/FBA.
SVID Interface/Configuration Registers/Control
Logic
RSET/RSETA
The interface receives the SVID signal from CPU and sends
The Ramp generator is designed to improve noise immunity
the relative signals to Loop Control/Protection Logic for
and reduce jitter.
loop control to execute the action by CPU. The registers
save the pin setting data from ADC output. The Control PWM CMP
Logic controls the ADC timing and generates the digital The PWM comparator compares COMP signal and current
code of the VID for VSEN voltage. feedback signal to generate a signal for TON trigger.
Loop Control/Protection Logic IMON Filter

It controls the power on sequence, the protection behavior, IMON Filter is used to average sum current signal by
and the operational phase number. analog RC filter.
MUX and ADC

The MUX supports the inputs from SET1, SET2, SET3,
SETA1, SETA2, IMONI_M, IMONI_A, TSEN or TSENA.
The ADC converts these analog signals to digital codes
for reporting or performance adjustment.

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RT3606BC
Table 1. IMVP8 VID Code Table
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
0 0 0 0 0 0 0 1 01 0.25
0 0 0 0 0 0 1 0 02 0.255
0 0 0 0 0 0 1 1 03 0.26
0 0 0 0 0 1 0 0 04 0.265
0 0 0 0 0 1 0 1 05 0.27
0 0 0 0 0 1 1 0 06 0.275
0 0 0 0 0 1 1 1 07 0.28
0 0 0 0 1 0 0 0 08 0.285
0 0 0 0 1 0 0 1 09 0.29
0 0 0 0 1 0 1 0 0A 0.295
0 0 0 0 1 0 1 1 0B 0.3
0 0 0 0 1 1 0 0 0C 0.305
0 0 0 0 1 1 0 1 0D 0.31
0 0 0 0 1 1 1 0 0E 0.315
0 0 0 0 1 1 1 1 0F 0.32
0 0 0 1 0 0 0 0 10 0.325
0 0 0 1 0 0 0 1 11 0.33
0 0 0 1 0 0 1 0 12 0.335
0 0 0 1 0 0 1 1 13 0.34
0 0 0 1 0 1 0 0 14 0.345
0 0 0 1 0 1 0 1 15 0.35
0 0 0 1 0 1 1 0 16 0.355
0 0 0 1 0 1 1 1 17 0.36
0 0 0 1 1 0 0 0 18 0.365
0 0 0 1 1 0 0 1 19 0.37
0 0 0 1 1 0 1 0 1A 0.375
0 0 0 1 1 0 1 1 1B 0.38
0 0 0 1 1 1 0 0 1C 0.385
0 0 0 1 1 1 0 1 1D 0.39
0 0 0 1 1 1 1 0 1E 0.395
0 0 0 1 1 1 1 1 1F 0.4
0 0 1 0 0 0 0 0 20 0.405
0 0 1 0 0 0 0 1 21 0.41
0 0 1 0 0 0 1 0 22 0.415
0 0 1 0 0 0 1 1 23 0.42
0 0 1 0 0 1 0 0 24 0.425

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RT3606BC
0 0 1 0 0 1 0 1 25 0.43
0 0 1 0 0 1 1 0 26 0.435
0 0 1 0 0 1 1 1 27 0.44
0 0 1 0 1 0 0 0 28 0.445
0 0 1 0 1 0 0 1 29 0.45
0 0 1 0 1 0 1 0 2A 0.455
0 0 1 0 1 0 1 1 2B 0.46
0 0 1 0 1 1 0 0 2C 0.465
0 0 1 0 1 1 0 1 2D 0.47
0 0 1 0 1 1 1 0 2E 0.475
0 0 1 0 1 1 1 1 2F 0.48
0 0 1 1 0 0 0 0 30 0.485
0 0 1 1 0 0 0 1 31 0.49
0 0 1 1 0 0 1 0 32 0.495
0 0 1 1 0 0 1 1 33 0.5
0 0 1 1 0 1 0 0 34 0.505
0 0 1 1 0 1 0 1 35 0.51
0 0 1 1 0 1 1 0 36 0.515
0 0 1 1 0 1 1 1 37 0.52
0 0 1 1 1 0 0 0 38 0.525
0 0 1 1 1 0 0 1 39 0.53
0 0 1 1 1 0 1 0 3A 0.535
0 0 1 1 1 0 1 1 3B 0.54
0 0 1 1 1 1 0 0 3C 0.545
0 0 1 1 1 1 0 1 3D 0.55
0 0 1 1 1 1 1 0 3E 0.555
0 0 1 1 1 1 1 1 3F 0.56
0 1 0 0 0 0 0 0 40 0.565
0 1 0 0 0 0 0 1 41 0.57
0 1 0 0 0 0 1 0 42 0.575
0 1 0 0 0 0 1 1 43 0.58
0 1 0 0 0 1 0 0 44 0.585
0 1 0 0 0 1 0 1 45 0.59
0 1 0 0 0 1 1 0 46 0.595
0 1 0 0 0 1 1 1 47 0.6
0 1 0 0 1 0 0 0 48 0.605
0 1 0 0 1 0 0 1 49 0.61

8
RT3606BC
0 1 0 0 1 0 1 0 4A 0.615
0 1 0 0 1 0 1 1 4B 0.62
0 1 0 0 1 1 0 0 4C 0.625
0 1 0 0 1 1 0 1 4D 0.63
0 1 0 0 1 1 1 0 4E 0.635
0 1 0 0 1 1 1 1 4F 0.64
0 1 0 1 0 0 0 0 50 0.645
0 1 0 1 0 0 0 1 51 0.65
0 1 0 1 0 0 1 0 52 0.655
0 1 0 1 0 0 1 1 53 0.66
0 1 0 1 0 1 0 0 54 0.665
0 1 0 1 0 1 0 1 55 0.67
0 1 0 1 0 1 1 0 56 0.675
0 1 0 1 0 1 1 1 57 0.68
0 1 0 1 1 0 0 0 58 0.685
0 1 0 1 1 0 0 1 59 0.69
0 1 0 1 1 0 1 0 5A 0.695
0 1 0 1 1 0 1 1 5B 0.7
0 1 0 1 1 1 0 0 5C 0.705
0 1 0 1 1 1 0 1 5D 0.71
0 1 0 1 1 1 1 0 5E 0.715
0 1 0 1 1 1 1 1 5F 0.72
0 1 1 0 0 0 0 0 60 0.725
0 1 1 0 0 0 0 1 61 0.73
0 1 1 0 0 0 1 0 62 0.735
0 1 1 0 0 0 1 1 63 0.74
0 1 1 0 0 1 0 0 64 0.745
0 1 1 0 0 1 0 1 65 0.75
0 1 1 0 0 1 1 0 66 0.755
0 1 1 0 0 1 1 1 67 0.76
0 1 1 0 1 0 0 0 68 0.765
0 1 1 0 1 0 0 1 69 0.77
0 1 1 0 1 0 1 0 6A 0.775
0 1 1 0 1 0 1 1 6B 0.78
0 1 1 0 1 1 0 0 6C 0.785
0 1 1 0 1 1 0 1 6D 0.79
0 1 1 0 1 1 1 0 6E 0.795

9
RT3606BC
0 1 1 0 1 1 1 1 6F 0.8
0 1 1 1 0 0 0 0 70 0.805
0 1 1 1 0 0 0 1 71 0.81
0 1 1 1 0 0 1 0 72 0.815
0 1 1 1 0 0 1 1 73 0.82
0 1 1 1 0 1 0 0 74 0.825
0 1 1 1 0 1 0 1 75 0.83
0 1 1 1 0 1 1 0 76 0.835
0 1 1 1 0 1 1 1 77 0.84
0 1 1 1 1 0 0 0 78 0.845
0 1 1 1 1 0 0 1 79 0.85
0 1 1 1 1 0 1 0 7A 0.855
0 1 1 1 1 0 1 1 7B 0.86
0 1 1 1 1 1 0 0 7C 0.865
0 1 1 1 1 1 0 1 7D 0.87
0 1 1 1 1 1 1 0 7E 0.875
0 1 1 1 1 1 1 1 7F 0.88
1 0 0 0 0 0 0 0 80 0.885
1 0 0 0 0 0 0 1 81 0.89
1 0 0 0 0 0 1 0 82 0.895
1 0 0 0 0 0 1 1 83 0.9
1 0 0 0 0 1 0 0 84 0.905
1 0 0 0 0 1 0 1 85 0.91
1 0 0 0 0 1 1 0 86 0.915
1 0 0 0 0 1 1 1 87 0.92
1 0 0 0 1 0 0 0 88 0.925
1 0 0 0 1 0 0 1 89 0.93
1 0 0 0 1 0 1 0 8A 0.935
1 0 0 0 1 0 1 1 8B 0.94
1 0 0 0 1 1 0 0 8C 0.945
1 0 0 0 1 1 0 1 8D 0.95
1 0 0 0 1 1 1 0 8E 0.955
1 0 0 0 1 1 1 1 8F 0.96
1 0 0 1 0 0 0 0 90 0.965
1 0 0 1 0 0 0 1 91 0.97
1 0 0 1 0 0 1 0 92 0.975
1 0 0 1 0 0 1 1 93 0.98

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RT3606BC
1 0 0 1 0 1 0 0 94 0.985
1 0 0 1 0 1 0 1 95 0.99
1 0 0 1 0 1 1 0 96 0.995
1 0 0 1 0 1 1 1 97 1
1 0 0 1 1 0 0 0 98 1.005
1 0 0 1 1 0 0 1 99 1.01
1 0 0 1 1 0 1 0 9A 1.015
1 0 0 1 1 0 1 1 9B 1.02
1 0 0 1 1 1 0 0 9C 1.025
1 0 0 1 1 1 0 1 9D 1.03
1 0 0 1 1 1 1 0 9E 1.035
1 0 0 1 1 1 1 1 9F 1.04
1 0 1 0 0 0 0 0 A0 1.045
1 0 1 0 0 0 0 1 A1 1.05
1 0 1 0 0 0 1 0 A2 1.055
1 0 1 0 0 0 1 1 A3 1.06
1 0 1 0 0 1 0 0 A4 1.065
1 0 1 0 0 1 0 1 A5 1.07
1 0 1 0 0 1 1 0 A6 1.075
1 0 1 0 0 1 1 1 A7 1.08
1 0 1 0 1 0 0 0 A8 1.085
1 0 1 0 1 0 0 1 A9 1.09
1 0 1 0 1 0 1 0 AA 1.095
1 0 1 0 1 0 1 1 AB 1.1
1 0 1 0 1 1 0 0 AC 1.105
1 0 1 0 1 1 0 1 AD 1.11
1 0 1 0 1 1 1 0 AE 1.115
1 0 1 0 1 1 1 1 AF 1.12
1 0 1 1 0 0 0 0 B0 1.125
1 0 1 1 0 0 0 1 B1 1.13
1 0 1 1 0 0 1 0 B2 1.135
1 0 1 1 0 0 1 1 B3 1.14
1 0 1 1 0 1 0 0 B4 1.145
1 0 1 1 0 1 0 1 B5 1.15
1 0 1 1 0 1 1 0 B6 1.155
1 0 1 1 0 1 1 1 B7 1.16
1 0 1 1 1 0 0 0 B8 1.165

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RT3606BC
1 0 1 1 1 0 0 1 B9 1.17
1 0 1 1 1 0 1 0 BA 1.175
1 0 1 1 1 0 1 1 BB 1.18
1 0 1 1 1 1 0 0 BC 1.185
1 0 1 1 1 1 0 1 BD 1.19
1 0 1 1 1 1 1 0 BE 1.195
1 0 1 1 1 1 1 1 BF 1.2
1 1 0 0 0 0 0 0 C0 1.205
1 1 0 0 0 0 0 1 C1 1.21
1 1 0 0 0 0 1 0 C2 1.215
1 1 0 0 0 0 1 1 C3 1.22
1 1 0 0 0 1 0 0 C4 1.225
1 1 0 0 0 1 0 1 C5 1.23
1 1 0 0 0 1 1 0 C6 1.235
1 1 0 0 0 1 1 1 C7 1.24
1 1 0 0 1 0 0 0 C8 1.245
1 1 0 0 1 0 0 1 C9 1.25
1 1 0 0 1 0 1 0 CA 1.255
1 1 0 0 1 0 1 1 CB 1.26
1 1 0 0 1 1 0 0 CC 1.265
1 1 0 0 1 1 0 1 CD 1.27
1 1 0 0 1 1 1 0 CE 1.275
1 1 0 0 1 1 1 1 CF 1.28
1 1 0 1 0 0 0 0 D0 1.285
1 1 0 1 0 0 0 1 D1 1.29
1 1 0 1 0 0 1 0 D2 1.295
1 1 0 1 0 0 1 1 D3 1.3
1 1 0 1 0 1 0 0 D4 1.305
1 1 0 1 0 1 0 1 D5 1.31
1 1 0 1 0 1 1 0 D6 1.315
1 1 0 1 0 1 1 1 D7 1.32
1 1 0 1 1 0 0 0 D8 1.325
1 1 0 1 1 0 0 1 D9 1.33
1 1 0 1 1 0 1 0 DA 1.335
1 1 0 1 1 0 1 1 DB 1.34
1 1 0 1 1 1 0 0 DC 1.345
1 1 0 1 1 1 0 1 DD 1.35

12
RT3606BC
1 1 0 1 1 1 1 0 DE 1.355
1 1 0 1 1 1 1 1 DF 1.36
1 1 1 0 0 0 0 0 E0 1.365
1 1 1 0 0 0 0 1 E1 1.37
1 1 1 0 0 0 1 0 E2 1.375
1 1 1 0 0 0 1 1 E3 1.38
1 1 1 0 0 1 0 0 E4 1.385
1 1 1 0 0 1 0 1 E5 1.39
1 1 1 0 0 1 1 0 E6 1.395
1 1 1 0 0 1 1 1 E7 1.4
1 1 1 0 1 0 0 0 E8 1.405
1 1 1 0 1 0 0 1 E9 1.41
1 1 1 0 1 0 1 0 EA 1.415
1 1 1 0 1 0 1 1 EB 1.42
1 1 1 0 1 1 0 0 EC 1.425
1 1 1 0 1 1 0 1 ED 1.43
1 1 1 0 1 1 1 0 EE 1.435
1 1 1 0 1 1 1 1 EF 1.44
1 1 1 1 0 0 0 0 F0 1.445
1 1 1 1 0 0 0 1 F1 1.45
1 1 1 1 0 0 1 0 F2 1.455
1 1 1 1 0 0 1 1 F3 1.46
1 1 1 1 0 1 0 0 F4 1.465
1 1 1 1 0 1 0 1 F5 1.47
1 1 1 1 0 1 1 0 F6 1.475
1 1 1 1 0 1 1 1 F7 1.48
1 1 1 1 1 0 0 0 F8 1.485
1 1 1 1 1 0 0 1 F9 1.49
1 1 1 1 1 0 1 0 FA 1.495
1 1 1 1 1 0 1 1 FB 1.5
1 1 1 1 1 1 0 0 FC 1.505
1 1 1 1 1 1 0 1 FD 1.51
1 1 1 1 1 1 1 0 FE 1.515
1 1 1 1 1 1 1 1 FF 1.52

13
RT3606BC
Absolute Maximum Ratings (Note 1)
 VCC to GND ------------------------------------------------------------------------------------------- −0.3V to 6.5V
 PVCC to GND ----------------------------------------------------------------------------------------- −0.3V to 15V
 RGND to GND ----------------------------------------------------------------------------------------- −0.3V to 0.3V
 TONSET to GND -------------------------------------------------------------------------------------- −0.3V to 28
 BOOTx to PHASEx ---------------------------------------------------------------------------------- −0.3V to 15V
 PHASEx to GND
DC -------------------------------------------------------------------------------------------------------- −0.3V to 30V
<20ns --------------------------------------------------------------------------------------------------- −10V to 35V
 LGATEx to GND
DC -------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)
<20ns --------------------------------------------------------------------------------------------------- −2V to (VCC + 0.3V)
 UGATEx to GND
DC -------------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V)
<20ns --------------------------------------------------------------------------------------------------- (VPHASE − 2V) to (VBOOT + 0.3V)
 Other Pins ---------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)
 Power Dissipation, PD @ TA = 25°C
WQFN-60L 7x7 --------------------------------------------------------------------------------------- 3.92W
 Package Thermal Resistance (Note 2)
WQFN-60L 7x7, θJA ---------------------------------------------------------------------------------- 25.5°C/W
WQFN-60L 7x7, θJC --------------------------------------------------------------------------------- 6.5°C/W
 Junction Temperature -------------------------------------------------------------------------------- 150°C
 Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------- 260°C
 Storage Temperature Range ----------------------------------------------------------------------- −65°C to 150°C
 ESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------- 2kV
MM (Machine Mode) --------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 4)

 Supply Voltage, VCC -------------------------------------------------------------------------------- 4.5V to 5.5V
 Junction Temperature Range ----------------------------------------------------------------------- −40°C to 125°C
 Ambient Temperature Range ----------------------------------------------------------------------- −40°C to 85°C

14
RT3606BC
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit

Supply Input
Supply Voltage VCC 4.5 5 5.5 V
Supply Current IVCC VEN = H, No Switching -- 13 --
mA
Supply Current at PS4 IVCC_PS4 VEN = H, No Switching -- 0.1 --
Shutdown Current ISHDN VEN = 0V -- -- 5 A
Reference and DAC
VDAC = 0.75V 1.52V 0.5% 0 0.5% % of VID
DAC Accuracy VFB VDAC = 0.5V 0.745V 8 0 8
mV
VDAC = 0.25V 0.495V 10 0 10
Slew Rate
Set VID Fast -- 11.25 --
Dynamic VID Slew Rate SR (S Line) mV/s
Set VID Slow -- 5.625 --
Set VID Fast -- 33.75 --
Dynamic VID Slew Rate SR (H, Y, U Line) mV/s
Set VID Slow -- 16.875 --
EA
DC Gain EAGAIN RL = 47k 70 -- -- dB
Gain-Bandwidth Product GBW CLOAD = 5pF -- 5 -- MHz
Output Voltage Range VCOMP RL = 47k 0.5 -- 3.6 V
Max Source/Sink Current IOUTEA VCOMP = 2V -- 5 -- mA
Load Line Current Gain Amplifier
Input Offset Voltage VILOFS VIMON = 1V 5 -- 5 mV
VIMON VVREF = 1V
Current Gain AILGAIN -- 1/3 -- A/A
VFB = VCOMP = 1V
Current Sensing Amplifier
Input Offset Voltage VOSCS 0.5 -- 0.5 mV
Impedance at Positive
RISENxP 1 -- -- M
Input
Current Mirror Gain AMIRROR IIMON/ISENxN 0.97 1 1.03 A/A
TON Setting
TON Pin Voltage VTON IRTON = 26.8A, VDAC = 1V 0.9 1 1.1 V
On-Time Setting TON IRTON = 26.8A, VDAC = 1V 189 210 231 ns
Input Current Range IRTON VDAC = 1V 6 -- 70 A
Minimum Off time TOFF VDAC = 1V -- 180 -- ns

15
RT3606BC
IBIAS
IBIAS Pin Voltage VIBIAS RIBIAS = 100k 1.9 2 2.1 V
Protections
Under-Voltage Lockout VUVLO Falling edge 3.95 4.05 4.15 V

Threshold VUVLO Rising edge hysteresis -- 190 -- mV
VID + VID + VID +
Over-Voltage Protection Respect to VID voltage mV
VOV 300 350 400
Threshold
Lower limit to 1V 1300 1350 1400 mV
Negative Voltage
VNV 100 70 -- mV
Protection Threshold
EN and VR_REDAY
VIH Respect to 1V, 70% 0.7 -- -- V
EN Input Voltage
VIL Respect to 1V, 30% -- -- 0.3 V
Leakage Current of EN 1 -- 1 A
PGOOD Pull Low
VPGOOD IVR_Ready = 10mA -- -- 0.13 V
Voltage
DVD (Note 5)
VDVD = 2V or above, VR judge VIN
DVD Input High Voltage VIH 2 -- -- V
high
VDVD = 1.3V or below, VR judge VIN
DVD Input low Voltage VIL -- -- 1.3 V
low
Serial VID and VR_HOT
VIH Respect to INTEL Spec. with 50mV 0.65 -- --
VCLK, VDIO V
VIL hysteresis -- -- 0.45
Leakage Current of
VCLK, VDIO, ALERT ILEAK_IN 1 -- 1 A
and VR_HOT
VDIO, ALERT and IVDIO = 10mA

VR_HOT Pull Low IALERT = 10mA -- -- 0.13 V
Voltage IVR_HOT = 10mA
VREF
VREF Voltage VREF 0.55 0.6 0.65 V
ADC
VIMON  VIMON_INI = 1.6V -- 255 -- Decimal
Digital IMON Set VIMON VIMON  VIMON_INI = 0.8V -- 128 -- Decimal
VIMON  VIMON_INI = 0V -- 0 -- Decimal

16
RT3606BC
Update Period TIMON -- 125 -- s
TSEN Threshold for
100C -- 1.092 --
Tmp_Zone[7] Transition
TSEN Threshold for
97C -- 1.132 --
TSEN Threshold for
94C -- 1.176 --
TSEN Threshold for
91C -- 1.226 --
VTSEN V
TSEN Threshold for
88C -- 1.283 --
TSEN Threshold for
85C -- 1.346 --
TSEN Threshold for
82C -- 1.418 --
TSEN Threshold for
75C -- 1.624 --
Update Period Ttsen -- 100 -- s
CICCMAX1 VREF = 3.2V, VSETI = 0.404V 29 32 35 Decimal
Digital Code of ICCMAX CICCMAX2 VREF = 3.2V, VSETI = 0.804V 61 64 67 Decimal
CICCMAX3 VREF = 3.2V, VSETI = 1.592V 124 127 130 Decimal
Timing
UGATEx Rising Time tUGATEr 3nF load -- 25 -- ns
UGATEx Falling Time tUGATEf 3nF load -- 12 -- ns
LGATEx Rising Time tLGATEr 3nF load -- 24 -- ns
LGATEx Falling Time tLGATEf 3nF load -- 10 -- ns
tUGATEpgh VBOOTx VPHASEx = 12V -- 60 --
ns
tUGATEpdl See Timing Diagram -- 22 --
Propagation Delay
tLGATEpdh -- 30 --
See Timing Diagram ns
tLGATEpdl -- 8 --
Output
VBOOT  VPHASE = 12V, ISource =
UGATEx Drive Source RUGATEsr -- 1.7 -- 
100mA
VBOOT  VPHASE = 12V, ISink =
UGATEx Drive Sink RUGATEsk -- 1.4 -- 
100mA
LGATEx Drive Source RLGATEsr ISource = 100mA -- 1.6 -- 
LGATEx Drive Sink RLGATEsk ISink = 100mA -- 1.1 -- 
PWM Driving Capability
PWM Source Resistance RPWM_SRC -- 30 -- 
PWM Sink Resistance RPWM_SNK -- 10 -- 

17
RT3606BC
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5.(1) DVD Input High Voltage: DVD pin is an input pin of VR. VR always identify high level while the voltage given at DVD
pin >= 2V. The high-low transition is within 1.3V ~2V.
(2) DVD Input low Voltage: DVD pin is an input pin of VR. VR always identify low level while the voltage given at DVD
pin <= 1.3V. The high-low transition is within 1.3V ~2V.

18
RT3606BC
Typical Application Circuit
Discrete MOS
VIN
C18
R40 0.1µF
RT3606BC
60 2.2
R1 BOOT1
510k 44 59 R41
VIN DVD UGATE1 L1
0 220nH/0.49m
R2 C1 58
100k 0.1µF PHASE1
R42 0.47µF/
57 R43 R44
LGATE1 1k X7R/0603
0 1
30
5V VCC C19
R3 C2 3.3nF C20
2.2 2.2µF
R4 59k 8 Optional
15 ISEN1P
VREF SET1 R45
R5 69.8k 16 7 R82 680
SET2 ISEN1N
R6 174k 17 VIN
SET3
C22
R7 64.9k 18 R46 0.1µF
SETA1 56 2.2
BOOT2
R8 46.4k 19
SETA2 55 R47
UGATE2 L2
R9 R10 R11 R12 R13 0 220nH/0.49m
12k 7.5k 3.32k 18.2k 11k 54
PHASE2
R48 0.47µF/
53 R49
LGATE2 R50 X7R/0603
0 1
R14 R15 3
VIN TONSET C23 1k C24
2.2 C3 487k 3.3nF
0.22µF ISEN2P 9 Optional
R51
R16 R17 412k 43
VIN TONSETA R83 680
2.2 ISEN2N 10
C4 VCC_SENSE VSS_SENSE
0.22µF R18 32
IBIAS VIN
12V C26
100k R52 R88 R89
0.1µF
21 2.2 100 100
VREF VREF VCC BOOT C48
R19 13k C25 VCORE_OUT
R53
R87 1µF UGATE C45
PGND L3 C44
1 0 220nH/0.49m 22µF
R20 RNTC R22 470µF LOAD
20 1 PHASE x 19
C5 IMON PWM3 PWM x4
0.47µF/
0.47µF 3.09k 100k/4485 ( ) 16.5k R54
PS4_Dr EN LGATE R55 R56 X7R/0603
R23 24.3k 0 1 Optional
RT9624A
C27 1k C28
R24 RNTCA R25 3.3nF
22 IMONA
5 Optional
16k 100k/4485 ( ) 15.8k ISEN3P R57
VCCIO
6 R84 680
ISEN3N
R26 R27 R28 R29 R30
NC 110 55 75 10k VIN
2 12V C38
PGOOD R70 0.1µF
23 2.2
VR_HOT VCC BOOT
26 C37 R71
VCLK 1µF UGATE
PGND L6
25 0 220nH/0.49m
To CPU VDIO
24 47 PHASE
ALERT PWMA2 PWM 0.47µF/
R72
PS4_Dr EN LGATE R73 R74 X7R/0603
27 EN 0 1
Enable RT9624A
C39 1k C40
3.3nF
C6 470pF C7 56pF
38 Optional
ISENA2P R75
37 R33 680
R31 12k R32 32.4k 12 ISENA2N
VCC_SENSE COMP
VCCAXG_SENSE VSSAXG_SENSE
C8 C9
Optional Optional 11 FB
VIN
VSS_SENSE 14 C40 R90 R91
RGND R76 100
0.1µF 100
C11 2.2
Optional 48 C49 VAXG_OUT
BOOTA1
13 49 R77 C47
VCC_SENSE VSEN UGATEA1 L7 C46 22µF
0 220nH/0.49m 470µF LOAD
C12 330pF C13 33pF 50 x 14
PHASEA1 x4
R78 0.47µF/
51 R79 R80
LGATEA1 X7R/0603 Optional
R34 R35 35 0 1
COMPA C43 1k C10
C14 C15 10k 34k
36 FBA 3.3nF
Optional Optional
33 40 Optional
VSSAXG_SENSE RGNDA ISENA1P
R81
C16 R21 680
Optional 41
ISENA1N
VCCAXG_SENSE 34
VSENA 28
R36 93.1k OFSM
29
R37 RNTC OFSA/PSYS
4
TSEN
8.77k 150k/4500 ( ) 45
PS4_Dr PS4_Dr
R38 93.1k R65
100k
R39 RNTC 42
TSENA
8.77k 150k/4500 ( )
52 R64 2.2 5V for VIN = 19V
61 (Exposed Pad) PVCC
GND 12V for VIN =12V
C50
22µF

19
RT3606BC
Typical Operating Characteristics
CORE VR Power On from EN CORE VR Power Off from EN
V CORE
V CORE
(300mV/Div)
(300mV/Div)
PGOOD
PGOOD (1V/Div)
(1V/Div)
UGATE1 UGATE1
(10V/Div) (10V/Div)
EN EN
(1V/Div) (1V/Div)
VIN = 12V, No Load, VID = 0.8V, SET2 pin tied to 5V VIN = 12V, No Load, VID = 0.8V, SET2 pin tied to 5V
Time (500μs/Div) Time (50μs/Div)
CORE VR OCP CORE VR OVP
V CORE
(200mV/Div)
PGOOD V CORE
(1V/Div) (500mV/Div)
PGOOD
UGATE1
(1V/Div)
(20V/Div)
UGATE1
(20V/Div)
I LOAD
(60A/Div) LGATE1
(10V/Div)
VIN = 12V, VID = 0.9V
CORE VR Dynamic VID Up CORE VR Dynamic VID Down
V CORE V CORE
VCLK VCLK
VCLK VCLK
(1V/Div) (1V/Div)
V CORE VDIO V CORE VDIO
(200mV/Div) (200mV/Div)
VDIO VDIO
(1V/Div) (1V/Div)
ALERT ALERT
ALERT VIN = 12V, VID = 0.6V to 0.9V, ALERT VIN = 12V, VID = 0.9V to 0.6V,
(1V/Div) Slew Rate = Slow, S-line (1V/Div) Slew Rate = Slow, S-line

20
RT3606BC
CORE VR Dynamic VID Up CORE VR Mode Transient
V CORE
V CORE
VCLK VCLK
VCLK VLCK
(1V/Div) UGATE1
(1V/Div)
V CORE VDIO
(200mV/Div) UGATE1
(20V/Div) LGATE1
VDIO
(1V/Div)
ALERT LGATE1
ALERT VIN = 12V, VID = 0.6V to 0.9V, (5V/Div)
(1V/Div) Slew Rate = Fast, S-line V CORE VIN = 12V, VID = 0.9V, PS0 to PS2, ILOAD = 1A
(20mV/Div)
CORE VR Mode Transient CORE VR Thermal Monitioring
V CORE
VCLK
VLCK UGATE1
(1V/Div)
VTSEN
UGATE1 (500mV/Div)
(20V/Div)
LGATE1
LGATE1
(5V/Div) VR_HOT
(1V/Div) VIN = 12V, VTSEN Sweep from 1V to 2V
V CORE VIN = 12V, VID = 0.9V, PS2 to PS0, ILOAD = 1A
(20mV/Div)
Time (50μs/Div) Time (5ms/Div)
VIMON vs. Load Current AXG VR Power On from EN

2.5
2.0
VAXG
VIMON (V)
(300mV/Div)
1.5
PGOOD
(1V/Div)
1.0
UG_GT1
(10V/Div)
0.5
EN
(1V/Div) VIN = 12V, No Load, VID = 0.8V, SET2 pin tied to 5V
0.0
0 20 40 60 80 100 Time (500μs/Div)
Load Current (A)

21
RT3606BC
AXG VR Power Off from EN AXG VR OCP
VAXG
VAXG PGOOD PGOOD

(300mV/Div) (1V/Div)
PGOOD VAXG
(1V/Div) (200mV/Div)
UG_GT1
UG_GT1 (20V/Div)
(10V/Div)
EN I LOAD
(1V/Div) (50A/Div)
VIN = 12V, No Load, VID = 0.8V, SET2 pin tied to 5V
AXG VR OVP AXG VR Dynamic VID Up
PGOOD VAXG
PGOOD VAXG VCLK

(1V/Div)
VCLK
VAXG (1V/Div)
(500mV/Div) VAXG VDIO
UG_GT1 (200mV/Div)
(20V/Div) VDIO
(1V/Div)
LG_GT1 ALERT
(5V/Div) ALERT VIN = 12V, VID = 0.6V to 0.9V,
VIN = 12V, VID = 0.9V (1V/Div) Slew Rate = Slow, S-line
AXG VR Dynamic VID Down AXG VR Dynamic VID Up
VAXG
VAXG
VCLK VCLK
VCLK VCLK
(1V/Div) (1V/Div)
VAXG VDIO VAXG VDIO
VDIO VDIO
(1V/Div) (1V/Div)
ALERT ALERT
ALERT VIN = 12V, VID = 0.9V to 0.6V, ALERT VIN = 12V, VID = 0.6V to 0.9V,
(1V/Div) Slew Rate = Slow, S-line (1V/Div) Slew Rate = Fast, S-line

22
RT3606BC
AXG VR Mode Transient AXG VR Mode Transient
VAXG
VAXG
VCLK VCLK
VLCK UGATE1 VLCK UGATE1
(1V/Div) (1V/Div)
UG_GT1 UG_GT1
(20V/Div) (20V/Div)
LGATE1 LGATE1
LG_GT1 LG_GT1
(5V/Div) (5V/Div)
VAXG VIN = 12V, VID = 0.9V, PS0 to PS2, ILOAD = 1A VAXG VIN = 12V, VID = 0.9V, PS2 to PS0, ILOAD = 1A
AXG VR Thermal Monitioring VIMONA vs. Load Current

2.5
2.0
VIMONA (V)
1.5
VTSENA
(500mV/Div) 1.0
0.5
VR_HOT
(1V/Div) VIN = 12V, VTSENA Sweep from 1V to 2V
0.0
Time (5ms/Div) 0 20 40 60 80 100
Load Current (A)

23
RT3606BC
Applications information
The RT3606BC includes two voltage rails : a 3/2/1
multiphase synchronous buck controller, the CORE VR, Current feedback signal
and a 2/1 multiphase synchronous buck controller, the

Comp signal
AXG VR, designed to meet Intel IMVP8 compatible CPUs
specification with a serial SVID control interface. The
controller uses an ADC to implement the all kinds of
settings to save total pin number for easy use and
increasing PCB space utilization. RT3606BC is used in PWM1
notebook, desktop computers and servers.
PWM2
General loop Function

PWM3
TM
G-NAVP Control Mode
PWM4
The RT3606BC adopts the G-NAVPTM controller, which is
a current mode constant on-time control with DC offset Figure 1 (b). G-NAVPTM CCM behavior waveforms in
cancellation. The approach can not only improve DC offset CCM in Load Transient.
problem for increasing system accuracy but also provide
fast transient response. When current feedback signal
Diode Emulation Mode (DEM)
reaches comp signal, the RT3606BC generates an on-
time width to achieve PWM modulation. Figure 1 shows As well-known, the dominate power loss is switching
the basic G-NAVPTM behavior waveforms in continuous related loss during light load, hence VR needs to be
conduct mode (CCM). operated in asynchronous mode (or called discontinuous
conduct mode, DCM) to reduce switching related loss
Current feedback signal since switching frequency is dependent on loading in the
asynchronous mode. The RT3606BC can operate in diode
emulation mode (DEM) to improve light load efficiency. In
DEM operation, the behavior of the low side MOSFET(s)
needs to work like a diode, that is, the low side MOSFET(s)
Comp signal
will be turned on when the phase voltage is a negative
PWM1
value, i.e. the inductor current follows from Source to Drain
PWM2 of low-side MOSFET(s). And the low-side MOSFET(s) will
be turned off when phase voltage is a positive value, i.e.
PWM3
reversed current is not allowed. Figure 2 shows the control
behavior in DEM. Figure 3 shows the G-NAVPTM operation
PWM4
in DEM to illustrate the control behaviors. When load
decreases, the discharge time of output capacitors
Figure 1 (a). G-NAVPTM CCM behavior waveforms in
increases during UGATE and LGATE are turned off. Hence,
CCM in Steady State
the switching frequency and switching loss will be reduced
to improve efficiency in light load condition.

24
RT3606BC
Inductor current
Phase node
UGATE
LGATE
Figure 2. Diode Emulation Mode (DEM) in Steady State
Inductor
current signal
Output capacitor COMP signal

discharge slope
UGATE
LGATE
Figure 3. (a)
Inductor
current signal
Output capacitor COMP signal

discharge slope
UGATE
LGATE
Figure 3. (b)
Figure 3. G-NAVPTM operation in DEM. (a) : The load is lighter, output capacitor discharge slope is smaller and the
switching frequency is lower. (b) : The load is increasing, output capacitor discharge slope is increased and switching
frequency is increased, too.

25
RT3606BC
Phase Interleaving Function
Function 2 Function 1
RT3606BC is a multiphase controller, which has a phase <5:0> <5:0>
80µA
interleaving function, 120 degree phase shift for 3-phase
operation and 180 degree phase shift for 2-phase operation ADC
VREF
which can help reduce output voltage ripple and EMI
problem. Function 1
Register R1
SETX
Multi-Function Pin Setting Mechanism
(SETAX)
For reducing total pin number of package, SET [1:3] and Function 2 R2
Register
SETA[1:2] pins adopt the multi-function pin setting
mechanism in the RT3606BC. SET [1:3] and SETA[1:2]
are used to set CORE VR and AXG VR, respectively. Figure Function 2 Function 1
4 illustrates this operating mechanism. The voltage at <5:0> <5:0>
80µA
VREF pin will be pulled up to 3.2V after power ready (POR).
ADC
First, external voltage divider is used to set the Function1
VREF
and then internal current source 80μA is used to set the
Function 1
Function2. The setting voltage of Function1 and Function2 Register R1
can be represented as SETX
R2  3.2V (SETAX)
VFunction1  Function 2 R2
R1  R2
Register
VFunction2  80  R1 R2
R1  R2
All function setting will be done within 500ì s after power Figure 4. Multi-Function Pin Setting Mechanism
ready (POR), and the voltage at VREF pin will fix to 0.6V
Connects a R3 resistor from SETx pin or SETAx pin to
after all function setting over.
the middle node of voltage divider can help to fine tune the
If VFunction1 and VFunction2 are determined, R1 and R2 can set voltage of Function2, which does not affect the set
be calculated as follows : voltage of Function1. The Figure 5 shows the setting
3.2V  VFunction2 method and the set voltage of Function 1 and Function2
R1 
80  VFunction1
can be represented as :
R1 VFunction1 R2  3.2V
R2  VFunction1 
3.2V  VFunction1 R1 R2
In addition, Richtek provides a Microsoft Excel-based VFunction2  80 Α   R3  R1 R2 
 R1 R2 
spreadsheet to help design the SETx and SETAx resistor
By the way, SET1 and SET2 are used to set CORE rail
network for RT3606BC.
setting and SETA1 and SETA2 are used to set AXG rail
setting. The setting of SET3 is suitable for both CORE
rail and AXG rail. Table 2 summarizes the overall pin setting
function. Table 3 and Table 4 show the SET3 pin setting
function table.

26
RT3606BC
Table 2. Pin Setting Function Table
Function1 Function2
DVID threshold
Set1 (CORE Rail) ICCMAX
Over Current Protection (OCP) threshold
DVID width Quick Response (QR) threshold
Set2 (CORE Rail)
Ramp Amplitude Quick Response (QR) width
Enable PSYS Function
VR Address
Enable High Switching Frequency Ramp
Enable Zero Load-line
DVID Slew Rate
Set3 (CORE / AXG Rail) Enable Anti-overshoot Function
Disable DVID compensation
Anti-overshoot Behavior
Decrease GTU/SA Ramp Amplitude
Current Gain AI
(Only Active in max phase = 1 Application)
DVID threshold
SetA1 (AXG Rail) ICCMAXA
Over Current Protection (OCP) threshold
DVID width Quick Response (QR) threshold
SetA2 (AXG Rail)
Ramp Amplitude Quick Response (QR) width

Table 3. SET3 Pin Setting for VR Address, Enable Zero Load-line, Enable Anti-overshoot Function,
Anti-overshoot Behavior, and Current Gain AI
VSET3  R2  V
REF AHTI_OVS AI
R1  R2 VR Address Zero Load Line ANTI_OVS
Behavior GAIN
Min Typical Max Unit
0.000 10.948 21.896 mV 1X
High-Low-Floating
25.024 35.973 46.921 mV 2X
Disable
50.049 60.997 71.945 mV 1X
High-Floating
75.073 86.022 96.970 mV CORE : With LL 2X
100.098 111.046 121.994 mV AXG : With LL 1X
High-Low-Floating
125.122 136.070 147.019 mV 2X
Enable
150.147 161.095 172.043 mV 1X
High-Floating
175.171 186.119 197.067 mV CORE : 00 2X
200.196 211.144 222.092 mV AXG : 01 1X
High-Low-Floating
225.220 236.168 247.116 mV 2X
Disable
250.244 261.193 272.141 mV 1X
High-Floating
275.269 286.217 297.165 mV CORE : With LL 2X
300.293 311.241 322.190 mV AXG : W/O LL 1X
High-Low-Floating
325.318 336.266 347.214 mV 2X
Enable
350.342 361.290 372.239 mV 1X
High-Floating
375.367 386.315 397.263 mV 2X


27
RT3606BC
VSET3  R2  V
REF AHTI_OVS AI
R1  R2 VR Address Zero Load Line ANTI_OVS
Behavior GAIN
400.391 411.339 422.287 mV 1X
High-Low-Floating
425.415 436.364 447.312 mV 2X
Disable
450.440 461.388 472.336 mV 1X
High-Floating
475.464 486.413 497.361 mV CORE : With LL 2X
500.489 511.437 522.385 mV AXG : With LL 1X
High-Low-Floating
525.513 536.461 547.410 mV 2X
Enable
550.538 561.486 572.434 mV 1X
High-Floating
575.562 586.510 597.458 mV CORE : 00 2X
600.587 611.535 622.483 mV AXG : 02 1X
High-Low-Floating
625.611 636.559 647.507 mV 2X
Disable
650.635 661.584 672.532 mV 1X
High-Floating
675.660 686.608 697.556 mV CORE : With LL 2X
700.684 711.632 722.581 mV AXG : W/O LL 1X
High-Low-Floating
725.709 736.657 747.605 mV 2X
Enable
750.733 761.681 772.630 mV 1X
High-Floating
775.758 786.706 797.654 mV 2X
800.782 811.730 822.678 mV 1X
High-Low-Floating
825.806 836.755 847.703 mV 2X
Disable
850.831 861.779 872.727 mV 1X
High-Floating
875.855 886.804 897.752 mV CORE : With LL 2X
900.880 911.828 922.776 mV AXG : With LL 1X
High-Low-Floating
925.904 936.852 947.801 mV 2X
Enable
950.929 961.877 972.825 mV 1X
High-Floating
975.953 986.901 997.849 mV CORE : 01 2X
1000.978 1011.926 1022.874 mV AXG : 00 1X
High-Low-Floating
1026.002 1036.950 1047.898 mV 2X
Disable
1051.026 1061.975 1072.923 mV 1X
High-Floating
1076.051 1086.999 1097.947 mV CORE : W/O LL 2X
1101.075 1112.023 1122.972 mV AXG : With LL 1X
High-Low-Floating
1126.100 1137.048 1147.996 mV 2X
Enable
1151.124 1162.072 1173.021 mV 1X
High-Floating
1176.149 1187.097 1198.045 mV 2X


28
RT3606BC
VSET3  R2  V
REF AHTI_OVS AI
R1 R2 VR Address Zero Load Line ANTI_OVS
Behavior GAIN
1201.173 1212.121 1223.069 mV 1X
High-Low-Floating
1226.197 1237.146 1248.094 mV 2X
Disable
1251.222 1262.170 1273.118 mV 1X
High-Floating
1276.246 1287.195 1298.143 mV CORE : With LL 2X
1301.271 1312.219 1323.167 mV AXG : With LL 1X
High-Low-Floating
1326.295 1337.243 1348.192 mV 2X
Enable
1351.320 1362.268 1373.216 mV 1X
High-Floating
1376.344 1387.292 1398.240 mV CORE : 01 2X
1401.369 1412.317 1423.265 mV AXG : 03 1X
High-Low-Floating
1426.393 1437.341 1448.289 mV 2X
Disable
1451.417 1462.366 1473.314 mV 1X
High-Floating
1476.442 1487.390 1498.338 mV CORE : With LL 2X
1501.466 1512.414 1523.363 mV AXG : W/O LL 1X
High-Low-Floating
1526.491 1537.439 1548.387 mV 2X
Enable
1551.515 1562.463 1573.412 mV 1X
High-Floating
1576.540 1587.488 1598.436 mV 2X


29
RT3606BC
Table 4. SET3 Pin Setting for Enable PSYS Function, Enable High Switching Frequency Ramp, DVID Slew
Rate, Disable DVID compensation, Decrease GTU/SA Ramp Amplitude
(Only Active in max phase =1 Application)
Decrease GTU/SA
VSET3  80μA  R1 R2 EN HIGH Disable DIVD Ramp
R1  R2 EN PSYS DVID SR
FREQ RAMP Compensation (Only active as max
Min Typical Max Unit phase number =1)
0.000 10.948 21.896 mV Disable
25.024 35.973 46.921 mV Enable
Disable
50.049 60.997 71.945 mV Disable
75.073 86.022 96.970 mV Enable
33.75mV/s
100.098 111.046 121.994 mV Disable
125.122 136.070 147.019 mV Enable
Enable
150.147 161.095 172.043 mV Disable
175.171 186.119 197.067 mV Enable
Disable
200.196 211.144 222.092 mV Disable
225.220 236.168 247.116 mV Enable
Disable
250.244 261.193 272.141 mV Disable
275.269 286.217 297.165 mV Enable
11.25mV/s
300.293 311.241 322.190 mV Disable
325.318 336.266 347.214 mV Enable
Enable
350.342 361.290 372.239 mV Disable
375.367 386.315 397.263 mV Enable
Disable
400.391 411.339 422.287 mV Disable
425.415 436.364 447.312 mV Enable
Disable
450.440 461.388 472.336 mV Disable
475.464 486.413 497.361 mV Enable
33.75mV/s
500.489 511.437 522.385 mV Disable
525.513 536.461 547.410 mV Enable
Enable
550.538 561.486 572.434 mV Disable
575.562 586.510 597.458 mV Enable
Enable
600.587 611.535 622.483 mV Disable
625.611 636.559 647.507 mV Enable
Disable
650.635 661.584 672.532 mV Disable
675.660 686.608 697.556 mV Enable
11.25mV/s
700.684 711.632 722.581 mV Disable
725.709 736.657 747.605 mV Enable
Enable
750.733 761.681 772.630 mV Disable
775.758 786.706 797.654 mV Enable

30
RT3606BC
Decrease GTU/SA
VSET3  80μA  R1 R2 EN HIGH Disable DIVD Ramp
R1  R2 EN PSYS DVID SR
FREQ RAMP Compensation (Only active as max
Min Typical Max Unit phase number = 1)
800.782 811.730 822.678 mV Disable
825.806 836.755 847.703 mV Enable
Disable
850.831 861.779 872.727 mV Disable
875.855 886.804 897.752 mV Enable
33.75mV/s
900.880 911.828 922.776 mV Disable
925.904 936.852 947.801 mV Enable
Enable
950.929 961.877 972.825 mV Disable
975.953 986.901 997.849 mV Enable
Disable
1000.978 1011.926 1022.874 mV Disable
1026.002 1036.950 1047.898 mV Enable
Disable
1051.026 1061.975 1072.923 mV Disable
1076.051 1086.999 1097.947 mV Enable
11.25mV/s
1101.075 1112.023 1122.972 mV Disable
1126.100 1137.048 1147.996 mV Enable
Enable
1151.124 1162.072 1173.021 mV Disable
1176.149 1187.097 1198.045 mV Enable
Enable
1201.173 1212.121 1223.069 mV Disable
1226.197 1237.146 1248.094 mV Enable
Disable
1251.222 1262.170 1273.118 mV Disable
1276.246 1287.195 1298.143 mV Enable
33.75mV/s
1301.271 1312.219 1323.167 mV Disable
1326.295 1337.243 1348.192 mV Enable
Enable
1351.320 1362.268 1373.216 mV Disable
1376.344 1387.292 1398.240 mV Enable
Enable
1401.369 1412.317 1423.265 mV Disable
1426.393 1437.341 1448.289 mV Enable
Disable
1451.417 1462.366 1473.314 mV Disable
1476.442 1487.390 1498.338 mV Enable
11.25mV/s
1501.466 1512.414 1523.363 mV Disable
1526.491 1537.439 1548.387 mV Enable
Enable
1551.515 1562.463 1573.412 mV Disable
1576.540 1587.488 1598.436 mV Enable


31
RT3606BC
Function 2 Function 1
Anti-Overshoot and Anti-Overshoot Behavior
<5:0> <5:0> The anti-overshoot function can be enabled or disabled by
80µA
setting the voltage on SET3 with an external voltage
ADC
divider. During the anti-overshoot function is triggered, the
VREF
high side and low side MOS will both turn off. Therefore,
Function 1
Register
the output voltage adds the forward voltage of the MOS
R1
SETX R3 parasitic body diode will crosses on the inductor to speed
(SETAX) up the discharge speed and eases the overshoot
Function 2 R2
magnitude. However, if the MOS driver has tri-state delay
Register
time, the performance of the anti-overshoot function will
be degenerated. To prevent this phenomenon, RT3606BC
Function 2 Function 1 provides two kinds of anti-overshoot low side MOS behavior.
<5:0> <5:0>
80µA With the driver has tri-state delay time, the behavior of
anti-overshoot can choose as high-low-floating, and with
ADC
VREF
the driver without tri-state delay time, the behavior of anti-
overshoot can choose as high-floating.
Function 1
Register R1
SETX R3 High Switching Frequency Ramp
(SETAX) The switching frequency of RT3606BC can support from
Function 2 R2
Register 300kHz to 1.1MHz, however, with higher switching
frequency, the ramp is needed to increase simultaneously
to improve the system stability and smooth the mode
Figure 5. Multi-Function Pin Setting Mechanism with a
transient performance. As switching is higher than 550kHz,
R3 Resistor to Fine Tune the Set Voltage of Function2
the high switching frequency ramp is suggested to be
enabled. The high switching frequency ramp can be
VR Rail Addressing Setting
enabled or disabled by the internal current source 80μA
The VR address of RT3606BC can be flipped by setting and the parallel of the high low side resistor on SET3 pin.
the voltage on SET3 with an external voltage divider as
shown in Figure 6. The voltage at VREF pin will be pulled Decrease GTU/SA Ramp Amplitude (Only Active in
up to 3.2V after power ready (POR) and the voltage at max phase = 1 Application)
VREF pin will fix to 0.6V within 500μs after power ready If RT3606BC apply in GTU or SA application and the
(POR). Besides, when AXG rail address is set to 2, the maximum phase number is 1. The ramp amplitude will
boot voltage of AXG rail is 1.05V. automatically increase to improve the stability. This
Function 1
function can be disabled to improve the transient
<5:0> VREF performance by the internal current source 80μA and the
ADC parallel of the high low side resistor on SET3 pin.
R1
Function 1 SET3
Register
R2
Figure 6. VR Rail Addressing and Zero Load-Line Setting

for SET3

32
RT3606BC
Precise Reference Current Generation, IBIAS VDDIO
Analog circuits need very precise reference voltage/current

to drive/set these analog devices. The RT3606BC provides VR_HOT
a 2V voltage source at the IBIAS pin, and a 100kΩ resistor

is required to be connected between the IBIAS pin and 80µA
analog ground to generate a very precise reference current.
Through this connection, the RT3606BC will generate a TSEN(A)
-
20μA current from the IBIAS pin to analog ground, and + RNTC
this 20μA current will be mirrored inside the RT3606BC R1
1.092V
for internal use. The IBIAS pin can only be connected R2
with a 100kΩ resistor to GND for internal analog circuit
use. The resistance error of this resistor is recommended
Figure 8. VR_HOT Circuit
to be 1% or smaller. Figure 7 shows the IBIAS setting
circuit.
Power Ready (POR) Detection
Current Mirror
During start-up, the RT3606BC detects the voltage at the
2V + 20µA
voltage input pins: VCC, EN and DVD. When VCC > 4.34V
- and VDVD > 2V, the RT3606BC recognizes the power state
of system to be ready (POR = high) and waits for enable
IBIAS command at the EN pin. After POR = high and VEN >
100k
0.7V, the RT3606BC will enter start-up sequence. If the
Figure 7. IBIAS Setting Circuit voltage at any voltage pin drops below low threshold (POR
= low), the RT3606BC will enter power down sequence
TSEN, TSENA and VR_HOT and all the functions will be disabled. Normally, connecting
system voltage VTT (1.05V) to the EN pin and power stage
The VR_HOT signal is an open-drain signal which is used
VIN (12V, through a voltage divider) to the DVD pin is
for VR thermal protection. When the sensed voltage in
recommended. 2ms (max) after the chip has been
TSEN(A) pin is less than 1.092, the VR_HOT signal will
enabled, the SVID circuitry will be ready. All the protection
be pulled-low to notify CPU that the thermal protection
latches (OVP, OCP, UVP) will be cleared only by VCC.
needs to work. According to Intel VR definition, VR_HOT
The condition of VEN = low will not clear these latches.
signal needs acting if VR power chain temperature
Figure 9 and Figure 10 show the POR detection and the
exceeds 100°C. Placing an NTC thermistor at the hottest
timing chart for POR process, respectively.
area in the VR power chain and its connection is shown
in Figure 8, to design the voltage divider elements (R1, Under Voltage Lockout (UVLO)
R2 and NTC) so that VTSEN(A) = 1.092V at 100°C. The
During normal operation, if the voltage at the VCC drops
resistance error of TSEN network is recommended to be
below POR threshold 3.95V (min) or DVD voltage drops
1% or smaller.
below POR threshold 1.3V, the VR triggers UVLO. The
VTSEN(Α)  80 Α  (R1//(R2  RNTC (100C ))
UVLO protection forces all high-side MOSFETs and low-
side MOSFETs off by shutting down internal PWM logic
drivers.

33
RT3606BC
VIN 5V output voltage. Users can disable offset function by simply
connecting OFSM pin to GND. Figure 11 shows a voltage
VCC CP
+
divider used to set no load offset voltage. No load offset
R1 4.34V -
voltage setting is :
DVD CP
+ POR VOFS_CORE  0.4  ( VOFSM  1.7)
R2 2V -
The range of VOFS_CORE is between −500mV and 590mV
Chip
VTT EN CP
Enable and the resolution is 10mV.
+
1.05V
0.7V - For example, a 100mV no load offset requirement, VOFSM
needs to be set as 1.95V.
Figure 9. POR Detection
SVID Offset
Register
VCC VCC SVID VID VID_REF
+
++ DAC
Register
DVD
R1
OFSM PIN Offset
POR ADC Register
R2
EN 2ms
SVID Invalid Valid Invalid Figure 11. No Load Offset Circuit
Switching Frequency Setting

Figure 10. Timing Chart for POR Process
RT3606BC is one kind of constant on-time control. The
patented CCRCOT (Constant Current Ripple COT)
technology can generate an adaptive on-time, the on-time
CORE VR
will vary with the input voltage and VID code to obtain a
Phase Disable (Before POR) constant current ripple, so that the output voltage ripple
The number of active phases is determined by the internal can be controlled nearly like a constant as different input
circuitry that monitors the ISENxN voltages during startup. and output voltages change.
Normally, the VR operates as a 3-phase PWM controller. For CORE VR, connect a resistor RTON between input
Pulling ISEN3N to VCC programs a 2-phase operation, terminal and TONSET pin to set the on-time width.
and pulling ISEN2N and ISEN3N to VCC programs a 1- RTON  4.73p  1.2
phase operation. Before POR, VR detects whether the TON  (VDAC  1.2)
VIN  VDAC
voltages of ISEN2N and ISEN3N are higher than “VCC− R  4.73p  VDAC
TON  TON (VDAC  1.2)
1V” respectively to decide how many phases should be VIN  VDAC
active. Phase selection is only active during POR. When For better efficiency of the given load range, the maximum
POR = high, the number of active phases is determined switching frequency is suggested to be :
and latched. The unused ISENxP pins are recommended FSW(MAX) 
IccTDC  RON_LS,max 
to be connected to VCC and unused PWM pins can be VID1   DCR   N  RLL 
N  nLS 
left floating.  IccTDC  RON_LS,max RON_HS,max  IccTDC  RON_LS,max 
 VIN(MAX)        TON  TD  TON,VAR      TD
 N  nLS nHS   N  nLS 
NO Load Offset (Platform) Where Fsw(MAX) is the maximum switching frequency, VID1
The CORE VR features no load offset function which is the typical VID of application, VIN(MAX) is the maximum
provides the possibility of wide range positive offset of application input voltage, IccTDC is the thermal design
current of application, N is the phase number. The
RON_HS,max is the maximum equivalent high-side RDS(ON),

34
RT3606BC
and nHS is the number of high-side MOSFETs; RON_LS,max Total Current Sense
is the maximum equivalent low-side RDS(ON), and nLS is Total current sense method is a patented topology, unlike
the number of low-side MOSFETs. TD is the summation of conventional current sense method need a NTC resistor
the high-side MOSFET delay time and the rising time, in per phase current loop for thermal compensation.
TON,VAR is the TON variation value. DCR is the inductor RT3606BC adopts the total current sense method requiring
DCR, and RLL is the loadline setting. In addition, Richtek only one NTC resistor for thermal compensation, and NTC
provides a Microsoft Excel-based spreadsheet to help resistor cost can be saved by using this method. Figure
design the RTON for RT3606BC. 13 shows the total current sense method which connects
When load increases, on-time keeps constant. The off- the resistor network between IMON pin and VREF pin to
time width will be reduced so that loading can load more set a part of current loop gain for load line (droop) setting
power from input terminal to regulate output voltage. Hence and set accurate over current protection.
the loading current usually increases in case the switching VIMON  VREF = DCR  REQ  (IL1 +IL2 +IL3 )
RCS
frequency also increases. Higher switching frequency
REQ includes a NTC resistor to compensate DCR thermal
operation can reduce power components' size and PCB
drifting for high accuracy load-line (droop).
space, trading off the whole efficiency since switching VCORE
IL1
related switching related loss increases, vice versa. L DCR
Per Phase Current Sense R C
In the RT3606BC, the current signal is used for load-line IMON ISEN1N +
ISEN1P
setting and over-current protection (OCP). The inductor - ISEN1N RCS
current sense method adopts the lossless current sensing

IL2
for allowing high efficiency as illustrated in Figure 12. When
L DCR
inductance and DCR time constant is equal to RXCX filter RNTC
network time constant, a voltage ILx x DCR will drop on Cx REQ R C
to generate inductor current signal. According to the Figure ISEN2N

+
ISEN2P
12, the ISENxN is as follows : - ISEN2N RCS
I  DCR
ISENxN  LX
RCSx IL3
L DCR
Where Lx/DCR = RXCX is held. The method can get high VREF
efficiency performance, but DCR value will be drifted by R C
temperature, a NTC resistor should add in the resistor ISEN3N ISEN3P

+
network in the IMON pin to achieve DCR thermal - ISEN3N RCS
compensation.
In RT3606BC design, the resistance of RCSx is restricted Figure 13. Total Current Sense Method
to 680Ω; moreover, the error of RCSx is recommended to Load-Line Setting (Droop)
be 1% or smaller. The G-NAVPTM topology can set load-line (droop) via the
ILx VCORE
current loop and the voltage loop, the load-line is a slope
LX DCR between load current ICC and output voltage VCORE as
shown Figure 14. Figure 15 shows the voltage control
RX CX
ISENxN
and current loop. By using the both loops, the load-line
ISENxP
+ (droop) can be set easily. The load-line set equation is :
- ISENxN RCSx 1  DCR  R
EQ
AI 3 RCS
RLL 
AV

R2
 m 
Figure 12. Lossless Current Sense Method R1

35
RT3606BC
VCOEE C2
C1 R2
Load line slope = -RLL -

R1 +
RLL x ICC
VID
Figure 16. Type I Compensator

ICC
Differential Remote Sense Setting

Figure 14. Load-Line (Droop)
The VR provides differential remote-sense inputs to
eliminate the effects of voltage drops along the PC board
VCORE
R2 traces, CPU internal power routes and socket contacts.
Voltage Loop TON Generator
- The CPU contains on-die sense pins, VCC_SENSE and
R1 +
+
VSS_SENSE. Connect RGND to VSS_SENSE and connect FB
-
IL1.2.3 to VCC_SENSE with a resistor to build the negative input
DCR L VID
1/3 path of the error amplifier as shown in Figure 17. The VDAC
+
-
R and the precision voltage reference are referred to RGND
C
ISEN1N + ISEN2N + RNTC for accurate remote sensing.
ISEN[1:3]P ISEN3N
+
IMON CPU VCC_SENSE
RCS
- VREF
ISEN[1:3]N
VOUT
REQ
FB R1
-
EA
Figure 15. Voltage Loop and Current Loop + COUT
+
VID
-
Compensator Design RGND R2
The compensator of RT3606BC doesn’t need a complex

type II or type III compensator to optimize control loop CPU VSS_SENSE
performance. It can adopt a simple type I compensator

(one pole, one zero) in G-NAVPTM topology to achieve Figure 17. Remote Sensing Circuit
constant output impedance design for Intel IMVP8 ACLL
Maximum Processor Current Setting, ICCMAX
specification. The one pole one zero compensator is
shown as Figure 16, the transfer function of compensator The maximum processor current ICCMAX can be set by
should be design as following transfer function to achieve the SET1 pin. ICCMAX register is set by an external voltage
constant output impedance, i.e. Zo(s) = load-line slope in divider with the multi-function mechanism. The table 5
the entire frequency range shows the ICCMAX setting on the SET1 pin. For example,
1 s ICCMAX = 80A, the VICCMAX needs to set as 0.503 typical.
GCON (S) 
AI   fsw
RLL 1  s Additionally, VIMON − VREF needs to be set as 1.6V at
ESR ICCMAX when the maximum phase > 1. As in 1-phase
Where AI is current loop gain, RLL is load line, fSW is application, the VIMON − VREF needs to be set as 0.4V at
switching frequency and ωESR is a pole that should be ICCMAX. The ICCMAX alert signal will be pulled to low
located at 1 / (COUT x ESR). Then the C1 and C2 should level if VIMON − VREF = 1.6V (for maximum phase > 1) or
be designed as VIMON − VREF = 0.4 (for 1-phase application).
C1  1 COUT  ESR
R1 π fSW C2 
R2

36
RT3606BC
Table 5. SET1 Pin Setting in ICCMAX
R2  3.2V VSET1  R2  3.2V
VSET1 
R1 R2 ICCMAX Unit R1 R2 ICCMAX Unit
Min Typical Max Unit Min Typical Max Unit
0.000 3.128 6.256 mV 0 A 475.464 478.592 481.720 mV 76 A
12.512 15.640 18.768 mV 2 A 487.977 491.105 494.233 mV 78 A
25.024 28.152 31.281 mV 4 A 500.489 503.617 506.745 mV 80 A
37.537 40.665 43.793 mV 6 A 513.001 516.129 519.257 mV 82 A
50.049 53.177 56.305 mV 8 A 525.513 528.641 531.769 mV 84 A
62.561 65.689 68.817 mV 10 A 538.025 541.153 544.282 mV 86 A
75.073 78.201 81.329 mV 12 A 550.538 553.666 556.794 mV 88 A
87.586 90.714 93.842 mV 14 A 563.050 566.178 569.306 mV 90 A
100.098 103.226 106.354 mV 16 A 575.562 578.690 581.818 mV 92 A
112.610 115.738 118.866 mV 18 A 588.074 591.202 594.330 mV 94 A
125.122 128.250 131.378 mV 20 A 600.587 603.715 606.843 mV 96 A
137.634 140.762 143.891 mV 22 A 613.099 616.227 619.355 mV 98 A
150.147 153.275 156.403 mV 24 A 625.611 628.739 631.867 mV 100 A
162.659 165.787 168.915 mV 26 A 638.123 641.251 644.379 mV 102 A
175.171 178.299 181.427 mV 28 A 650.635 653.763 656.891 mV 104 A
187.683 190.811 193.939 mV 30 A 663.148 666.276 669.404 mV 106 A
200.196 203.324 206.452 mV 32 A 675.660 678.788 681.916 mV 108 A
212.708 215.836 218.964 mV 34 A 688.172 691.300 694.428 mV 110 A
225.220 228.348 231.476 mV 36 A 700.684 703.812 706.940 mV 112 A
237.732 240.860 243.988 mV 38 A 713.196 716.325 719.453 mV 114 A
250.244 253.372 256.500 mV 40 A 725.709 728.837 731.965 mV 116 A
262.757 265.885 269.013 mV 42 A 738.221 741.349 744.477 mV 118 A
275.269 278.397 281.525 mV 44 A 750.733 753.861 756.989 mV 120 A
287.781 290.909 294.037 mV 46 A 763.245 766.373 769.501 mV 122 A
300.293 303.421 306.549 mV 48 A 775.758 778.886 782.014 mV 124 A
312.805 315.934 319.062 mV 50 A 788.270 791.398 794.526 mV 126 A
325.318 328.446 331.574 mV 52 A 800.782 803.910 807.038 mV 128 A
337.830 340.958 344.086 mV 54 A 813.294 816.422 819.550 mV 130 A
350.342 353.470 356.598 mV 56 A 825.806 828.935 832.063 mV 132 A
362.854 365.982 369.110 mV 58 A 838.319 841.447 844.575 mV 134 A
375.367 378.495 381.623 mV 60 A 850.831 853.959 857.087 mV 136 A
387.879 391.007 394.135 mV 62 A 863.343 866.471 869.599 mV 138 A
400.391 403.519 406.647 mV 64 A 875.855 878.983 882.111 mV 140 A
412.903 416.031 419.159 mV 66 A 888.368 891.496 894.624 mV 142 A
425.415 428.543 431.672 mV 68 A 900.880 904.008 907.136 mV 144 A
437.928 441.056 444.184 mV 70 A 913.392 916.520 919.648 mV 146 A
450.440 453.568 456.696 mV 72 A 925.904 929.032 932.160 mV 148 A
462.952 466.080 469.208 mV 74 A 938.416 941.544 944.673 mV 150 A

37
RT3606BC
R2  3.2V VSET1  R2  3.2V
VSET1 
R1 R2 ICCMAX Unit R1 R2 ICCMAX Unit
Min Typical Max Unit Min Typical Max Unit
950.929 954.057 957.185 mV 152 A 1426.393 1429.521 1432.649 mV 228 A
963.441 966.569 969.697 mV 154 A 1438.905 1442.033 1445.161 mV 230 A
975.953 979.081 982.209 mV 156 A 1451.417 1454.545 1457.674 mV 232 A
988.465 991.593 994.721 mV 158 A 1463.930 1467.058 1470.186 mV 234 A
1000.978 1004.106 1007.234 mV 160 A 1476.442 1479.570 1482.698 mV 236 A
1013.490 1016.618 1019.746 mV 162 A 1488.954 1492.082 1495.210 mV 238 A
1026.002 1029.130 1032.258 mV 164 A 1501.466 1504.594 1507.722 mV 240 A
1038.514 1041.642 1044.770 mV 166 A 1513.978 1517.107 1520.235 mV 242 A
1051.026 1054.154 1057.283 mV 168 A 1526.491 1529.619 1532.747 mV 244 A
1063.539 1066.667 1069.795 mV 170 A 1539.003 1542.131 1545.259 mV 246 A
1076.051 1079.179 1082.307 mV 172 A 1551.515 1554.643 1557.771 mV 248 A
1088.563 1091.691 1094.819 mV 174 A 1564.027 1567.155 1570.283 mV 250 A
1101.075 1104.203 1107.331 mV 176 A 1576.540 1579.668 1582.796 mV 252 A
1113.587 1116.716 1119.844 mV 178 A 1589.052 1592.180 1595.308 mV 254 A
1126.100 1129.228 1132.356 mV 180 A
1138.612 1141.740 1144.868 mV 182 A
1151.124 1154.252 1157.380 mV 184 A
1163.636 1166.764 1169.892 mV 186 A
1176.149 1179.277 1182.405 mV 188 A
1188.661 1191.789 1194.917 mV 190 A
1201.173 1204.301 1207.429 mV 192 A
1213.685 1216.813 1219.941 mV 194 A
1226.197 1229.326 1232.454 mV 196 A
1238.710 1241.838 1244.966 mV 198 A
1251.222 1254.350 1257.478 mV 200 A
1263.734 1266.862 1269.990 mV 202 A
1276.246 1279.374 1282.502 mV 204 A
1288.759 1291.887 1295.015 mV 206 A
1301.271 1304.399 1307.527 mV 208 A
1313.783 1316.911 1320.039 mV 210 A
1326.295 1329.423 1332.551 mV 212 A
1338.807 1341.935 1345.064 mV 214 A
1351.320 1354.448 1357.576 mV 216 A
1363.832 1366.960 1370.088 mV 218 A
1376.344 1379.472 1382.600 mV 220 A
1388.856 1391.984 1395.112 mV 222 A
1401.369 1404.497 1407.625 mV 224 A
1413.881 1417.009 1420.137 mV 226 A

38
RT3606BC
Dynamic VID (DVID) Compensation
When VID transition event occurs, a charger current will be generated in the loop to cause DVID performance. However,
the DVID performance will be deteriorated by this induced charger current, this phenomenon is called droop effect. The
droop effect is shown in Figure 18, when VID up transition occurs, the output capacitor will be charged by inductor
current. Since current signal is sensed in inductor, an induced charge current will appear in control loop. The induced
charge current will produce a voltage drop in R1 to cause output voltage to have a droop effect. Due to this, VID transition
performance will be deteriorated.
Charge current
L
VIN
Q1 CO1 CO2
Q2
Gate
Driver RESR
CPU
Ai
Induced charge C2 Output voltage
current signal
R2 C1
CCRCOT
VIN COMP - R1
-
VID tON + EA
+ IDROOP
VID
VID Transition
Figure 18. Droop Effect in VID transition
DVID_Width
(SET2)
DVID_Threshold
(SET1)
Figure 19. Definition of Virtual Charge Current Signal
RT3606BC provide a DVID compensation function. A virtual charge current signal can be established by the SET1/SET2
pins to cancel the real induced charge current signal and the virtual charge current signal is defined in Figure 19. Figure
20 shows the operation of canceling droop effect. A virtual charge current signal is established first and then VID signal
plus virtual charge current signal to be generated on the FB pin. Hence, an induced charge current signal flows to R1
and is cancelled to reduce droop effect.

39
RT3606BC
Charge current
L
VIN
Q1 CO1 CO2
Q2 Output voltage
Gate
Driver RESR
CPU
Ai C2
Induced charge
current signal C1
R2
CCRCOT
IDROOP
VIN COMP - R1
-
VID tON + EA Virtual Charge Current
+
IDROOP has a great cancellation by

Slew Rate
adding a suitable virtual charge + VID
Control
current VID Transition
DVID Event
Virtual Charge
Current SET1
Generator
Figure 20. DVID Compensation
Table 6 show the DVID_Threshold on the SET1 pin with internal 80μA current source and Table 7 describes DVID_Width
settings in SET2 pin with external voltage divider. For example, 39.67mV DVID_Threshold (SR = 11.25mV/μs) / 119mV
DVID_threshold (SR = 33.75mV/μs) and 36μs DVID_Width are designed (OCP sets as 110% ICCMAX, RSET sets as
133% low frequency ramp / 200% high frequency ramp). According to the Table 6 and Table 7, the DVID_Threshold set
voltage should be between 0.4254V to 0.4473V and the DVID_Width set voltage should be between 1.051V to 1.073V.
Please note that a high accuracy resistor is needed for this setting, < 1% error tolerance is recommended.

40
RT3606BC
Table 6. SET1 Pin Setting for DVID_Threshold
R1 R2
VSET1 = 80Α  DVID_Threshold
R1+R2
OCP = %ICCMAX
DVID SR DVID SR
= 11.25mV/s = 33.75mV/s
0.000 10.948 21.896 mV NA
25.024 35.973 46.921 mV 110%
50.049 60.997 71.945 mV 120%
75.073 86.022 96.970 mV 130%
18.33mV 55mV
100.098 111.046 121.994 mV 140%
125.122 136.070 147.019 mV 150%
150.147 161.095 172.043 mV 160%
175.171 186.119 197.067 mV NA
200.196 211.144 222.092 mV NA
225.220 236.168 247.116 mV 110%
250.244 261.193 272.141 mV 120%
275.269 286.217 297.165 mV 130%
29mV 87mV
300.293 311.241 322.190 mV 140%
325.318 336.266 347.214 mV 150%
350.342 361.290 372.239 mV 160%
375.367 386.315 397.263 mV NA
400.391 411.339 422.287 mV NA
425.415 436.364 447.312 mV 110%
450.440 461.388 472.336 mV 120%
475.464 486.413 497.361 mV 130%
39.67mV 119mV
500.489 511.437 522.385 mV 140%
525.513 536.461 547.410 mV 150%
550.538 561.486 572.434 mV 160%
575.562 586.510 597.458 mV NA
600.587 611.535 622.483 mV NA
625.611 636.559 647.507 mV 110%
650.635 661.584 672.532 mV 120%
675.660 686.608 697.556 mV 130%
50.33mV 151mV
700.684 711.632 722.581 mV 140%
725.709 736.657 747.605 mV 150%
750.733 761.681 772.630 mV 160%
775.758 786.706 797.654 mV NA

41
RT3606BC
R1 R2
VSET1 = 80Α  DVID_Threshold
R1+R2
OCP = %ICCMAX
DVID SR DVID SR
= 11.25mV/s = 33.75mV/s
800.782 811.730 822.678 mV NA
825.806 836.755 847.703 mV 110%
850.831 861.779 872.727 mV 120%
875.855 886.804 897.752 mV 130%
61mV 183mV
900.880 911.828 922.776 mV 140%
925.904 936.852 947.801 mV 150%
950.929 961.877 972.825 mV 160%
975.953 986.901 997.849 mV NA
1000.978 1011.926 1022.874 mV NA
1026.002 1036.950 1047.898 mV 110%
1051.026 1061.975 1072.923 mV 120%
1076.051 1086.999 1097.947 mV 130%
71.67mV 215mV
1101.075 1112.023 1122.972 mV 140%
1126.100 1137.048 1147.996 mV 150%
1151.124 1162.072 1173.021 mV 160%
1176.149 1187.097 1198.045 mV NA
1201.173 1212.121 1223.069 mV NA
1226.197 1237.146 1248.094 mV 110%
1251.222 1262.170 1273.118 mV 120%
1276.246 1287.195 1298.143 mV 130%
82.33mV 247mV
1301.271 1312.219 1323.167 mV 140%
1326.295 1337.243 1348.192 mV 150%
1351.320 1362.268 1373.216 mV 160%
1376.344 1387.292 1398.240 mV NA
1401.369 1412.317 1423.265 mV NA
1426.393 1437.341 1448.289 mV 110%
1451.417 1462.366 1473.314 mV 120%
1476.442 1487.390 1498.338 mV 130%
93mV 279mV
1501.466 1512.414 1523.363 mV 140%
1526.491 1537.439 1548.387 mV 150%
1551.515 1562.463 1573.412 mV 160%
1576.540 1587.488 1598.436 mV NA

42
RT3606BC
Table 7. SET2 Pin Setting for DVID_Width
R2 RSET
VSET2 = VCC 
R1+R2 %410k RTON
DVID_Width
Low FSW High FSW
Ramp Ramp
0.000 10.948 21.896 mV 100% 133%
25.024 35.973 46.921 mV 117% 167%
50.049 60.997 71.945 mV 133% 200%
75.073 86.022 96.970 mV 150% 233%
6s
100.098 111.046 121.994 mV 167% 267%
125.122 136.070 147.019 mV 183% 300%
150.147 161.095 172.043 mV 200% 333%
175.171 186.119 197.067 mV 217% 367%
200.196 211.144 222.092 mV 100% 133%
225.220 236.168 247.116 mV 117% 167%
250.244 261.193 272.141 mV 133% 200%
275.269 286.217 297.165 mV 150% 233%
12s
300.293 311.241 322.190 mV 167% 267%
325.318 336.266 347.214 mV 183% 300%
350.342 361.290 372.239 mV 200% 333%
375.367 386.315 397.263 mV 217% 367%
400.391 411.339 422.287 mV 100% 133%
425.415 436.364 447.312 mV 117% 167%
450.440 461.388 472.336 mV 133% 200%
475.464 486.413 497.361 mV 150% 233%
18s
500.489 511.437 522.385 mV 167% 267%
525.513 536.461 547.410 mV 183% 300%
550.538 561.486 572.434 mV 200% 333%
575.562 586.510 597.458 mV 217% 367%
600.587 611.535 622.483 mV 100% 133%
625.611 636.559 647.507 mV 117% 167%
650.635 661.584 672.532 mV 133% 200%
675.660 686.608 697.556 mV 150% 233%
24s
700.684 711.632 722.581 mV 167% 267%
725.709 736.657 747.605 mV 183% 300%
750.733 761.681 772.630 mV 200% 333%
775.758 786.706 797.654 mV 217% 367%
800.782 811.730 822.678 mV 100% 133%
825.806 836.755 847.703 mV 117% 167%
850.831 861.779 872.727 mV 133% 200%
875.855 886.804 897.752 mV 150% 233%
30s
900.880 911.828 922.776 mV 167% 267%
925.904 936.852 947.801 mV 183% 300%
950.929 961.877 972.825 mV 200% 333%
975.953 986.901 997.849 mV 217% 367%

43
RT3606BC
R2 RSET
VSET2 = VCC 
R1+R2 %130k RTON
DVID_Width
Low FSW High FSW
Ramp Ramp
1000.978 1011.926 1022.874 mV 100% 133%
1026.002 1036.950 1047.898 mV 117% 167%
1051.026 1061.975 1072.923 mV 133% 200%
1076.051 1086.999 1097.947 mV 150% 233%
36s
1101.075 1112.023 1122.972 mV 167% 267%
1126.100 1137.048 1147.996 mV 183% 300%
1151.124 1162.072 1173.021 mV 200% 333%
1176.149 1187.097 1198.045 mV 217% 367%
1201.173 1212.121 1223.069 mV 100% 133%
1226.197 1237.146 1248.094 mV 117% 167%
1251.222 1262.170 1273.118 mV 133% 200%
1276.246 1287.195 1298.143 mV 150% 233%
42s
1301.271 1312.219 1323.167 mV 167% 267%
1326.295 1337.243 1348.192 mV 183% 300%
1351.320 1362.268 1373.216 mV 200% 333%
1376.344 1387.292 1398.240 mV 217% 367%
1401.369 1412.317 1423.265 mV 100% 133%
1426.393 1437.341 1448.289 mV 117% 167%
1451.417 1462.366 1473.314 mV 133% 200%
1476.442 1487.390 1498.338 mV 150% 233%
48s
1501.466 1512.414 1523.363 mV 167% 267%
1526.491 1537.439 1548.387 mV 183% 300%
1551.515 1562.463 1573.412 mV 200% 333%
1576.540 1587.488 1598.436 mV 217% 367%

44
RT3606BC
Ramp Compensation QR Width
TM
The G-NAVP topology is one type of ripple based control
that has fast transient response and can lower BOM cost.
VCORE QR Threshold
However, ripple based control usually has poor noise
immunity. RT3606BC provides the ramp compensation to
increase noise immunity and reduce jitter at the switching
node. Figure 21 shows the ramp compensation.
PWM1
Noise Margin w/o ramp compensation
PWM2
IMON-VREF
PWM3
VCOMP
Load
Noise Margin
w/ ramp compensation Figure 22. Quick Response Mechanism
IMON-VREF
The output voltage signal behavior needs to be detected
so that QR mechanism can be trigged. The output voltage
signal is via a remote sense line to connect at VSEN pin
VCOMP
that is shown in Figure 23. The QR mechanism needs to
set QR width and QR threshold. Both definitions are shown
in Figure 22. A proper QR mechanism set can meet different
Figure 21. Ramp Compensation
applications. SET2 can set QR threshold and QR width
For the RT3606BC, the ramp compensation also needs by internal current source 80μA with multi-function pin
to be considered during mode transition from PS0/1 to setting mechanism.
PS2. For achieving smooth mode transition into PS2, a
QR_TH
proper ramp compensation design is necessary. Since
QR Pulse VSEN
+
-
-
the ramp compensation needs to be proportional to the Generation CMP

+
Circuit
on-time, then RAMP is set as
FS QR_width
133% 
400k
Figure 23. Simplified QR Trigger Schematic
Quick Response (QR) Mechanism
For example, QR threshold 20mV/10mV at PS0/PS1 and
When the transient load step-up becomes quite large, it
2.22 x TON QR width are set. According to the Table 8,
is difficult for loop response to meet the energy transfer.
the set voltage should be between 0.4505V and 0.4723V.
Hence, that output voltage generate undershoot to fail
Please note that a high accuracy resistor is needed for
specification. The RT3606BC has Quick Response (QR)
this setting accuracy, < 1% error tolerance is
mechanism being able to improve this issue. It adopts a
recommended. In the Table 8, there are some “NA” marks
nonlinear control mechanism which can disable
in QRWIDTH section. It means that users should not use
interleaving function and simultaneously turn on all UGATE
it to avoid the possibility of shift digital code due to
one pulse at instantaneous step-up transient load to
tolerance concern.
restrain the output voltage drooping, Figure 22 shows the
QR behavior.

45
RT3606BC
Table 8. SET2 Pin Setting for QR Threshold and QR Width
R1 R2
VSET2 = 80Α  QR Threshold
R1+R2 QR Width (%TON)
Min Typical Max Unit PS0 PS1
0.000 10.948 21.896 mV NA
25.024 35.973 46.921 mV Disable
50.049 60.997 71.945 mV 222%
75.073 86.022 96.970 mV 177.6%
15mV 10mV
100.098 111.046 121.994 mV 133.2%
125.122 136.070 147.019 mV 88%
150.147 161.095 172.043 mV 44%
175.171 186.119 197.067 mV NA
200.196 211.144 222.092 mV NA
225.220 236.168 247.116 mV Disable
250.244 261.193 272.141 mV 222%
275.269 286.217 297.165 mV 177.6%
15mV 15mV
300.293 311.241 322.190 mV 133.2%
325.318 336.266 347.214 mV 88%
350.342 361.290 372.239 mV 44%
375.367 386.315 397.263 mV NA
400.391 411.339 422.287 mV NA
425.415 436.364 447.312 mV Disable
450.440 461.388 472.336 mV 222%
475.464 486.413 497.361 mV 177.6%
20mV 10mV
500.489 511.437 522.385 mV 133.2%
525.513 536.461 547.410 mV 88%
550.538 561.486 572.434 mV 44%
575.562 586.510 597.458 mV NA
600.587 611.535 622.483 mV NA
625.611 636.559 647.507 mV Disable
650.635 661.584 672.532 mV 222%
675.660 686.608 697.556 mV 177.6%
20mV 15mV
700.684 711.632 722.581 mV 133.2%
725.709 736.657 747.605 mV 88%
750.733 761.681 772.630 mV 44%
775.758 786.706 797.654 mV NA

46
RT3606BC
R1 R2
VSET2 = 80Α  QR Threshold
800.782 811.730 822.678 mV NA
825.806 836.755 847.703 mV Disable
850.831 861.779 872.727 mV 222%
875.855 886.804 897.752 mV 177.6%
25mV 10mV
900.880 911.828 922.776 mV 133.2%
925.904 936.852 947.801 mV 88%
950.929 961.877 972.825 mV 44%
975.953 986.901 997.849 mV NA
1000.978 1011.926 1022.874 mV NA
1026.002 1036.950 1047.898 mV Disable
1051.026 1061.975 1072.923 mV 222%
1076.051 1086.999 1097.947 mV 177.6%
25mV 15mV
1101.075 1112.023 1122.972 mV 133.2%
1126.100 1137.048 1147.996 mV 88%
1151.124 1162.072 1173.021 mV 44%
1176.149 1187.097 1198.045 mV NA
1201.173 1212.121 1223.069 mV NA
1226.197 1237.146 1248.094 mV Disable
1251.222 1262.170 1273.118 mV 222%
1276.246 1287.195 1298.143 mV 177.6%
30mV 10mV
1301.271 1312.219 1323.167 mV 133.2%
1326.295 1337.243 1348.192 mV 88%
1351.320 1362.268 1373.216 mV 44%
1376.344 1387.292 1398.240 mV NA
1401.369 1412.317 1423.265 mV NA
1426.393 1437.341 1448.289 mV Disable
1451.417 1462.366 1473.314 mV 222%
1476.442 1487.390 1498.338 mV 177.6%
30mV 15mV
1501.466 1512.414 1523.363 mV 133.2%
1526.491 1537.439 1548.387 mV 88%
1551.515 1562.463 1573.412 mV 44%
1576.540 1587.488 1598.436 mV NA

47
RT3606BC
Current Monitor, IMON Output Over-Voltage Protection
RT3606BC includes a current monitor (IMON) function An OVP condition is detected when the VSEN pin is
which can be used to detect over-current protection and 350mV more than VID as VID > 1V. If VID < 1V, the OVP
the maximum processor current ICCMAX, and also sets is detected when the VSEN pin is 350mV more than 1V.
a part of current gain in the load-line setting. It produces When OVP is detected, the high-side gate voltage
an analog voltage proportional to output current between UGATEx is pulled low and the low-side gate voltage
the IMON and VREF pins. LGATEx is pulled high. OVP is latched with a 0.5μs delay
The calculation for IMON-VREF voltage is shown as below : to prevent false trigger. Besides, the OVP function will be
masked during DVID and soft-start period. After 46μs of
VIMON  VREF = DCR  REQ  (IL1 +IL2 +IL3 ) DVID or soft-start alert is asserted, the OVP function will
RCS
re-active.
Where IL1 + IL2 + IL3 are output current and the definitions
of DCR, RCS and REQ can refer to Figure 13. Negative Voltage Protection
Since the OVP latch continuously turns on all low side
Over-Current Protection
MOSFETs of the VR, the VR will suffer negative output
The RT3606BC provides Over-Current Protection (OCP) voltage. When the VSEN detects a voltage below −0.07V
which is set by the SET1 pin. The OCP threshold setting after triggering OVP, the VR triggers NVP to turn off all
can refer to ICCMAX current in Table 5. For example, if low-side MOSFETs of the VR while the high-side
ICCMAX is set as 120A, users can set voltage by using MOSFETs remains off. After triggering NVP, if the output
the external voltage divider on the SET1 pin as 0.754V voltage rises above 0V, the OVP latch restarts to turn on
typically. If 156A OCP (130% x ICCMAX) threshold and all low-side MOSFETs. Therefore, the output voltage may
DVID_TH (SR = 11.25mV/μs) = 39.67mV / DVID_TH (SR = bounce between 0V and −0.07V due to OVP latch and
33.75mV/μs) = 119mV will be set. According to Table 6, NVP triggering. The NVP function will be active only after
the set voltage should be between 0.4755V and 0.4974V. OVP is triggered.
When output current is higher than the OCP threshold,
OCP is latched with a 40μs delay to prevent false trigger.
Besides, the OCP function is masked when dynamic VID
transient occurs, and soft-start period. And the OCP
function will re-active after 46μs of DVID or soft-start alert
is asserted.

48
RT3606BC
Current Loop Design in Details
VCORE
IL1
L1 DCR1
VREF
REQ R1 C1
ISEN1P
IMON ISEN1N +
RNTC
- ISEN1N 680
IL2
0.6V - L2 DCR2
+
1/3
R2 C2
-
COMP + ISEN2N ISEN2P
+ +
- ISEN2N 680
IL3
L3 DCR3
R3 C3
ISEN3N ISEN3P
+
- ISEN3N 680
Figure 24. Current Loop Structure
Figure 24 shows the whole current loop structure. The current loop plays an important role in RT3606BC that can decide
ACLL performance, DCLL accuracy and ICCMAX accuracy. For ACLL performance, the correct compensator design is
assumed, if RC network time constant matches inductor time constant LX / DCRX, an expected load transient waveform
can be designed. If RXCX network time constant is larger than inductor time constant LX / DCRX, VCORE waveform has a
sluggish droop during load transient. If RXCX network is smaller than inductor time constant LX / DCRX, a worst VCORE
waveform will sag to create an undershooting to fail the specification. Figure 25 shows the variety RXCX constant
corresponding to the output waveforms.

49
RT3606BC
Where :
Lx
R x  Cx =
VCORE DCR x (1) The relationship between DCR and temperature is as
IOUT x RLL
follows :
DCR (T) = DCR (25C)  1+ 0.00393 (T - 25)
IOUT (2) REQ (T) is the equivalent resistor of the resistor network
VIMON with a NTC thermistor
REQ (T) = RIMON1 + RIMON2 / / RIMON3 + RNTC (T)
Expected load transient waveform
And the relationship between NTC and temperature is as

Lx
R x  Cx < follows :
VCORE DCR x
IOUT x RLL β( 1 - 1 )
RNTC (T) = RNTC (25C)  e T+273 298
β is in the NTC thermistor datasheet.

IOUT
VIMON
Step3 : Three equations and three unknowns, RIMON1,
RIMON2 and RIMON3 can be found out unique solution.
Undershoot created in VCORE
R  (RNTCTR +RIMON3 )
RIMON1 = K TR  IMON2
RIMON2 +RNTCTR +RIMON3
Lx
R x  Cx >
DCR x 2
VCORE [KR3 +KR3 (RNTCTL +RNTCTR )
IOUT x RLL RIMON2 =
+RNTCTLRNTCTR ]α TL
RIMON3 = RIMON2 +KR3

IOUT
VIMON
Where :
Sluggish droop
K TH  K TR
Figure 25. All Kinds of RxCx Constants α TH =
RNTCTH  RNTCTR
For DCLL performance and ICCMAX accuracy, since the K TL  K TR

α TL =
copper wire of inductor has a positive temperature RNTCTL  RNTCTR
coefficient, when temperature goes high in the heavy load (α TH / α TL )RNTCTH  RNTCTL
condition, DCR value goes large simultaneously. A resistor KR3 =
1 (α TH / α TL )
network with NTC thermistor compensation connecting
K TL = 1.6
between IMON and REF pins is necessary, to compensate GCS (TL)  ICC-MAX
the positive temperature coefficient of inductor DCR. The
design flow is as follows : K TR = 1.6
GCS (TR)  ICC-MAX
Step1 : Given the three system temperature TL, TR and
TH, at which are compensated. K TH = 1.6
GCS (TH)  ICC-MAX
Step2 : Three equations can be listed as
4
DCR (TL )
680 
 iLi  REQ (TL ) = 1.6
i=1
4
DCR (TR )
680
  iLi  REQ (TR ) = 1.6
i=1
4
DCR (TH )
680
  iLi  REQ (TH ) = 1.6
i=1

50
RT3606BC
Design Step :  Current sensor adopts lossless RC filter to sense current
RT3606BC excel based design tool is available. Users signal in DCR. For getting an expect load transient
can contact your Richtek representative to get the waveform, RxCx time constant needs to match Lx /
spreadsheet. Three main design procedures for RT3606BC DCRx per phase. Cx = 0.47μF is set, then
design, first step is initial settings, second step is loop LX
RX   960
design and the last step is protection settings. The 0.47F  DCR X
following design example is to explain the RT3606BC  IMON resistor network design : TL = 25°C, TR = 50°C
design procedure : and T H = 100°C are decided, NTC thermistor =
VCORE Specification 100kΩ@25°C, β = 4485 and ICCMAX = 90A.
Input Voltage 12V According to the sub-section “Current Loop Design in
Details”, RIMON1 = 10.66kΩ, RIMON2 = 16.16kΩ and
No. of Phases 3
RIMON3 = 1 2.63kΩ can be decided. The REQ (25°C) =
ICCMAX 90A 24.91kΩ.
ICC-DY 69A
 Load-line design : 2.1mΩ droop is requirement, because
ICC-TDC 68A REQ (25°C) has decided, the voltage loop Av gain is also
Load Line 2.1m can be decided by following equation
Fast Slew Rate 10mV/s 1  DCR  R
EQ
AI 3 RCS
Max Switching
400kHz
RLL 
AV

R2
 m 
Frequency R1
Where DCR (25°C) = 0.49mΩ, R CS = 680Ω and
In IMVP8 VRTB Guideline, the output filter requirements
REQ (25°C) = 24.91kΩ. Hence the AV = R2 / R1 = 2.85
of VRTB specification for desktop platform are :
can be obtained. R1 = 10kΩ usually decided, so R2 =
Output Inductor : 220nH/0.49mΩ 28.5kΩ.
Output Bulk Capacitor : 560μF/2.5V/5mΩ (max) 4 to 5pcs  Typical compensator design can use the following
Output Ceramic Capacitor : 22μF/0805 (19pcs max in equations to design the C1 and C2 values
cavity) 1
C1   470pF
R1   fSW
(1) Initial Settings :
COUT  ESR
 IBIAS needs to connect a 100kΩ resistor to ground. C2   98pF
R2
A voltage divider for setting DVD can choose RDVD_U = For Intel platform, in order to induce the band width to
510kΩ and RDVD_L = 125kΩ to set VDVD > 2V, RT3606BC enhance transient performance to meet Intel’s criterion,
enabled. the compensator of zero can be designed close to 1/10
(2) Loop Design : of switching frequency.
 On time setting : Using the specification, TON is  SET1 resistor network design : First the ICCMAX is
design as 90A. Next, OCP threshold is designed as
RTON  4.73p  1.2
TON  ( VDAC  1.2)  246n 1.5 x ICCMAX. Last, DVID compensation parameters
VIN  VDAC
need to be decided. The DVID_TH can be calculated as
The on time setting resistor RTON = 483kΩ
following equation
VDVID_TH = LL  COUT  dVID
dt

51
RT3606BC
Where LL is load-line, COUT is total output capacitance AXG VR
and dVID/dt is DVID fast slew rate. Thus VDVID_TH =
Phase Disable (Before POR)
50.33mV is needed in this case. By using above
information, the two equations can be listed by using The number of active phases is determined by the internal
multi-function pin setting mechanism circuitry that monitors the ISENAxN voltages during
R2  3.2 startup. Normally, the VR operates as a 2-phase PWM
0.566 
R1  R2 controller. Pulling ISENA2N to VCC programs a 1-phase
0.736  80 Α  R1 R2 operation. Before POR, VR detects whether the voltages
R1  R2
of ISENA2N is higher than “VCC-1V” respectively to
R1 = 52kΩ, R2 = 11.2kΩ. decide how many phases should be active. Phase
selection is only active during POR. When POR = high,
 SET2 resistor network design :
400k the number of active phases is determined and latched.
RAMP = 133% x = 133%, 133% is set. And The unused ISENAxP pins are recommended to be
400k
DVID_Width is chosen as 24μsec typical. Last, the QR connected to VCC and unused PWM pins can be left
mechanism parameters need to be designed first. Initial floating.
QR_TH is designed as 25mV and QR_Width is designed
as 0.44 x TON. By using the information, the two No Load Offset (Platform)
equations can be listed by using multi-function pin The AXG VR features no load offset function which provides
setting mechanism the possibility of wide range positive offset of output voltage.
R2  3.2 Users can disable offset function by simply connecting
0.661 
R1  R2 OFSA/PSYS pin to GND. Figure 26 shows a voltage divider
1.162  80 Α  R1 R2 used to set no load offset voltage. No load offset voltage
R1  R2
setting is :
R 1= 70.3kΩ, R2 = 18.2kΩ.
VOFS_AXG  0.4  ( VOFSA  1.7)
(1) Protection Settings :
The range of VOFS_AXG is between −500mV and 590mV
 OVP protections : When VSEN pin voltage is 350mV and the resolution is 10mV.
more than VID, the OVP will be latched.
For example, a 100mV no load offset requirement, VOFSA
 TSEN and VR_HOT design : Using the following equation needs to be set as 1.95V.
to calculate related resistances for VR_HOT setting.
VTSEN  80 A  R1// R2  RNTC (100C)  
SVID Offset
 Choosing R1 is open and an NTC thermistor RNTC (25°C) Register
= 100kΩ which β = 4485. When temperature is 100°C, VCC SVID VID + VID_REF
++ DAC
the RNTC (100!) = 4.85kΩ. Then R2 = 8.8kΩ can be Register
calculated. R1
OFSA/PSYS PIN Offset
ADC Register
R2
Figure 26. No Load Offset Circuit

52
RT3606BC
Switching Frequency Setting RAXCAX filter network time constant, a voltage ILAx x DCR
As mention in switching frequency setting section of will drop on CAX to generate inductor current signal.
CORE VR, connect a resistor RTONA between input terminal According to the Figure 27, the ISENAxN is as follows :
and TONSETA pin to set the on-time width. ILAX  DCR
ISENAxN 
RCSAx
RTONA  4.793p  1.2
TONA  (VDAC  1.2) Where LAX / DCR = RAXCAX is held. The method can get
VIN  VDAC
R  4.793p  VDAC high efficiency performance, but DCR value will be drifted
TONA  TONA (VDAC  1.2)
VIN  VDAC by temperature, a NTC resistor should add in the resistor
network in the IMONA pin to achieve DCR thermal
For better efficiency of the given load range, the maximum
compensation.
switching frequency is suggested to be :
FSWA(MAX)  In RT3606BC design, the resistance of RCSAx is restricted
IccTDC  RON_LS,max 
VID1 
N
  DCR 
nLS
 N  RLL  to 680Ω; moreover, the error of RCSAx is recommended to
 

 VIN(MAX) 
IccTDC  RON_LS,max RON_HS,max  
      TONA  TD  TONA,VAR  
IccTDC  RON_LS,max


  TD
be 1% or smaller.
 N  nLS nHS   N  nLS 
ILAx VAXG
where FSW(MAX) is the maximum switching frequency, VID1 LAX DCR

is the typical VID of application, VIN (MAX) is the maximum
RAX CAX
application input voltage, IccTDC is the thermal design
ISENAxN
ISENAxP
current of application, N is the phase number. The +
RON_HS,max is the maximum equivalent high-side RDS(ON), - ISENAxN RCSAx
and nHS is the number of high-side MOSFETs; RON_LS,max

is the maximum equivalent low-side RDS(ON), and nLS is
Figure 27. Lossless Current Sense Method
the number of low-side MOSFETs. TD is the summation
of the high-side MOSFET delay time and the rising time, Total Current Sense
TON,VAR is the TON variation value. DCR is the inductor
As presented in total current sense section of AXG VR,
DCR, and RLL is the loadline setting. In addition, Richtek
Figure 28 shows the total current sense method which
provides a Microsoft Excel-based spreadsheet to help
connects the resistor network between IMONA and VREF
design the RTON for RT3606BC.
pins to set a part of current loop gain for load-line (droop)
When load increases, on-time keeps constant. The off- setting and set accurate over current protection.
time width will be reduced so that loading can load more
VIMONA  VREF  DCR  REQA  (ILA1  ILA2 )
power from input terminal to regulate output voltage. Hence RCS
the loading current usually increases in case the switching REQA includes a NTC resistor to compensate DCR thermal
frequency also increases. Higher switching frequency drifting for high accuracy load-line (droop).
operation can reduce power components' size and PCB
space, trading off the whole efficiency since switching
related switching related loss increases, vice versa.
Per Phase Current Sense

In the RT3606BC, the current signal is used for load-line
setting and Over-Current Protection (OCP). The inductor
current sense method adopts the lossless current sensing
for allowing high efficiency as illustrated in the Figure 27.
When inductance and DCR time constant is equal to

53
RT3606BC
VAXG
ILA1
VAXG
L DCR RA2
Voltage Loop TON Generator
R C -
RA1 +
+
ISENA1P
IMONA ISENA1N + IL1.2
-
- ISENA1N RCSA
DCR LA VID
1/3
+
-
ILA2 R
L DCR C RNTC
RNTC ISENA[1:2]P ISENA1N + ISENA2N
+
REQA R C
- IMONA VREF
RCS ISENA[1:2]N
ISENA2N ISENA2P
+ REQA
- ISENA2N RCSA
Figure 30. Voltage Loop and Current Loop
VREF Compensator Design

The compensator of RT3606BC doesn't need a complex
type II or type III compensator to optimize control loop
Figure 28. Total Current Sense Method performance. It can adopt a simple type I compensator
(one pole, one zero) in G-NAVPTM topology to achieve
constant output impedance design for Intel IMVP8 ACLL
Load-Line (Droop) Setting
specification. The one pole one zero compensator is
The G-NAVPTM topology can set load-line (droop) via the shown as Figure 31, the transfer function of compensator
current loop and the voltage loop, the load-line is a slope should be design as following transfer function to achieve
between load current ICCA and output voltage VAXG as constant output impedance, i.e. Zo(s) = load-line slope in
shown Figure 29. Figure 30 shows the voltage control the entire frequency range
and current loop. By using the both loops, the load-line s
1
(droop) can be set easily. The load-line set equation is : GCON (S) 
AI   fSWA
RLLA 1  s
1  DCR  R
EQA ESRA
AI 3 RCS
RLLA 
AV

RA2
 m 
Where AI is current loop gain, RLLA is load line for AXG
RA1
VR, fSWA is switching frequency for AXG VR and ωESRA is a
VAXG
pole that should be located at 1 / (COUTA x ESR). Then the
CA1 and CA2 should be designed as follows :
CA1  1
Load line slope = -RLLA RA1   fSWA
RLLA x ICCA
COUTA  ESR
CA2 
RA2
CA2
ICCA
CA1 RA2
Figure 29. Load-Line (Droop) -

RA1 +
VID
Figure 31. Type I Compensator

54
RT3606BC
Differential Remote Sense Setting Maximum Processor Current Setting, ICCMAXA
The VR provides differential remote-sense inputs to The maximum processor current ICCMAXA can be set by
eliminate the effects of voltage drops along the PC board the SETA1 pin. ICCMAXA register is set by an external
traces, CPU internal power routes and socket contacts. voltage divider with the multi-function mechanism. Table
The CPU contains on-die sense pins, VCCAXG_SENSE and 9 shows the ICCMAXA setting on the SETA1 pin. For
VSSAXG_SENSE. Connect RGNDA to VSSAXG_SENSE and example, ICCMAXA = 40A, the VICCMAXA needs to set
connect FBA to VCCAXG_SENSE with a resistor to build the as 0.253 typical. Additionally, VIMONA − VREF needs to be
negative input path of the error amplifier as shown in Figure set as 1.6V at ICCMAXA when the maximum phase >1.
32. The VDAC and the precision voltage reference are As in 1-phase application, the VIMONA − VREF needs to be
referred to RGNDA for accurate remote sensing. set as 0.4V at ICCMAXA. The ICCMAXA alert signal will
be pulled to low level.
if VIMONA − VREF = 1.6V (for maximum phase >1) or
VIMONA − VREF = 0.4V (for 1-phase application)
CPU VCCAXG_SENSE
VOUTA
FBA R1
-
EA
+ COUTA
+
VID
-
RGNDA R2
CPU VSSAXG_SENSE
Figure 32. Remote Sensing Circuit

55
RT3606BC
Table 9. SETA1 Pin Setting for ICCMAXA
VSETA1  R2  3.2V
R1 R2 ICCMAXA Unit
0.000 3.128 6.256 mV 0 A
12.512 15.640 18.768 mV 2 A
25.024 28.152 31.281 mV 4 A
37.537 40.665 43.793 mV 6 A
50.049 53.177 56.305 mV 8 A
62.561 65.689 68.817 mV 10 A
75.073 78.201 81.329 mV 12 A
87.586 90.714 93.842 mV 14 A
100.098 103.226 106.354 mV 16 A
112.610 115.738 118.866 mV 18 A
125.122 128.250 131.378 mV 20 A
137.634 140.762 143.891 mV 22 A
150.147 153.275 156.403 mV 24 A
162.659 165.787 168.915 mV 26 A
175.171 178.299 181.427 mV 28 A
187.683 190.811 193.939 mV 30 A
200.196 203.324 206.452 mV 32 A
212.708 215.836 218.964 mV 34 A
225.220 228.348 231.476 mV 36 A
237.732 240.860 243.988 mV 38 A
250.244 253.372 256.500 mV 40 A
262.757 265.885 269.013 mV 42 A
275.269 278.397 281.525 mV 44 A
287.781 290.909 294.037 mV 46 A
300.293 303.421 306.549 mV 48 A
312.805 315.934 319.062 mV 50 A
325.318 328.446 331.574 mV 52 A
337.830 340.958 344.086 mV 54 A
350.342 353.470 356.598 mV 56 A
362.854 365.982 369.110 mV 58 A
375.367 378.495 381.623 mV 60 A
387.879 391.007 394.135 mV 62 A
400.391 403.519 406.647 mV 64 A
412.903 416.031 419.159 mV 66 A

56
RT3606BC
VSETA1  R2  3.2V
425.415 428.543 431.672 mV 68 A
437.928 441.056 444.184 mV 70 A
450.440 453.568 456.696 mV 72 A
462.952 466.080 469.208 mV 74 A
475.464 478.592 481.720 mV 76 A
487.977 491.105 494.233 mV 78 A
500.489 503.617 506.745 mV 80 A
513.001 516.129 519.257 mV 82 A
525.513 528.641 531.769 mV 84 A
538.025 541.153 544.282 mV 86 A
550.538 553.666 556.794 mV 88 A
563.050 566.178 569.306 mV 90 A
575.562 578.690 581.818 mV 92 A
588.074 591.202 594.330 mV 94 A
600.587 603.715 606.843 mV 96 A
613.099 616.227 619.355 mV 98 A
625.611 628.739 631.867 mV 100 A
638.123 641.251 644.379 mV 102 A
650.635 653.763 656.891 mV 104 A
663.148 666.276 669.404 mV 106 A
675.660 678.788 681.916 mV 108 A
688.172 691.300 694.428 mV 110 A
700.684 703.812 706.940 mV 112 A
713.196 716.325 719.453 mV 114 A
725.709 728.837 731.965 mV 116 A
738.221 741.349 744.477 mV 118 A
750.733 753.861 756.989 mV 120 A
763.245 766.373 769.501 mV 122 A
775.758 778.886 782.014 mV 124 A
788.270 791.398 794.526 mV 126 A
800.782 803.910 807.038 mV 128 A
813.294 816.422 819.550 mV 130 A
825.806 828.935 832.063 mV 132 A
838.319 841.447 844.575 mV 134 A
850.831 853.959 857.087 mV 136 A

57
RT3606BC
VSETA1  R2  3.2V
863.343 866.471 869.599 mV 138 A
875.855 878.983 882.111 mV 140 A
888.368 891.496 894.624 mV 142 A
900.880 904.008 907.136 mV 144 A
913.392 916.520 919.648 mV 146 A
925.904 929.032 932.160 mV 148 A
938.416 941.544 944.673 mV 150 A
950.929 954.057 957.185 mV 152 A
963.441 966.569 969.697 mV 154 A
975.953 979.081 982.209 mV 156 A
988.465 991.593 994.721 mV 158 A
1000.978 1004.106 1007.234 mV 160 A
1013.490 1016.618 1019.746 mV 162 A
1026.002 1029.130 1032.258 mV 164 A
1038.514 1041.642 1044.770 mV 166 A
1051.026 1054.154 1057.283 mV 168 A
1063.539 1066.667 1069.795 mV 170 A
1076.051 1079.179 1082.307 mV 172 A
1088.563 1091.691 1094.819 mV 174 A
1101.075 1104.203 1107.331 mV 176 A
1113.587 1116.716 1119.844 mV 178 A
1126.100 1129.228 1132.356 mV 180 A
1138.612 1141.740 1144.868 mV 182 A
1151.124 1154.252 1157.380 mV 184 A
1163.636 1166.764 1169.892 mV 186 A
1176.149 1179.277 1182.405 mV 188 A
1188.661 1191.789 1194.917 mV 190 A
1201.173 1204.301 1207.429 mV 192 A
1213.685 1216.813 1219.941 mV 194 A
1226.197 1229.326 1232.454 mV 196 A
1238.710 1241.838 1244.966 mV 198 A
1251.222 1254.350 1257.478 mV 200 A
1263.734 1266.862 1269.990 mV 202 A
1276.246 1279.374 1282.502 mV 204 A
1288.759 1291.887 1295.015 mV 206 A

58
RT3606BC
VSETA1  R2  3.2V
1301.271 1304.399 1307.527 mV 208 A
1313.783 1316.911 1320.039 mV 210 A
1326.295 1329.423 1332.551 mV 212 A
1338.807 1341.935 1345.064 mV 214 A
1351.320 1354.448 1357.576 mV 216 A
1363.832 1366.960 1370.088 mV 218 A
1376.344 1379.472 1382.600 mV 220 A
1388.856 1391.984 1395.112 mV 222 A
1401.369 1404.497 1407.625 mV 224 A
1413.881 1417.009 1420.137 mV 226 A
1426.393 1429.521 1432.649 mV 228 A
1438.905 1442.033 1445.161 mV 230 A
1451.417 1454.545 1457.674 mV 232 A
1463.930 1467.058 1470.186 mV 234 A
1476.442 1479.570 1482.698 mV 236 A
1488.954 1492.082 1495.210 mV 238 A
1501.466 1504.594 1507.722 mV 240 A
1513.978 1517.107 1520.235 mV 242 A
1526.491 1529.619 1532.747 mV 244 A
1539.003 1542.131 1545.259 mV 246 A
1551.515 1554.643 1557.771 mV 248 A
1564.027 1567.155 1570.283 mV 250 A
1576.540 1579.668 1582.796 mV 252 A
1589.052 1592.180 1595.308 mV 254 A

59
RT3606BC
Dynamic VID (DVID) Compensation for AXG VR divider. For example, 39.67mV DVID_Threshold (SR =
As mention in DVID compensation section of CORE VR, 11.25mV/μs) / 119mV DVID_Threshold (SR = 33.75mV/μs)
the RT3606BC also provide a DVID compensation function and 36μs DVID_Width are designed (OCPA sets as 110%
for AXG VR. A virtual charge current signal can be ICCMAXA, RSETA sets as 133% low frequency ramp /
established by SETA1 and SETA2 pins to cancel the real 200% high frequency ramp). According to the Table 10
induced charge current signal. and Table 11, the DVID_Threshold set voltage should be
between 0.4254V to 0.4473V and the DVID_Width set
Table 10 show the DVID_Threshold in SETA1 pin with
voltage should be between 1.051V to 1.073V. Please note
internal 80μA current source and Table 11 describes
that a high accuracy resistor is needed for this setting, <
DVID_Width settings on SETA2 pin with external voltage
1% error tolerance is recommended.
Table 10. SETA1 Pin Setting for DVID_Threshold
R1 R2
VSETA1 = 80Α  DVID_Threshold
R1+R2
OCP = %ICCMAX
DVID SR DVID SR
= 11.25mV/s = 33.75mV/s
0.000 10.948 21.896 mV NA
25.024 35.973 46.921 mV 110%
50.049 60.997 71.945 mV 120%
75.073 86.022 96.970 mV 130%
18.33mV 55mV
100.098 111.046 121.994 mV 140%
125.122 136.070 147.019 mV 150%
150.147 161.095 172.043 mV 160%
175.171 186.119 197.067 mV NA
200.196 211.144 222.092 mV NA
225.220 236.168 247.116 mV 110%
250.244 261.193 272.141 mV 120%
275.269 286.217 297.165 mV 130%
29mV 87mV
300.293 311.241 322.190 mV 140%
325.318 336.266 347.214 mV 150%
350.342 361.290 372.239 mV 160%
375.367 386.315 397.263 mV NA
400.391 411.339 422.287 mV NA
425.415 436.364 447.312 mV 110%
450.440 461.388 472.336 mV 120%
475.464 486.413 497.361 mV 130%
39.67mV 119mV
500.489 511.437 522.385 mV 140%
525.513 536.461 547.410 mV 150%
550.538 561.486 572.434 mV 160%
575.562 586.510 597.458 mV NA

60
RT3606BC
R1 R2
VSETA1 = 80Α  DVID_Threshold
R1+R2
OCP = %ICCMAX
DVID SR DVID SR
= 11.25mV/s = 33.75mV/s
600.587 611.535 622.483 mV NA
625.611 636.559 647.507 mV 110%
650.635 661.584 672.532 mV 120%
675.660 686.608 697.556 mV 130%
50.33mV 151mV
700.684 711.632 722.581 mV 140%
725.709 736.657 747.605 mV 150%
750.733 761.681 772.630 mV 160%
775.758 786.706 797.654 mV NA
800.782 811.730 822.678 mV NA
825.806 836.755 847.703 mV 110%
850.831 861.779 872.727 mV 120%
875.855 886.804 897.752 mV 130%
61mV 183mV
900.880 911.828 922.776 mV 140%
925.904 936.852 947.801 mV 150%
950.929 961.877 972.825 mV 160%
975.953 986.901 997.849 mV NA
1000.978 1011.926 1022.874 mV NA
1026.002 1036.950 1047.898 mV 110%
1051.026 1061.975 1072.923 mV 120%
1076.051 1086.999 1097.947 mV 130%
71.67mV 215mV
1101.075 1112.023 1122.972 mV 140%
1126.100 1137.048 1147.996 mV 150%
1151.124 1162.072 1173.021 mV 160%
1176.149 1187.097 1198.045 mV NA
1201.173 1212.121 1223.069 mV NA
1226.197 1237.146 1248.094 mV 110%
1251.222 1262.170 1273.118 mV 120%
1276.246 1287.195 1298.143 mV 130%
82.33mV 247mV
1301.271 1312.219 1323.167 mV 140%
1326.295 1337.243 1348.192 mV 150%
1351.320 1362.268 1373.216 mV 160%
1376.344 1387.292 1398.240 mV NA
1401.369 1412.317 1423.265 mV NA
1426.393 1437.341 1448.289 mV 110%
1451.417 1462.366 1473.314 mV 120%
1476.442 1487.390 1498.338 mV 130%
93mV 279mV
1501.466 1512.414 1523.363 mV 140%
1526.491 1537.439 1548.387 mV 150%
1551.515 1562.463 1573.412 mV 160%
1576.540 1587.488 1598.436 mV NA

61
RT3606BC
Table 11. SETA2 Pin Setting for DVID_Width
R2 RSET
VSETA2 = VCC 
R1+R2 %410k RTON
DVID_Width
Low FSW High FSW
Ramp Ramp
0.000 10.948 21.896 mV 100% 133%
25.024 35.973 46.921 mV 117% 167%
50.049 60.997 71.945 mV 133% 200%
75.073 86.022 96.970 mV 150% 233%
6s
100.098 111.046 121.994 mV 167% 267%
125.122 136.070 147.019 mV 183% 300%
150.147 161.095 172.043 mV 200% 333%
175.171 186.119 197.067 mV 217% 367%
200.196 211.144 222.092 mV 100% 133%
225.220 236.168 247.116 mV 117% 167%
250.244 261.193 272.141 mV 133% 200%
275.269 286.217 297.165 mV 150% 233%
12s
300.293 311.241 322.190 mV 167% 267%
325.318 336.266 347.214 mV 183% 300%
350.342 361.290 372.239 mV 200% 333%
375.367 386.315 397.263 mV 217% 367%
400.391 411.339 422.287 mV 100% 133%
425.415 436.364 447.312 mV 117% 167%
450.440 461.388 472.336 mV 133% 200%
475.464 486.413 497.361 mV 150% 233%
18s
500.489 511.437 522.385 mV 167% 267%
525.513 536.461 547.410 mV 183% 300%
550.538 561.486 572.434 mV 200% 333%
575.562 586.510 597.458 mV 217% 367%
600.587 611.535 622.483 mV 100% 133%
625.611 636.559 647.507 mV 117% 167%
650.635 661.584 672.532 mV 133% 200%
675.660 686.608 697.556 mV 150% 233%
24s
700.684 711.632 722.581 mV 167% 267%
725.709 736.657 747.605 mV 183% 300%
750.733 761.681 772.630 mV 200% 333%
775.758 786.706 797.654 mV 217% 367%

62
RT3606BC
R2 RSET
VSETA2 = VCC 
R1+R2 %410k RTON
DVID_Width
Low FSW High FSW
Ramp Ramp
800.782 811.730 822.678 mV 100% 133%
825.806 836.755 847.703 mV 117% 167%
850.831 861.779 872.727 mV 133% 200%
875.855 886.804 897.752 mV 150% 233%
30s
900.880 911.828 922.776 mV 167% 267%
925.904 936.852 947.801 mV 183% 300%
950.929 961.877 972.825 mV 200% 333%
975.953 986.901 997.849 mV 217% 367%
1000.978 1011.926 1022.874 mV 100% 133%
1026.002 1036.950 1047.898 mV 117% 167%
1051.026 1061.975 1072.923 mV 133% 200%
1076.051 1086.999 1097.947 mV 150% 233%
36s
1101.075 1112.023 1122.972 mV 167% 267%
1126.100 1137.048 1147.996 mV 183% 300%
1151.124 1162.072 1173.021 mV 200% 333%
1176.149 1187.097 1198.045 mV 217% 367%
1201.173 1212.121 1223.069 mV 100% 133%
1226.197 1237.146 1248.094 mV 117% 167%
1251.222 1262.170 1273.118 mV 133% 200%
1276.246 1287.195 1298.143 mV 150% 233%
42s
1301.271 1312.219 1323.167 mV 167% 267%
1326.295 1337.243 1348.192 mV 183% 300%
1351.320 1362.268 1373.216 mV 200% 333%
1376.344 1387.292 1398.240 mV 217% 367%
1401.369 1412.317 1423.265 mV 100% 133%
1426.393 1437.341 1448.289 mV 117% 167%
1451.417 1462.366 1473.314 mV 133% 200%
1476.442 1487.390 1498.338 mV 150% 233%
48s
1501.466 1512.414 1523.363 mV 167% 267%
1526.491 1537.439 1548.387 mV 183% 300%
1551.515 1562.463 1573.412 mV 200% 333%
1576.540 1587.488 1598.436 mV 217% 367%

63
RT3606BC
Ramp Compensation Quick Response (QR) Mechanism
G-NAVPTM topology is one type of ripple based control As presented in QR mechanism section of CORE VR,
that has fast transient response and can lower BOM cost. RT3606BC also supports QR function in AXG VR. The
However, ripple based control usually has poor noise output voltage signal behavior needs to be detected so
immunity. The RT3606BC provides the ramp compensation that QR mechanism can be trigged. The output voltage
in AXG VR to increase noise immunity and reduce jitter at signal is via a remote sense line to connect at VSENA
the switching node. Figure 33 shows the ramp pin that is shown in Figure 34. The QR mechanism needs
compensation. to set QR width and QR threshold. Both definitions are
shown in Figure 22. A proper QR mechanism set can meet
Noise Margin w/o ramp compensation
different applications. SETA2 can set QR threshold and
IMONA-VREF
QR width by internal current source 80μA with multi-
function pin setting mechanism.
VCOMPA
QR_TH
QR Pulse VSENA
+
-
-
Generation CMP
+
Circuit
w/ ramp compensation
Noise Margin
QR_width
IMONA-VREF
Figure 34. Simplified QR Trigger Schematic
VCOMPA
For example, QR threshold 20mV/10mV at PS0/PS1 and
2.22 x TON QR width are set. According to the Table 12,
Figure 33. Ramp Compensation the set voltage should be between 0.4504V and 0.4723V.
Please note that a high accuracy resistor is needed for
For the RT3606BC, the ramp compensation also needs this setting accuracy, < 1% error tolerance is
to be considered during mode transition from PS0/1 to recommended. In the Table 12, there are some
PS2. For achieving smooth mode transition into PS2, a “NA”marks in QRWIDTH section. It means that user
proper ramp compensation design is necessary. Since should not use it to avoid the possibility of shift digital
the ramp compensation needs to be proportional to the code due to tolerance concern.
on-time, then RAMP is set as
F
133%  S
400k

64
RT3606BC
Table 12. SETA2 Pin Setting for QR Threshold and QR Width
R1 R2
VSETA2 = 80Α  QR Threshold
0.000 10.948 21.896 mV NA
25.024 35.973 46.921 mV Disable
50.049 60.997 71.945 mV 222%
75.073 86.022 96.970 mV 177.6%
15mV 10mV
100.098 111.046 121.994 mV 133.2%
125.122 136.070 147.019 mV 88%
150.147 161.095 172.043 mV 44%
175.171 186.119 197.067 mV NA
200.196 211.144 222.092 mV NA
225.220 236.168 247.116 mV Disable
250.244 261.193 272.141 mV 222%
275.269 286.217 297.165 mV 177.6%
15mV 15mV
300.293 311.241 322.190 mV 133.2%
325.318 336.266 347.214 mV 88%
350.342 361.290 372.239 mV 44%
375.367 386.315 397.263 mV NA
400.391 411.339 422.287 mV NA
425.415 436.364 447.312 mV Disable
450.440 461.388 472.336 mV 222%
475.464 486.413 497.361 mV 177.6%
20mV 10mV
500.489 511.437 522.385 mV 133.2%
525.513 536.461 547.410 mV 88%
550.538 561.486 572.434 mV 44%
575.562 586.510 597.458 mV NA
600.587 611.535 622.483 mV NA
625.611 636.559 647.507 mV Disable
650.635 661.584 672.532 mV 222%
675.660 686.608 697.556 mV 177.6%
20mV 15mV
700.684 711.632 722.581 mV 133.2%
725.709 736.657 747.605 mV 88%
750.733 761.681 772.630 mV 44%
775.758 786.706 797.654 mV NA

65
RT3606BC
R1 R2
VSETA2 = 80Α  QR Threshold
800.782 811.730 822.678 mV NA
825.806 836.755 847.703 mV Disable
850.831 861.779 872.727 mV 222%
875.855 886.804 897.752 mV 177.6%
25mV 10mV
900.880 911.828 922.776 mV 133.2%
925.904 936.852 947.801 mV 88%
950.929 961.877 972.825 mV 44%
975.953 986.901 997.849 mV NA
1000.978 1011.926 1022.874 mV NA
1026.002 1036.950 1047.898 mV Disable
1051.026 1061.975 1072.923 mV 222%
1076.051 1086.999 1097.947 mV 177.6%
25mV 15mV
1101.075 1112.023 1122.972 mV 133.2%
1126.100 1137.048 1147.996 mV 88%
1151.124 1162.072 1173.021 mV 44%
1176.149 1187.097 1198.045 mV NA
1201.173 1212.121 1223.069 mV NA
1226.197 1237.146 1248.094 mV Disable
1251.222 1262.170 1273.118 mV 222%
1276.246 1287.195 1298.143 mV 177.6%
30mV 10mV
1301.271 1312.219 1323.167 mV 133.2%
1326.295 1337.243 1348.192 mV 88%
1351.320 1362.268 1373.216 mV 44%
1376.344 1387.292 1398.240 mV NA
1401.369 1412.317 1423.265 mV NA
1426.393 1437.341 1448.289 mV Disable
1451.417 1462.366 1473.314 mV 222%
1476.442 1487.390 1498.338 mV 177.6%
30mV 15mV
1501.466 1512.414 1523.363 mV 133.2%
1526.491 1537.439 1548.387 mV 88%
1551.515 1562.463 1573.412 mV 44%
1576.540 1587.488 1598.436 mV NA

66
RT3606BC
Current Monitor, IMONA Output Over-Voltage Protection
RT3606BC includes a current monitor (IMONA) function An OVP condition is detected when the VSENA pin is
which can be used to detect over current protection and 150mV more than VID. as VID > 1V. If VID < 1V, the OVP
the maximum processor current ICCMAXA, and also sets is detected when the VSEN pin is 350mV more than 1V.
a part of current gain in the load-line setting. It produces When OVP is detected, the high-side gate voltage
an analog voltage proportional to output current between UGATEAx is pulled low and the low-side gate voltage
the IMONA and VREF pins. LGATEAx is pulled high, OVP is latched with a 0.5μs
delay to prevent false trigger. Besides, the OVP function
The calculation for IMONA-VREF voltage is shown as
will be masked during DVID and soft-start period. After
below :
46μs of DVID or soft-start alert is asserted, the OVP
VIMONA  VREF  DCR  REQA  (ILA1  ILA2 ) function will re-active.
RCSA
Where ILA1 + ILA2 are output current and the definitions of Negative Voltage Protection
DCR, RCSA and REQA can refer to Figure 28. Since the OVP latch continuously turns on all low-side
MOSFETs of the VR, the VR will suffer negative output
Over Current Protection
voltage. When the VSENA detects a voltage below −0.07V
RT3606BC provides the Over Current Protection (OCP)
after triggering OVP, the VR triggers NVP to turn off all
which is set by the SETA1 pin in AXG VR. The OCP
low-side MOSFETs of the VR while the high-side
threshold setting can refer to ICCMAXA current in the Table
MOSFETs remain off. After triggering NVP, if the output
9. For example, if ICCMAXA is set as 120A, user can set
voltage rises above 0V, the OVP latch restarts to turn on
voltage by using the external voltage divider on SETA1
all low-side MOSFETs. Therefore, the output voltage may
pin as 0.759V typically. If 156A OCP (130% x ICCMAX)
bounce between 0V and −0.07V due to OVP latch and
threshold and DVID_TH (SR = 11.25mV/μs) = 39.67mV /
NVP triggering. The NVP function will be active only after
DVID_TH (SR = 33.75mV/μs) = 119mV will be set.
OVP is triggered.
According to Table 10, the set voltage should be between
0.4755V and 0.4974V. When output current is higher than
the OCP threshold, OCP is latched with a 40μs delay to
prevent false trigger. Besides, the OCP function is masked
when dynamic VID transient occurs, and soft-start period.
And the OCP function will re-active after 46μs of DVID or
soft-start alert is asserted.

67
RT3606BC
Current Loop Design in Details
VAXG
ILA1
LA1 DCR1
VREF
REQA R1 C1
ISENA1P
IMONA ISENA1N +
RNTC
- ISENA1N 680
ILA2
0.6V - LA2 DCR2
+
1/3
R2 C2
-
COMPA + ISENA2N ISENA2P
+ +
- ISENA2N 680
Figure 35. Current Loop Structure
Figure 35 shows the whole current loop structure. The Design Step
current loop plays an important role in the RT3606BC that The RT3606BC excel based design tool is available. Users
can decide ACLL performance, DCLL accuracy and can contact your Richtek representative to get the
ICCMAXA accuracy. For ACLL performance, the correct spreadsheet. Three main design procedures for RT3606BC
compensator design is assumed, if RC network time design, first step is initial settings, second step is loop
constant matches inductor time constant LAX / DCRX, an design and the last step is protection settings. The
expected load transient waveform can be designed. If RXCX following design example is to explain RT3606BC design
network time constant is larger than inductor time constant procedure :
LAX / DCRX, VAXG waveform has a sluggish droop during
load transient. If RXCX network is smaller than inductor VAXG Specification
time constant LAX /DCRX, a worst VAXG waveform will sag Input Voltage 12V
to create an undershooting to fail the specification. No. of Phases 2
For DCLL performance and ICCMAXA accuracy, since the Vboot 0.9V
copper wire of inductor has a positive temperature ICCMAX 76A
coefficient, when temperature goes high in the heavy load ICC-DY 42A
condition, DCR value goes large simultaneously. A resistor
ICC-TDC 45A
network with NTC thermistor compensation connecting
between the IMONA to REF pins is necessary, to Load Line 3.1m
compensate the positive temperature coefficient of inductor Fast Slew Rate 10mV/s
DCR. The design flow is as presented in current loop Max Switching
400kHz
design in details of CORE VR. Frequency

68
RT3606BC
In IMVP8 VRTB Guideline, the output filter requirements  Typical compensator design can use the following
of VRTB specification for desktop platform are : equations to design the C1 and C2 values
Output Inductor : 220nH/0.49mΩ C2  1  87pF
R1   fSWA
Output Bulk Capacitor : 470μF/2.5V/7mΩ (max) 4 to 5pcs
C  ESR
C2  OUT  115pF
Output Ceramic Capacitor : 22μF/0805 (14pcs max in R2
cavity) For Intel platform, in order to induce the band width to
(1) Initial Settings : enhance transient performance to meet Intel’s criterion,
RT3606BC initial voltage is 0.9V the compensator of zero can be designed close to 1/10
of switching frequency.
(2) Loop Design :
 SETA1 resistor network design : First the ICCMAX is
On time setting : Using the specification, TONA is
design as 76A. Next, OCP threshold is designed as
TONA  4.73p  1.2 1.5 x ICCMAX. Last, DVID compensation parameters
TONA = ( VDAC < 1.2) = 204n
VIN -VDAC need to be decided. The DVID_TH can be calculated as
The on time setting resistor RTONA = 400kΩ following equation
 Current sensor adopts lossless RC filter to sense current VDVID_TH = LL  COUT  dVID
dt
signal in DCR. For getting an expect load transient
Where LL is load line, COUT is total output capacitance
waveform, RxCx time constant needs to match
and dVID/dt is DVID fast slew rate. Thus VDVID_TH =
Lx / DCRx per phase. Cx = 0.47μF is set, then
39.67mV is needed in this case. By using above
LX
RX   780 information, the two equations can be listed by using
0.47 F  DCR X
multi-function pin setting mechanism
 IMONA resistor network design : TL = 25°C, TR = 50°C 0.479  R2  3.2
and T H = 100°C are decided, NTC thermistor = R1  R2
100kΩ@25°C, β = 4485 and ICCMAXA = 76A. According 0.536  80 Α  R1 R2
R1  R2
to the sub-section “Current Loop Design in Details”,
R1 = 44.84kΩ, R2 = 7.89kΩ.
RIMONA1 = 10.6kΩ, RIMONA2 = 15.05kΩ and RIMONA3 =
11.46kΩ can be decided. The REQA (25°C) = 23.86kΩ.  SETA2 resistor network design :
400k
 Load-line design : 2.1mΩ droop is requirement, because RAMP = 133% x = 133%, 133% is set. And
400k
REQA(25°C) has decided, the voltage loop Av gain is also DVID_Width is chosen as 24μsec typical. Last, the QR
can be decided by following equation mechanism parameters need to be designed first. Initial
1  DCR  R QR_TH is designed as 20mV and QR_Width is designed
EQA
AI 3 RCSA as 0.44 x TON. By using the information, the two
RLLA 
AV

R2
 m 
equations can be listed by using multi-function pin
R1
setting mechanism
Where DCR (25°C) = 0.6mΩ, R CS = 680Ω and
REQA (25°C) = 23.86kΩ. Hence the AV = R2 / R1 = 2.26 0.661  R2  3.2
can be obtained. R = 10kΩ usually is decided, so R2 = R1  R2
22.6kΩ. 0.761  80 Α  R1 R2
R1  R2
R1 = 46.05kΩ, R2 = 12kΩ.

69
RT3606BC
(3) Protection Settings : (4) Addressing Settings :
 OVP protections : When the VSENA pin voltage is  SET3 resistor network design : Based on table13
350mV more than VID, the OVP will be latched. When information, the two equations can be listed as following
VSENA pin voltage is 350mV less than VID, the UVP R2
0.060   3.2V
will be latched. R1 R2
R1 R2
 TSEN and VR_HOT design : Using the following equation 0.261  80Α 
R1 R2
to calculate related resistances for VR_HOT setting.
R1 = 171.3kΩ, R2 = 3.32kΩ.
VTSENA  80 A  RA1// RA2  R ANTC (100C)  
Table 13. SET3 design information

Main address:00 Anti-oversh Anti-overshoot
Main and auxiliary
Function1 Auxiliary oot function PWM behavior is AI gain is 1.
rail disable zero load
address:01 disable high to tri stage.
Select low DVID slew Enable DVID When 1 phase
PSYS function
Function2 frequency ramp rate is compensation application,
disable
table 11.25mV/s function ramp increase.
Thermal Considerations
For continuous operation, do not exceed absolute resistance, θJA. The derating curve in Figure 36 allows
maximum junction temperature. The maximum power the designer to see the effect of rising ambient temperature
dissipation depends on the thermal resistance of the IC on the maximum power dissipation.
package, PCB layout, rate of surrounding airflow, and
4.5
difference between junction and ambient temperature. The Four-Layer PCB
Maximum Power Dissipation (W)1
4.0
maximum power dissipation can be calculated by the
following formula : 3.5
3.0
PD(MAX) = (TJ(MAX) − TA) / θJA
2.5
where TJ(MAX) is the maximum junction temperature, TA is
2.0
the ambient temperature, and θJA is the junction to ambient
1.5
thermal resistance.
1.0
For recommended operating condition specifications, the
0.5
maximum junction temperature is 125°C. The junction to
0.0
ambient thermal resistance, θJA, is layout dependent. For
0 25 50 75 100 125
WQFN-60L 7x7 package, the thermal resistance, θJA, is
Ambient Temperature (°C)
25.5°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C Figure 36. Derating Curve of Maximum Power
can be calculated by the following formula : Dissipation
PD(MAX) = (125°C − 25°C) / (25.5°C/W) = 3.92W for

WQFN-60L 7x7 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal

70
RT3606BC
Outline Dimension
1 1
2 2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.
Dimensions In Millimeters Dimensions In Inches

Symbol
Min. Max. Min. Max.
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.150 0.250 0.006 0.010
D 6.900 7.100 0.272 0.280
D2 5.650 5.750 0.222 0.226
E 6.900 7.100 0.272 0.280
E2 5.650 5.750 0.222 0.226
e 0.400 0.016
L 0.350 0.450 0.014 0.018
H 0.250 0.350 0.010 0.014
W-Type 60L QFN 7x7 Package

71
RT3606BC
Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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Dual Channel PWM Controller with Integrated Driver for IMVP8

ALERT PWMA2 Driver MOSFET VAXG

DS3606BC-00 October 2015 www.richtek.com

Functional Pin Description

www.richtek.com DS3606BC-00 October 2015

31, 39, 46 NC No Internal Connection.

DS3606BC-00 October 2015 www.richtek.com

www.richtek.com DS3606BC-00 October 2015

From Control Logic DVID SR

DS3606BC-00 October 2015 www.richtek.com

Loop Control/Protection Logic IMON Filter

MUX and ADC

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DS3606BC-00 October 2015 www.richtek.com

www.richtek.com DS3606BC-00 October 2015

DS3606BC-00 October 2015 www.richtek.com

www.richtek.com DS3606BC-00 October 2015

DS3606BC-00 October 2015 www.richtek.com

www.richtek.com DS3606BC-00 October 2015

DS3606BC-00 October 2015 www.richtek.com

Recommended Operating Conditions (Note 4)

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Parameter Symbol Test Conditions Min Typ Max Unit

DS3606BC-00 October 2015 www.richtek.com

Under-Voltage Lockout VUVLO Falling edge 3.95 4.05 4.15 V

VDIO, ALERT and IVDIO = 10mA

www.richtek.com DS3606BC-00 October 2015

DS3606BC-00 October 2015 www.richtek.com

www.richtek.com DS3606BC-00 October 2015

DS3606BC-00 October 2015 www.richtek.com

Time (500μs/Div) Time (50μs/Div)

CORE VR OCP CORE VR OVP

Time (100μs/Div) Time (50μs/Div)

CORE VR Dynamic VID Up CORE VR Dynamic VID Down

Time (10μs/Div) Time (10μs/Div)

www.richtek.com DS3606BC-00 October 2015

CORE VR Dynamic VID Up CORE VR Mode Transient

CORE VR Mode Transient CORE VR Thermal Monitioring

VIMON vs. Load Current AXG VR Power On from EN

DS3606BC-00 October 2015 www.richtek.com

AXG VR Power Off from EN AXG VR OCP

VAXG PGOOD PGOOD

Time (500μs/Div) Time (100μs/Div)

AXG VR OVP AXG VR Dynamic VID Up

PGOOD VAXG VCLK

Time (50μs/Div) Time (10μs/Div)

AXG VR Dynamic VID Down AXG VR Dynamic VID Up

Time (10μs/Div) Time (10μs/Div)

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AXG VR Mode Transient AXG VR Mode Transient

AXG VR Thermal Monitioring VIMONA vs. Load Current

Load Current (A)

DS3606BC-00 October 2015 www.richtek.com

and a 2/1 multiphase synchronous buck controller, the

General loop Function

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Figure 2. Diode Emulation Mode (DEM) in Steady State

Output capacitor COMP signal