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Modulo N Counter

The document describes a synthesizable modulo-n counter design that can be used to generate delays in digital circuits without using non-synthesizable wait statements. It presents two Verilog modules: 1) A basic modulo-n counter and 2) An enabled modulo-n counter. It then explains how the counter can be used to create a synthesizable delay generator by counting clock cycles.

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Shankar Rao
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© Attribution Non-Commercial (BY-NC)
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231 views

Modulo N Counter

The document describes a synthesizable modulo-n counter design that can be used to generate delays in digital circuits without using non-synthesizable wait statements. It presents two Verilog modules: 1) A basic modulo-n counter and 2) An enabled modulo-n counter. It then explains how the counter can be used to create a synthesizable delay generator by counting clock cycles.

Uploaded by

Shankar Rao
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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---------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 22:24:17 09/19/2010 -- Design Name: -- Module Name: mod_n_counter_001 - arch -- Project

Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mod_n_counter_001 is generic ( g_counter_bits g_modulus integer:= 7 port ( reset : in ); clk std_logic; : in std_logic; : integer:= 3; :

o_tick : out std_logic ); end mod_n_counter_001; architecture arch of mod_n_counter_001 is signal i_counter_now downto 0); signal i_counter_next begin process(clk, reset) begin : unsigned(g_counter_bits-1 : unsigned(g_counter_bits-1 downto 0);

if (reset = '1') then i_counter_now <= (others=>'0'); elsif (clk'event and clk = '1') then i_counter_now <= i_counter_next; end if; end process; i_counter_next <= (others => '0') when i_counter_now = (g_modulus-1) else (i_counter_now+1); o_tick <= end arch; '1' when i_counter_now = g_modulus-1 else '0';

---------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 22:24:17 09/19/2010 -- Design Name: -- Module Name: mod_n_counter_en_001 - arch -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mod_n_counter_en_001 is generic ( g_counter_bits g_modulus integer:= 7 port ( reset : in ); clk std_logic; i_en : in std_logic; : integer:= 3; :

: in std_logic;

o_tick : out std_logic ); end mod_n_counter_en_001; architecture arch of mod_n_counter_en_001 is signal i_counter_now downto 0); signal i_counter_next begin process(clk, reset) : unsigned(g_counter_bits-1 : unsigned(g_counter_bits-1 downto 0);

begin if (reset = '1') then i_counter_now <= (others=>'0'); elsif (clk'event and clk = '1') and i_en = '1' then i_counter_now <= i_counter_next; end if; end process; i_counter_next <= (others => '0') when i_counter_now = (g_modulus-1) else (i_counter_now+1); o_tick <= end arch; '1' when i_counter_now = (g_modulus-1) else '0';

Schematic diagram for a modulo n counter

A synthesizable delay generator instead of 'wait for' statement


There are many situations in which you may need to activate a process after a certain delay or at fixed time intervals.If you want to do simulation alone for your design then you can simply use "wait for" statement to call a delay routine.But this keyword is not synthesizable.So what will you do in such situations? A simple delay routine,which is synthesizable, can be designed using the properties of a "MOD-n counter".A MOD-n counter can be used to generate a frequency of (f / n) using a frequency 'f'. The code for generating such a delay is given below: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test is port (clk : in std_logic; --delay to be generated. a : in std_logic_vector(31 downto 0); --this is a pulse to notify that time interval equal to delay is over. flag : out std_logic ); end test; architecture Behavioral of test is signal count :integer:=0; begin process(clk) begin if(clk'event and clk='1') then count <= count +1; --increment counter. end if; --see whether counter value is reached,if yes set the flag. if(count = conv_integer(a)) then count <= 0; flag <='1'; else flag <='0'; end if; end process; end Behavioral;

The module has 2 inputs0- clock and a vector which determines the amount of delay to be generated. Say you want a 100 ns delay.Now say your clk frequency is 1 GHz,that is your clock period is 1 ns.So the value of 'a' should be equal to (100 / 1) = 100.When the counter counts till 100, it sends a pulse to notify.Below is an example of how to do it : ---- a program which uses a delay routine of 100 ns. architecture Behavioral of your_module is signal flag : std_logic :='0'; signal delay_needed : std_logic_vector(31 downto 0); delay_needed <= "00000000000000000000000001100100"; --100 in binary. inst_delay : test port map(clk,delay_needed,flag); begin process(flag) begin if(flag'event and flag='1') then output <= calculated; -- this line is executed only once in 100 ns. end if; end process; end Behavioral; This small code can be used under many situations,like : 1) To run some parts of your design at a lesser clock frequency than your system clock. 2) To create a delay between some of the processes. The range of delay values can be increased by increasing the size of 'a'.Also the maximum error in the delay produced is equal to time period of input clock.

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