Introduction

Definitions :

“An Embedded System is a system that has embedded software and computer
hardware, which makes if a system dedicated for an application or specific part
of an application”

“An embedded system is a microcontroller-based, software –driven, reliable,

real time control system, autonomous, or human-or network interactive,
operating on diverse physical variables and in diverse environments, and sold
into a competitive and cost-conscious market”.

“An Embedded systems are electronic systems that contain a microprocessor or

microcontroller, but we do not think of them as computers” The computer is
hidden or Embedded in the system”

“An Embedded system is a Electronic/Electro-mechanical system designed to

perform a specific function and is a combination of both hardware and
firmware”
Definition : “An electronic controller built into the application, continuously
monitors the process variables and ensures that the Process variable (PV) does
not change; in the event of a change the controller generates a counteracting
signal applied to the application so that the deviated PV is brought to its normal.

Example :
Air conditioner : What does an air conditioner do ?.
 The temperature is set as per requirement, say 190C.
 There may be variations in external temperature and that will also reflect
in the room air conditioner if fitted.
 But however the external temperature varies, the AC machine facilitates
user with cool atmosphere.

Assume : Process variable : Temperature ; Controller : Keep on monitors the PV

If at all room temperature changes due to variation in external temperature
changes, controller will take a counter signal and PV will be brought to required
range.

Pace maker : Its work to trigger the heart beat if at all heart is getting into
trouble.

Assume : Heart beat : PV Controller : Monitors the heart beat.

If it is getting low, immediately a counter acting will be taken and it will boost up
the heart
Applications :

Single functioned : Microwave oven , Mobile phone, ATMs, Car braking

systems, Automobile cruise controllers

Real time and Reactive : Pace makers, ECG, Flight Landing control
Cruise controller : Monitors : Acceleration or deceleration

Complex algorithms : Digital camera

User interface : Ex ATM

Multirate : Digital camera

Embedded System-on-Chip(SOC) AND Use of VLSI Circuit Design Technology

Embedded Systems are being designed on a Single Silicon Chip, Called

System on chip(SoC)

SoC is a system on a VLSI Chip that has all the necessary

• Analog &Digital circuits
• Processors
• Software

A SoC may be embedded with the following components

• Embedded Processor : GPP or ASIP Core

• Single Purpose processing cores or multiple processors
• A Network bus protocol core
• An encryption function unit
• Memories
• Discrete cosine transforms for Signal processing applications
• Intellectual Property Cores
• FPGA (Field Programmable gate array) cores
• Programmable logic device
An embedded system processor chip or core can be one of the following

1. General Purpose Processor(GPP):

(Instruction set designed not to specific application)
• Microprocessor
• Embedded processor
2. Application Specific Instruction-Set Processor (ASIP)
• Microcontroller
• Embedded microcontroller
• DSP & Media Processor
• Network processor
3. Single Purpose Processors as additional processors
• Coprocessor
Ex: Graphic Processing,Floating Point Processing, Encrypting
• Accelerator Ex.Java codes accelerator
• Controllers Ex: for peripherals,direct memory accesses, &
buses
4. GPP or ASIP cores integrated into either ASIC or a VLSI circuit
FPGA cores integrated with processor units in a VLSI

5. Application specific System Processor (ASSP)

Real time video processing EX: TV decoders,set-up boxes,DVD
6. Multicore processors or multiprocessor
General Purpose Processor (GPP):

Microprocessor Source CISC or RISC

80x86 Intel CISC
68HCxxx Motorola CISC
SPARC Sun RISC
ARM ARM RISC with CISC
Application Specific Instruction-Set Processor (ASIP)
Microcontroller Source CISC or RISC
8051,8051MX Intel,Philips CISC

68HC11xx,HC12xx,HC16xx Motorola CISC

PIC 16F84 or 16C76, 16F876 Microchip CISC

CORTEX-M3 : ARM9/ARM7 ARM, Texas, Philips, RISC core with
Samsung and ST CISC
Microelectronics
Application Specific Instruction-Set Processor (ASIP)
Digital Signal Processor

DSP Processor Source

TMS320Cxx Texas
Tiger SHARC Analog device
5600xx Motorola
PNX 1300, 1500 Philips
Classification of Embedded Systems
Small scale embedded systems
• Designed with a 8-bit or 16-bit µC
• Complexities are Less : hardware & software
• Board level design
• Battery operated
• Developing Embedded software
an Editor, Assembler, cross assembler,
an Integrated development environment (IDE)
• Using C language programs are compiled into
assembly and executable codes are appropriately
located in the system memory

Medium scale embedded systems

• Designed with a single or a few 16-bit or 32-bit µc,DSPs
• Complexities are more : hardware & software
• Developing Embedded soft-ware
C/C++/Visual C++/Java, RTOs, source code
engineering tool, simulator, debugger,
an Integrated development environment (IDE)
Classification of Embedded Systems
Sophisticated embedded systems
Designed with ASIPs, PLAs,Configurable processors
Complexities are more: Hardware & software
Used for cutting edge applications
Software functions
• Encryption and deciphering algorithms
• Discrete cosine transformation
and Inverse transformation algorithms
• TCP/IP Protocol stacking
• Network driver functions (hardware)

C/C++/Visual C++/Java, RTOs and other programming

tools
 Harvard architecture Von-neumann architecture

CPU is connected with both the data There is no separate data and
memory (RAM) & Program memory program memory. It is
(ROM) connected with a memory
(ROM)
Requires more hardware because Requires less hardware
separate address bus and data buses
Requires more space Requires less space

Speed of execution is faster because Speed of execution is slower

the fetches data and instructions since cannot fetch the data and
simultaneously instructions at the same time
Components of Embedded system
Memory Organization

Memory Scales Examples :

Data Centers : Peta Bytes

Personal Computer : MB-TB

Embedded Systems : KB-MB

SRAM : 4 KB-32 KB : Program Data

Flash : 32 KB- 256 KB : Program Code

Volatile : This memory works as long as it is powered

: RAM (Random Access Memory)
It loses its stored value when power is removed.

Non-Volatile : This memory that retains its stored value when power is
removed. ROM (Read Only Memory)
ROM (Read Only Memory) :

• ROM is used to hold a program that is executed automatically by

the system every time it is turned-on or reset.

• This program is called BOOTSTRAP or BOOT LOADER,which instructs

the system load its operating system from its Hard disk.

RAM (Random Access Memory)

It does not retain the data stored in it, when the system power is
turned-off.

A mobile phone has 128 KB or 256KB of RAM to hold stack and

temporary variables of the program
Princeton Architecture : 80x86 & ARM7
Read
Vectors and
Pointers
Write
Program Memory

Do-Da-1 • Boostup Programs

Program Memory • Functions
• Routines
• Tasks

Ao-Aa-1
Data Memory
Address range

0X0000 to 0XFF FF

Stack Data Memory

• I/P Data
• O/P Data
Harvard Architecture : 8051
Read
Vectors and
Pointers
Write
Program Memory
Do-Da-1
• Boostup Programs
Program Memory • Functions
• Routines
• Tasks
Ao-Aa-1

Data Memory
Address range

0X0000 to 0XFF FF

Stack Data Memory

• I/P Data
• O/P Data
Princeton Architecture :

Vectors and Pointers

Variables
Program Segments Different Addresses in the Program
Memory Block of Data
Stacks

Harvard Architecture :

Program Segments Separate Set of Addresses

Memory Block of Data
Stacks

Single instruction multiple data type instructions and DSP instructions

Ex: 8051 : CJNE Reg1,Reg2,Memorylocation (Compare two registers , if

both are not equal then Program control will transfer to that memory
location)
Basic Memory Map : 64 KB

FFFFH
Peripherals
(8KB)
8192 Bytes
E000H
DFFFH

SRAM
(24KB)
24496 Bytes
8000H
7FFFH
EPROM
(32KB) Note :
32768 Bytes A15 line if it is low : EPROM
A15 line is High : SRAM
0000H
Memory Map :
Smart Card/
Credit card/ Debit card : 2KB
Java Embeddedcard : 32KB

0x201FFH 0x201FFH
EEPROM EEPROM
512 Bytes 512 Bytes

0x20000H 0x20000H

0x100FFH 0x10FFFH

RAM RAM
(256 BYTES) (4KB)
4048 BYTES)
0x10000H 0x10000H
0x007FFH 0x07FFFH

ROM ROM
(2KB) (32KB)
2048 Bytes 2048 Bytes

0x00000H 0x00000H
Memory Map
Smart Card

Credit/Debit Card
Memory Map
Memory Mapped I/O & I/O Mapped I/O
Memory mapped I/O

 It is a method to perform I/O Operations between CPU and Peripherals

: Uses the Same Address space for Memory and I/O Devices

 Memory Mapped I/O Uses the same instructions for both I/O & memory
operations

I/O Mapped I/O

 It is a method to perform I/O Operations between CPU and Peripherals

: Uses the two separate Address spaces for Memory and I/O Devices

 I/O Mapped I/O Uses the Separate instructions for read & write operations in
I/O & memory operations
Bus Arbitration:
It is a Process by which current bus master accesses and then leaves
the control of the bus and pass it to the another bus requesting
processor unit.

The controller that has access to a bus at an instance known as a Bus

Master.

Bus Arbitration Methods :

• Daisy Chaining method

• Polling Priority method

• Fixed Priority Method

Daisy Chaining Method:

Memor
y
Another Processor
Processor 2
1 Slave
Main Slave
Bus
Process con
or trolll
Master er Request signal to access Buses (Address
bus/Data bus) Method s: Used to accessing
buses
 Polling Priority Method

Polling ID: 000 Polling ID: 001 Polling ID: 010

Device 0 Device 1 Device 2

Bus Grant

Polling lines
Bus Arbiter
Bus Request

Polling IDs : Assume if 8 no devices are connected

Polling lines : 2^3= 8 = 3 lines represent : Device ID

Ex : If Device 1 has highest priority, then bus master gives permission to

Device 1 by Place corresponding Polling ID

Polling IDs : Device 0 : 000 Device1: 001 Device 2: 010 Device 3: 011
and so on
Fixed Priority Method

Bus Grant
Device 1

Bus Request

Bus Grant
Bus Arbiter
or Device 2
Bus Master Bus Request
Bus Grant
Device 3

Bus Request
Design Process
Concepts Used during a Design
1. Abstraction
• Problem component to be abstracted

2. Hardware & software Architectures

• Architectures should be well understand before a design

3. Extra functional properties

• Extra functionalities required in the system being developed
should be well understand

4. System Related family of designs

• Families of related systems developed earlier should be taken
into consideration during designing

5. Modular design
• System designing is fast by decomposition of software into
modules that are to be implemented
6. Mapping:
Ex : Image is I/p data to a system
It can have different no of pixels and colours
System does not process each pixel and colour individually

Transform mapping of image is done by appropriate

compression and storage algorithms

7. User Interface Design

User interfaces are designed as per user requirements
Ex : Automatic Chocolate or Coffee Vending Machine
User Interface is LCD
It can display welcome message
Also specify the coins / Amount needed to be inserted into the
machine for each type of chocolate

8. Refinements :
Each Component and module design needs to be refined
iteratively till it becomes the most appropriate for implementation by
the software team
The Embedded System Design Process :
Requirements :
Purpose, Inputs, Outputs, Functioning , Design metrics and
Validation requirement for Finally developed system.

Power Dissipation, Performance, Process dead lines, User

Interface, Size, Engineering cost, Manufacturing Cost, Time to market,
System and User safety

Specification:
Customer Expectations from the Product
Designer Needs specifications for
Hardware : Peripheral devices, Processor,& Memory
Data types & Processing specification
Expected System Behaviour
Constraints of Design
Expected Life Cycle
Architecture

Data modeling designs of attributes of Data Structure, Data flow

graphs, Software architecture layers and hardware architecture are
defined.

First Layer : Architectural Design

Data Structures
Data bases
Algorithms
Control Functions
State Transitions
Process and Data and Program Flow
Second Layer : Data Design
Design of Data Structures and Data Bases
would be most appropriate for given
problem

Third Layer : Consist of Interface Design

What shall be the interfaces to Integrate the components?
What is the Design for System Integration?
Components :

Component Level Design

Processor
Memory
Peripherals and Devices
Ports & Buses
Power Source & Battery

System Integration :
Built components are integrated in the system.
The system is made to function and validated.
Debugging tools are used to correct erroneous functioning.
Challenges in Embedded Computing System Design

How much hardware do we need ?

How do we minimize power consumption?
How do we design for upgradability?
Does it Really work?
Software in Embedded System
: An Overview of programming Language
Machine Coding

Assembly Coding

High level Coding

“AnEmbedded System processor executes software that is

specific to a given application of that system”

“Instruction Codes and Data in the Final phase are placed

in the ROM (or)FLASH Memory for all the tasks are executed
when system runs”

The software is also called “ROM image”

Assembly/C/C++------------------------- ROM Image
A machine implementable software file is therefore like a table having in
each rows the address and bytes.

The table has to be reached as a “ ROM Image” for the targetted

hardware. PC-Address
SP-Address
2-Bytes for Address from where
ISR Vector system starts execution on
2-Bytes for addresses of 2 powerup
Address of bytes each
Stack on
RESET Bootup Program

Machine codes for

Specific codes for
each program, ISR &
Tasks

RTOS Machine codes for Real time

Operating Systems

ROM Image on System Memory

“Final Stage Software” is also called the ROM Image

The Final machine implementable software for a product embeds in the one
programmable FLASH ROM as an “Image” in a Frame.

“A Program or a Small part can be coded in assembly language using an

Assembler”

Assembler is Software used for developing codes in Assembly.

ALP Coding is extremely used for Configuring Physical Devices like

PORTs,
Display Interface,
ADC,
DAC,
Reading into or transmitting from a Buffer
PROCESS OF CONVERTING ALP TO ROM Image

Machine Machine
Machine
Specific Assembler Codes ready
Codes for the
Assembly for locating at
1 Programs at
Language various
various 3
Program Addresses
Addresses

Reallocation
Device
Programmer
From Library Linker ROM’
Needed Bytes for Linked Loader Burner
2
Machine Codes Program

ES ROM Memory
Data Bytes
Assembler : Translates assembly software into the machine codes

Linker : Links the codes with other codes required

Ex: There are standard codes to program a delay task
for which there is a reference in ALPs
The linked file in Binary for run on a computer is commonly known as an
executable file or .EXE file

Loader : Reallocating the codes after finding the Physical addresses

Locator : Locates I/O Tasks and Hardware device driver at Fixed Addresses
and then Burn
C language to ROM Image

C Program
Machine Codes in
Function
Object File
Complier

Code Optimizer
From
Linker
Library Bytes for Linked
Needed Programs
Machine
Codes
Step 3 & 4 Same
as Previous

Embedded
System ROM
Memory
Ex :
Bank 2 needs to be select
SETB PSW.3 (Set bit) R0=1
CLR PSW.4 Clear bit R1=0
R1 R0
1 0 Bank 2
2 Bank 3
3 SETB PSW.3 R0=1
4 SETB PSW.4 R1=1
5 Bank0 ,1,2,3: Register R0-R7 (Each bank 8 no
bytes R0 R1, R2,R…R7
Addressing modes

Register Addressing mode

MOV A,R5
Direct Addressing mode
MOV A,07H ; 07 = RAM memory location

INDIRECT Addressing mode

MOV A,@R0 ( @ symbol indirectly shows memory location)

MOVC
Indexed addressing mode :
(Move from Code Memory)
MOVC A, @A+DPTR ; MOVC A,@A+PC
(Base address DPTR + Offset A)
DPTR = 2006 2006 = …
A= 02H 2007=
2008 2008= 89
Immediate addressing
# Symbol represents a Immediate data
MOV A,#45H (45 Immediate data -----A)
Addressing Modes:
This is a method to define Operands
dest operand, Source Operand

Register Addressing
Data can transfer between Register to Register
MOV A, R7
MOV B, R0
Invalid : MOV R0,R4
All banks have same names , It may confuse.

Immediate Addressing (# Symbol used along with

a immediate data )
MOV A,#48H 48H------- A=48
Addressing Modes:
This is a method to define Operands
dest operand, Source Operand

Register Indirect Addressing (@R0)

Data can transfer between Memory location
Indirectly pointed by any Register to Mem/Register
MOV A, @R0 (R0=55)
mem loc 55= 78
MOV B, @R0

Direct Addressing : ( if any 8-bit presence in one of

destination operand)
MOV A,48H 48H------- A=57
48H is a RAM Memory location=57H
Data Transfer Instructions :
MOV , MOVX,MOVC , PUSH, POP,XCH, XCHD

MOV R0,40H : 40H RAM memory location

MOV 40H,R0
MOV A,@R0 : Move data between register to memory / mem-Reg/ Reg-Reg

MOV A,#40H ( Immediate data )

X External Memory (Data)

MOVX ( Move the data between external memory to register/ reg-ext mem)

MOVX A,@R0 : R0 Indirectly pointing a memory location (External)

MOVX @R0,A
MOVX A,@DPTR ; DPTR contains a 16-bit address (EXTERNAL MEMORY)
MOVX @DPTR,A

MOVC (Code memory) : Is used for reading from the code memory

MOVC A,@A+DPTR
PUSH : Push the content available in R0 move to Top of Stack
Ex: First STEP: Stack Pointer Increments by ONE (SP+1)
Second Step : Transfer R0 content on Stack memory

PUSH AR0 : PUSH AR0

PUSH AR1

Ex : If SP=07H before executing PUSH instruction, what will be content in SP

after execution?
SP=07 Before execution & SP=08 After execution
POP :

Ex : POP AR0

First Step : Content pointed by SP will move to R0

Second Step : SP Decrements by one (SP-1)

If SP=08H before executing POP instruction, what will be content in SP after

execution?
SP=08 Before execution & SP=07 After execution
XCH : Exchange the content between Reg-Reg/Reg-Mem/mem-Reg

Ex : XCH A,07

A= 0FH (Before ex) 07 (RAM mem loc) =FFH

A=FF 07=0F

XCHD (Lower Nibble source to lower nibble dest) :

Xchange the data between Accumulator & Data memory(Indirectly pointed by
any Reg / Directly)

Ex : XCHD A,@R0

Before Execution

A=0FH 07 Mem loc (R0)= F0H

After execution

A = 00H 07 (Memloc)= FFH

Arithmetic & Logical Instructions :

ADD, SUB, MUL, INC,DEC, DIV, DAA , ANL,ORL, XRL, RR,RL,RRC,RLC,SWAP

ADD :

Ex : ADD A,07
ADD A,@R0
ADD A,#40H

ADDC (Addition with Carry)

Ex : ADDC A,R0
If previous Carry Flag =1
A= 08H
+
R0= 01
+
Cy = 01
--------------
=========
SUB

Ex : SUB A,R0

SUBB (Subtraction with Borrow)

Ex : SUBB A,R0
If Previous Carry flag =1
A= 07H
-
R0=01
-
CY=01
------------

Increment : INC 40H

INC R0

Decrement : DEC A
DEC 40H
Multiplication :

MUL AB

After multiplication : Result Low order byte : Accumulator

High order byte : B

Division :

DIV AB

After division

Result Quotient : A Remainder : B

DAA (Decimal Adjust Accumulator) :

To Provide result in Valid BCD
A =28 R0=12
28 3A
+ +
12 06
3A ( “A” It is not valid) 40 (Valid BCD)
Logical Instructions

ANL A,@R0
ANL A,40H

ORL 40H,A
ORL 40H,#07H

XRL A,40H
XRL 40H,A
XRL 40H,#07H

CLR A (Clear bit A)

CLR PSW.5

CPL A

RL A

RR A

RRC A
RLC A

SWAP A (Swapping between A register)

Lower nibble ----Upper Nibble

Ex : A = 07H
After execution
A=70H

Boolean Instructions :
CLR C
SETB C
SETB PSW.3
ANL C,bit(0) CF=1 AND 01 ; CF=
JC address ; Jump if Carry flag=1
JNC ; Jump if no carry CF=0
JB (Jump if bit =1) JB P1.3, Location ;
JNB P1.0,Location (Jump if No Bit P1.0=0)
JBC (jump if bit is set to 1 and Clears the bit) : JBC P1.0, location
JBC P3.5,memory loc
JBC P3.5,
Ex :The pin 3.5 of an 8051 microcontroller is controlled by a
Push Button. Write a sequence of instructions which turns
Port 1 into a counter. The port 1 value has to be
incremented when the Push button is pressed and
released.

MOV P1, #00 ; Count value =00

L1: JB P3.5, $ ;
; Until P3.5 = 1 High, $ symbol to stay in the same line
JNB P3.5,$ ; Until P3.5=0 Low
INC P1 : P1 =1
SJMP L1
Unconditional & Conditional Branching Instructions

JMP, CALL Unconditional

JNZ,CJNE, : Conditional

UNCONDITIONAL :
SHORT JUMP ; SJMP
Program Control transfer within 128 Bytes

LONG JUMP ; LJMP

Program Control transfer with in 64kB memory

ABSOLUTE JUMP : AJMP

Program Control transfer with in 2 kB Page in memory
UNCONDITIONAL :

CALL : Short Call

LCALL : Long Call

ACALL : Absolute call

Difference between JMP & Call : PC : 200A & SP : 200A

PC : 3000 Subroutine:
DELAY
……
…… 2000: MOV A,40H
2000: MOV A,40H 3000: DJNE
2001:
2001: ……..
2005: CPL P1.5
2005: CPL P1.5 ……..RET
-------
------- ------
------ 200A: CALL Delay DELAY14
------- 4000 :
2100: Call delay1 DJNZ ….
200A: JMP 2005 2101 : MUL AB RET
CONDITIONAL :

JC 2006 If this condition is true then only it can transfer

DJNZ R0,2008 : Decrement and If not zero : it will transfer
CJNE A,#80,2008

Ex : When P1.7 is chosen as Output of the Pulse generator

L1: CPL P1.7 : Complement P1.7 bit

SJMP L1

Write a Program to generate 20 pulses

MOV P1,#20 ; P1= 0010 000
DJNZ P1,$ : Decrement P1, IF P1 reaches
zero
JZ
JNZ
DJNZ
CJNE Compare and Jump if not equal
CJNZ
CJNE

Ex : CJNE 40H,#80,200A

CJNE A,#80,200A

DJNZ :

DJNZ 40H,200A

ReturnInterrupt

RETI

NOP No operation
RR A

A = 1000 0010

0100 0001

1010 0000

1000 00 10 CY=1
RRC A
1100 0001 CY=0

0 110 0 0 00 CY=1
RLC A

SWAP A (Swapping between A register)

Lower nibble ----Upper Nibble

Ex : A = 07H
After execution
A=70H

Boolean Instructions :
CLR C
SETB C
SETB PSW.3
ANL C,bit(0)
JC
JNC
JB (Jump if bit =1) JB P1.3, Location
JNB P1.0,Location (Jump if No Bit P1.0=0)
JBC (jump if bit is set to 1 and Clears the bit) : JBC P1.0, location
RLC A

SWAP A (Swapping between A register)

Lower nibble ----Upper Nibble

Ex : A = 07H
After execution
A=70H

Boolean Instructions :
CLR C
SETB C
SETB PSW.3
ANL C,bit(0)
JC
JNC
JB (Jump if bit =1) JB P1.3, Location
JNB P1.0,Location (Jump if No Bit P1.0=0)
JBC (jump if bit is set to 1 and Clears the bit) : JBC P1.0, location
RLC A

SWAP A (Swapping between A register)

Lower nibble ----Upper Nibble

Ex : A = 07H
After execution
A=70H

Boolean Instructions :
CLR C
SETB C
SETB PSW.3
ANL C,bit(0)
JC
JNC
JB (Jump if bit =1) JB P1.3, Location
JNB P1.0,Location (Jump if No Bit P1.0=0)
JBC (jump if bit is set to 1 and Clears the bit) : JBC P1.0, location
RLC A

SWAP A (Swapping between A register)

Lower nibble ----Upper Nibble

Ex : A = 07H
After execution
A=70H

Boolean Instructions :
CLR C
SETB C
SETB PSW.3
ANL C,bit(0)
JC
JNC
JB (Jump if bit =1) JB P1.3, Location
JNB P1.0,Location (Jump if No Bit P1.0=0)
JBC (jump if bit is set to 1 and Clears the bit) : JBC P1.0, location