Logic Gates

Introduction to Basic Gates and Functions
Logic gates
logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs
and one output. At any given moment, every terminal is in one of the two binary conditions low
(0) or high (1), represented by different voltage levels.
Digital systems are said to be constructed by using logic gates. These gates are the AND, OR,
NOT, NAND, NOR, EXOR and EXNOR gates. The basic operations are described below with
the aid of truth tables.
Types of Basic Logic Gates

There are several basic logic gates used in performing operations in digital systems. The
common ones are;
OR Gate
AND Gate
NOT Gate
XOR Gate
Additionally, these gates can also be found in a combination of one or two. Therefore we get
other gates such as NAND Gate, NOR Gate, EXOR Gate, and EXNOR Gate.
OR Gate
In an OR gate, the output of an OR gate attains state 1 if one or more inputs attain state 1.

The Boolean expression of the OR gate is Y = A + B, read as Y equals A ‘OR’ B.
The truth table of a two-input OR basic gate is given as;
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
AND Gate
In the AND gate, the output of an AND gate attains state 1 if and only if all the inputs are in state 1.

The Boolean expression of AND gate is Y = A.B
The truth table of a two-input AND basic gate is given as;
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
NOT Gate
In a NOT gate, the output of a NOT gate attains state 1 if and only if the input does not attain state 1.

The Boolean expression is:
Y=A¯
It is read as Y equals NOT A.
The truth table of NOT gate is as follows;
A Y
0 1
1 0
When connected in various combinations, the three gates (OR, AND and NOT) give us basic logic gates such
as NAND, and NOR gates, which are the universal building blocks of digital circuits.
NAND Gate
This basic logic gate is the combination of AND and NOT gates.

The Boolean expression of the NAND gate is:
―
Y=A.B
The truth table of a NAND gate is given as;
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
NOR Gate
This gate is the combination of OR and NOT gate.

The Boolean expression of NOR gate is:
Y=A+B―
The truth table of a NOR gate is as follows;
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
Exclusive-OR gate (XOR Gate)

In an XOR gate, the output of a two-input XOR gate attains state 1 if one adds only input attains state 1.

The Boolean expression of the XOR gate is:
A.B¯+A¯.B
or
Y=A⨁B
The truth table of an XOR gate is;
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
Exclusive-NOR Gate (XNOR Gate)

In the XNOR gate, the output is in state 1 when both inputs are the same, that is, both 0 or both 1.
The Boolean expression of the XNOR gate

The truth table of an XNOR gate is given below;
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
Boolean Algebra Operations
The basic operations of Boolean algebra are as follows:
Conjunction or AND operation
Disjunction or OR operation
Negation or Not operation

Below is the table defining the symbols for all three basic operations.
Operator Symbol Precedence
NOT ‘ (or) ¬ Highest
AND . (or) ∧ Middle
OR + (or) ∨ Lowest
Suppose A and B are two Boolean variables, then we can define the three operations as;
A conjunction B or A AND B, satisfies A ∧ B = True, if A = B = True or else A ∧ B = False.
A disjunction B or A OR B, satisfies A ∨ B = False, if A = B = False, else A ∨ B = True.
Negation A or ¬A satisfies ¬A = False, if A = True and ¬A = True if A = False
Boolean Expression
A logical statement that results in a Boolean value, either be True or False, is a Boolean expression.
Sometimes, synonyms are used to express the statement such as ‘Yes’ for ‘True’ and ‘No’ for ‘False’. Also, 1
and 0 are used for digital circuits for True and False, respectively.
Boolean expressions are the statements that use logical operators, i.e., AND, OR, XOR and NOT. Thus, if we
write X AND Y = True, then it is a Boolean expression.
Boolean Algebra Terminologies

Boolean Algebra: Boolean algebra is the branch of algebra that deals with logical operations and binary
variables.
Boolean Variables: A Boolean variable is defined as a variable or a symbol defined as a variable or a symbol,
generally an alphabet that represents the logical quantities such as 0 or 1.
Boolean Function: A Boolean function consists of binary variables, logical operators, constants such as 0 and
1, equal to the operator, and the parenthesis symbols.
Literal: A literal may be a variable or a complement of a variable.
Complement: The complement is defined as the inverse of a variable, which is represented by a bar over the
variable.
Truth Table: The truth table is a table that gives all the possible values of logical variables and the
combination of the variables. It is possible to convert the Boolean equation into a truth table. The number of
rows in the truth table should be equal to 2n, where “n” is the number of variables in the equation. For example,
if a Boolean equation consists of 3 variables, then the number of rows in the truth table is 8. (i.e.,) 2 3 = 8.
Boolean Algebra Truth Table

Now, if we express the above operations in a truth table, we get;
A B A∧B A∨B
True True True True
True False False True

False True False True
False False False False
A ¬A
True False
False True
Boolean Algebra Rules

Following are the important rules used in Boolean algebra.
Variable used can have only two values. Binary 1 for HIGH and Binary 0 for LOW.
The complement of a variable is represented by an overbar.
Thus, complement of variable B is represented as B¯. Thus if B=0 then B¯=1 and B =1 then B¯=0.
OR-ing of the variables is represented by a plus (+) sign between them. For example, the OR-ing of A, B, and
C is represented as A + B + C.
Logical AND-ing of the two or more variables is represented by writing a dot between them, such as A.B.C.
Sometimes, the dot may be omitted like ABC.
Laws of Boolean Algebra

There are six types of Boolean algebra laws. They are:
1. Commutative law
2. Associative law
3. Distributive law
4. AND law
5. OR law
6. Inversion law
Those six laws are explained in detail here.
Commutative Law
Any binary operation which satisfies the following expression is referred to as a commutative operation.
Commutative law states that changing the sequence of the variables does not have any effect on the output of a
logic circuit.
A. B = B. A
A+B=B+A
Associative Law
It states that the order in which the logic operations are performed is irrelevant as their effect is the same.
( A. B ). C = A . ( B . C )
( A + B ) + C = A + ( B + C)
Distributive Law
Distributive law states the following conditions:
A. ( B + C) = (A. B) + (A. C)
A + (B. C) = (A + B) . ( A + C)
AND Law
These laws use the AND operation. Therefore they are called AND laws.
A .0 = 0
A.1=A
A. A = A
A.A¯=0
OR Law
These laws use the OR operation. Therefore they are called OR laws.
A + 0 = A
A+1=1
A+A=A
A+A¯=1
Inversion Law
In Boolean algebra, the inversion law states that double inversion of variable results in the original variable
itself.
A¯¯=A
Boolean Algebra Theorems

The two important theorems which are extremely used in Boolean algebra are De Morgan’s First law and De
Morgan’s second law. These two theorems are used to change the Boolean expression. This theorem basically
helps to reduce the given Boolean expression in the simplified form. These two De Morgan’s laws are used to
change the expression from one form to another form. Now, let us discuss these two theorems in detail.
De Morgan’s First Law:
De Morgan’s First Law states that (A.B)’ = A’+B’.
The first law states that the complement of the product of the variables is equal to the sum of their individual
complements of a variable.
The truth table that shows the verification of De Morgan’s First law is given as follows:
A B A’ B’ (A.B)’ A’+B’
0 0 1 1 1 1
0 1 1 0 1 1
1 0 0 1 1 1
1 1 0 0 0 0
The last two columns show that (A.B)’ = A’+B’.
Hence, De Morgan’s First Law is proved.
De Morgan’s Second Law:
De Morgan’s Second law states that (A+B)’ = A’. B’.
The second law states that the complement of the sum of variables is equal to the product of their individual
complements of a variable.
The following truth table shows the proof for De Morgan’s second law.
A B A’ B’ (A+B)’ A’. B’
0 0 1 1 1 1
0 1 1 0 0 0
1 0 0 1 0 0
1 1 0 0 0 0
The last two columns show that (A+B)’ = A’. B’.
Hence, De Morgan’s second law is proved.
The other theorems in Boolean algebra are complementary theorem, duality theorem, transposition theorem,
redundancy theorem and so on. All these theorems are used to simplify the given Boolean expression. The
reduced Boolean expression should be equivalent to the given Boolean expression.
Solved Examples
Question: Simplify the following expression:
c+BC¯
Solution:
Given:
C+BC¯
According to Demorgan’s law, we can write the above expressions as
C+(B¯+C¯)
From Commutative law:
(C+C¯)+B¯
From Complement law
1+B¯=1
Therefore,
C+BC¯=1
Question 2: Draw a truth table for A(B+D).
Solution: Given expression A(B+D).
A B D B+D A(B+D)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 1 0
1 0 0 0 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1
SOP & POS

In digital logic, the inputs and output of a function are in the form of binary numbers
(boolean values) i.e., the values are either zero (0) or one (1). Therefore, digital logic is
also known as ‘Boolean logic’. These inputs and output can be termed as ‘Boolean
Variables’. The output boolean variable of a digital signal can be expressed in terms of
input boolean variables which forms the ‘Boolean Expression’.
Representation of Boolean expression can be primarily done in two ways. They are as
follows:
1. Sum of Products (SOP) form
2. Product of Sums (POS) form

Note:
If the number of input variables are n, then the total number of combinations in Boolean
algebra is 2n.
If the input variable (let A) value is :
 Zero (0) – a is LOW -It should be represented as A’ (Complement of A)
 One (1) – a is HIGH -It should be represented as A

In boolean logic,
AND is represented as '.'
A AND B is written as 'A.B'
OR is represented as '+'
A OR B is written as 'A+B'
For example, Considering number of input variables =3, Say A, B and C.
Total number of combinations are: 2 3=8.

A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Sum of Products (SOP):
It is one of the ways of writing a boolean expression. As the name suggests, it is formed
by adding (OR operation) the product terms. These product terms are also called as
‘min-terms’. Min-terms are represented with ‘m’, they are the product(AND operation)
of boolean variables either in normal form or complemented form.
Therefore, SOP is sum of minterms and is represented as:
F in SOP = m(0, 3)
Here, F is sum of minterm0 and minterm3.
For Example:
A=0, B=0, C=0 Minterm is A'.B'.C'
A=1, B=0, C=1 Minterm is A.B'.C
Consider a function X, whose truth table is as follows:

A B C X
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
The function X can be written in SOP form by adding all the min-terms when X is
HIGH(1).
While writing SOP, the following convention is to be followed:

If variable A is Low(0) - A'
A is High(1) - A
X (SOP) = m(1, 3, 6)
= A’.B’.C + A’.B.C + A.B.C’
Product of Sums (POS):
As the name suggests, it is formed by multiplying(AND operation) the sum terms.

These sum terms are also called as ‘max-terms’. Max-terms are represented with ‘M’,
they are the sum (OR operation) of Boolean variables either in normal form or
complemented form.
Therefore, POS is product of maxterms and is represented as:
F in POS = M(1, 2) Here, F is product of maxterm1 and maxterm2.
For Example:
A=0, B=1, C=0 Maxterm is A+B'+C
A=1, B=1, C=1 Maxterm is A'+B'+C'
Consider a function X, whose truth table is as follows:
A B C X
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
The function X can be written in POS form by multiplying all the max-terms when X is
LOW(0).
While writing POS, the following convention is to be followed:
If variable A is Low(0) - A
A is High(1) - A'
X (POS) = M (0, 2, 4, 5, 7)
= (A+B+C).(A+B'+C).(A'+B+C).(A'+B+C').(A'+B'+C')
Difference between SOP and POS :

S.No. SOP POS
A way of representing boolean A way of representing boolean

1. expressions as sum of product terms. expressions as product of sum terms.
SOP uses minterms. Minterm is product POS uses maxterms. Maxterm is sum of
of boolean variables either in normal boolean variables either in normal form
2. form or complemented form. or complemented form.
It is sum of minterms. Minterms are It is product of maxterms. Maxterms are

3. represented as ‘m’ represented as ‘M’
SOP is formed by considering all the POS is formed by considering all the
4. minterms, whose output is HIGH(1) maxterms, whose output is LOW(0)
While writing minterms for SOP, input While writing maxterms for POS, input
with value 1 is considered as the variable with value 1 is considered as the
itself and input with value 0 is considered complement and input with value 0 is
5. as complement of the input. considered as the variable itself.
Introduction of K-Map (Karnaugh Map)
In many digital circuits and practical problems we need to find expression with
minimum variables. We can minimize Boolean expressions of 3, 4 variables very easily
using K-map without using any Boolean algebra theorems. K-map can take two forms
Sum of Product (SOP) and Product of Sum (POS) according to the need of problem. K-
map is table like representation but it gives more information than TRUTH TABLE.
We fill grid of K-map with 0’s and 1’s then solve it by making groups.
Steps to solve expression using K-map-
1. Select K-map according to the number of variables.
2. Identify minterms or maxterms as given in problem.
3. For SOP put 1’s in blocks of K-map respective to the minterms (0’s
elsewhere).
4. For POS put 0’s in blocks of K-map respective to the maxterms(1’s
elsewhere).
5. Make rectangular groups containing total terms in power of two like 2,4,8 ..
(except 1) and try to cover as many elements as you can in one group.
6. From the groups made in step 5 find the product terms and sum them up for
SOP form.
SOP FORM :
1. K-map of 3 variables –
K-map SOP form for 3 variables
Z= ∑A,B,C(1,3,6,7)
From red group we get product term—
A’C
From green group we get product term—
AB
Summing these product terms we get- Final expression (A’C+AB)

2. K-map for 4 variables –
K-map 4 variable SOP form
F(P,Q,R,S)=∑(0,2,5,7,8,10,13,15)
From red group we get product term—
QS
From green group we get product term—
Q’S’
Summing these product terms we get- Final expression (QS+Q’S’)

POS FORM :
K-map 3 variable POS form
F(A,B,C)=π(0,3,6,7)

From red group we find terms
A B
Taking complement of these two
A' B'
Now sum up them
(A' + B')
From brown group we find terms
B C
Taking complement of these two terms
B’ C’
Now sum up them
(B’+C’)
From yellow group we find terms
A' B' C’
Taking complement of these two
A B C
Now sum up them
(A + B + C)
We will take product of these three terms : Final expression –
(A' + B’) (B’ + C’) (A + B + C)
K-map 4 variable POS form
F(A,B,C,D)=π(3,5,7,8,10,11,12,13)

From green group we find terms
C’ D B
Taking their complement and summing them
(C+D’+B’)
From red group we find terms
C D A’
(C’+D’+A)
From blue group we find terms
A C’ D’
(A’+C+D)
From brown group we find terms
A B’ C
(A’+B+C’)
Finally we express these as product –
(C+D’+B’).(C’+D’+A).(A’+C+D).(A’+B+C’)
PITFALL– *Always remember POS ≠ (SOP)’
*The correct form is (POS of F)=(SOP of F’)’
SEQUENTIAL CIRCUIT
digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the
present value of its input signals but on the sequence of past inputs, the input history as well. This is in
contrast to combinational logic, whose output is a function of only the present input
Combinational Circuit
 The output of a Combinational Circuit depends entirely on the present input.

 It exhibits a faster speed.
 It is comparatively easier to design.
 No feedback is present between the input and output.
 The combinational circuit depends on time.
 Logic gates form the building blocks of such circuits.
 One can make use of it for both boolean and arithmetic operations.
 They don’t hold the capacity of storing any state.
 These circuits do not have a clock- thus, they don’t require triggering.
 They do not possess any memory element.
 Users can feasibly use as well as handle them.
 Example – Demultiplexer, Multiplexer, Decoder, Encoder, etc.
Sequential Circuit
 The output of a Sequential Circuit depends on both- past as well as present inputs.
 It works at a comparatively slower speed.
 The design of these circuits is comparatively much tougher than the Combinational Circuit.
 A feedback path exists between the output and the input.
 The circuit is time-dependent.
 Flip-flops constitute the building blocks of such a circuit.
 People mainly use them for storing data and information.
 They possess the capability of storing any data state or retaining an earlier state at any given
point.
 Because a Sequential circuit depends on a clock, it usually requires triggering.
 They always possess a memory element.
 A user may not be able to handle and use these circuits easily.
 For Example – Counters, Flip-flops, etc.
Parameters Combinational Circuit Sequential Circuit
Meaning and It is a type of circuit that It is a type of circuit in which the output
Definition generates an output by relying does not only rely on the current input. It
on the input it receives at that also relies on the previous ones.
instant, and it stays
independent of time.
Feedback A Combinational Circuit The output of a Sequential Circuit, on

requires no feedback for the other hand, relies on both- the
generating the next output. It previous feedback and the current input.
is because its output has no So, the output generated from the
dependency on the time previous inputs gets transferred in the
instance. form of feedback. The circuit uses it
(along with inputs) for generating the
next output.
Performance We require the input of only In the case of a Sequential Circuit, the
the current state for a performance is very slow and also
Combinational Circuit. Thus, it comparatively lower. Its dependency on
performs much faster and the previous inputs makes the process
better in comparison with the much more complex.
Sequential Circuit.
Complexity It is very less complex in This type of circuit is always more

comparison. It is because it complex in its nature and functionality.
basically lacks It is because it implements the
implementation of feedback. feedback, depends on previous inputs
and also on clocks.
Elementary Logic gates form the building/ Flip-flops form the building/ elementary
Blocks elementary blocks of a blocks of a Sequential Circuit.
Combinational Circuit.
Operation One can use these types of You can mainly make use of these types
circuits for both- Boolean as of circuits for storing data.
well as Arithmetic operations.
Combinational Logic circuits
The combinational logic circuits are the circuits that contain different types of logic
gates. Simply, a circuit in which different types of logic gates are combined is known as
a combinational logic circuit. The output of the combinational circuit is determined
from the present combination of inputs, regardless of the previous input. The input
variables, logic gates, and output variables are the basic components of the
combinational logic circuit. There are different types of combinational logic circuits, such
as Adder, Subtractor, Decoder, Encoder, Multiplexer, and De-multiplexer.
There are the following characteristics of the combinational logic circuit:
o At any instant of time, the output of the combinational circuits depends only on the
present input terminals.
o The combinational circuit doesn't have any backup or previous memory. The present
state of the circuit is not affected by the previous state of the input.
o The n number of inputs and m number of outputs are possible in combinational logic
circuits.
The 'n' input variable comes from the external source while the 'm' output variable goes
to the external destination. In many applications, the source or destinations are storage
registers.
Half Adder
The half adder is a basic building block having two inputs and two outputs. The adder is
used to perform OR operation of two single bit binary numbers. The carry and sum are
two output states of the half adder.
Full Adder
The half adder is used to add only two numbers. To overcome this problem, the full
adder was developed. The full adder is used to add three 1-bit binary numbers A, B, and
carry C. The full adder has three input states and two output states i.e., sum and carry.
Half Subtractors
The half subtractor is also a building block of subtracting two binary numbers. It has two
inputs and two outputs. This circuit is used to subtract two single bit binary numbers A
and B. The 'diff' and 'borrow' are the two output state of the half adder.
Full Subtractors
The Half Subtractor is used to subtract only two numbers. To overcome this problem,
full subtractor was designed. The full subtractor is used to subtract three 1-bit numbers
A, B, and C, which are minuend, subtrahend, and borrow, respectively. The full
subtractor has three input states and two output states i.e., diff and borrow.
Multiplexers
The multiplexer is a combinational circuit that has n-data inputs and a single output. It is
also known as the data selector which selects one input from the inputs and routes it to
the output. With the help of the selected inputs, one input line from the n-input lines is
selected. The enable input is denoted by E, which is used in cascade.
De-multiplexers
A De-multiplexer performs the reverse operation of a multiplexer. The de-multiplexer
has only one input, which is distributed over several outputs. One output line is selected
at a time by selecting lines. The input is transmitted to the selected output line.
Decoder
A decoder is a combinational circuit having n inputs and to a maximum of m = 2n
outputs. The decoder is the same as the de-multiplexer. The only difference between
de-multiplexer and decoder is that in the decoder, there is no data input. The decoder
performs an operation that is completely opposite of an encoder.
Encoder
The encoder is used to perform the reverse operation of the decoder. An encoder
having n number of inputs and m number of outputs is used to produce m-bit binary
code which is related to the digital input number. The encoder takes the digital word
and converts it into another digital word.
Multiplexer
A multiplexer is a combinational circuit that has 2n input lines and a single output line.
Simply, the multiplexer is a multi-input and single-output combinational circuit. The
binary information is received from the input lines and directed to the output line. On
the basis of the values of the selection lines, one of these data inputs will be connected
to the output.
Unlike encoder and decoder, there are n selection lines and 2 n input lines. So, there is a
total of 2N possible combinations of inputs. A multiplexer is also treated as Mux.
There are various types of the multiplexer which are as follows:
2×1 Multiplexer:
In 2×1 multiplexer, there are only two inputs, i.e., A 0 and A1, 1 selection line, i.e., S0 and
single outputs, i.e., Y. On the basis of the combination of inputs which are present at the
selection line S0, one of these 2 inputs will be connected to the output. The block
diagram and the truth table of the 2×1 multiplexer are given below.
Block Diagram:
Truth Table:
The logical expression of the term Y is as follows:
Y=S0'.A0+S0.A1
Logical circuit of the above expression is given below:

4×1 Multiplexer:
In the 4×1 multiplexer, there is a total of four inputs, i.e., A 0, A1, A2, and A3, 2 selection
lines, i.e., S0 and S1 and single output, i.e., Y. On the basis of the combination of inputs
that are present at the selection lines S 0 and S1, one of these 4 inputs are connected to
the output. The block diagram and the truth table of the 4×1 multiplexer are given
below.
Block Diagram:
Truth Table:
Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3
8 to 1 Multiplexer
In the 8 to 1 multiplexer, there are total eight inputs, i.e., A 0, A1, A2, A3, A4, A5, A6, and A7,
3 selection lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of the
combination of inputs that are present at the selection lines S 0, S1, and S2, one of these 8
inputs are connected to the output. The block diagram and the truth table of the 8 ×1
multiplexer are given below.
Block Diagram:
Truth Table:
Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.S2 .A6+S
0.S1.S3.A7
8 ×1 multiplexer using 4×1 and 2×1 multiplexer

We can implement the 8×1 multiplexer using a lower order multiplexer. To implement
the 8×1 multiplexer, we need two 4×1 multiplexers and one 2×1 multiplexer. The 4×1
multiplexer has 2 selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has only 1
selection line.
For getting 8 data inputs, we need two 4×1 multiplexers. The 4×1 multiplexer produces
one output. So, in order to get the final output, we need a 2×1 multiplexer. The block
diagram of 8×1 multiplexer using 4×1 and 2×1 multiplexer is given below.
16 to 1 Multiplexer
In the 16 to 1 multiplexer, there are total of 16 inputs, i.e., A 0, A1, …, A16, 4 selection lines,
i.e., S0, S1, S2, and S3 and single output, i.e., Y. On the basis of the combination of inputs
that are present at the selection lines S 0, S1, and S2, one of these 16 inputs will be
connected to the output. The block diagram and the truth table of the 16×1
Block Diagram:
Truth Table:
Y=A0.S0'.S1'.S2'.S3'+A1.S0'.S1'.S2 '.S3+A2.S0'.S1'.S2.S3'+A3.S0'.S1 '.S2.S3+A4.S0'.S1.S2'.S3'+A5.S0 '.
S1.S2'.S3+A6.S1.S2.S3'+A7.S0 '.S1.S2.S3+A8.S0.S1'.S2'.S3'+A9 .S0.S1'.S2'.S3+Y10.S0.S1'.S2.S3 '+A11.S
0 .S1'.S2.S3+A12 S0.S1.S2 '.S3'+A13.S0.S1.S2'.S3+A14.S0.S1 .S2.S3'+A15.S0.S1.S2'.S3

16×1 multiplexer using 8×1 and 2×1 multiplexer
We can implement the 16×1 multiplexer using a lower order multiplexer. To implement
the 8×1 multiplexer, we need two 8×1 multiplexers and one 2×1 multiplexer. The 8×1
multiplexer has 3 selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has only 1
selection line.
For getting 16 data inputs, we need two 8 ×1 multiplexers. The 8×1 multiplexer
produces one output. So, in order to get the final output, we need a 2×1 multiplexer.
The block diagram of 16×1 multiplexer using 8×1 and 2×1 multiplexer is given below.
De-multiplexer
A De-multiplexer is a combinational circuit that has only 1 input line and 2 N output lines.
Simply, the multiplexer is a single-input and multi-output combinational circuit. The
information is received from the single input lines and directed to the output line. On
the basis of the values of the selection lines, the input will be connected to one of these
outputs. De-multiplexer is opposite to the multiplexer.
Unlike encoder and decoder, there are n selection lines and 2 n outputs. So, there is a
total of 2n possible combinations of inputs. De-multiplexer is also treated as De-mux.
There are various types of De-multiplexer which are as follows:
1×2 De-multiplexer:
In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y 0, and Y1, 1 selection lines,
i.e., S0, and single input, i.e., A. On the basis of the selection value, the input will be
connected to one of the outputs. The block diagram and the truth table of the 1×2
multiplexer are given below.
Block Diagram:
Truth Table:
Y0=S0'.A
Y1=S0.A
Logical circuit of the above expressions is given below:

1×4 De-multiplexer:
In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y 0, Y1, Y2, and Y3, 2 selection
lines, i.e., S0 and S1 and single input, i.e., A. On the basis of the combination of inputs
which are present at the selection lines S 0 and S1, the input be connected to one of the
outputs. The block diagram and the truth table of the 1×4 multiplexer are given below.
Block Diagram:
Truth Table:
Y0=S1' S0' A
y1=S1' S0 A
y2=S1 S0' A
y3=S1 S0 A

1×8 De-multiplexer
In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and
Y7, 3 selection lines, i.e., S0, S1and S2 and single input, i.e., A. On the basis of the
combination of inputs which are present at the selection lines S 0, S1 and S2, the input will
be connected to one of these outputs. The block diagram and the truth table of the 1×8
de-multiplexer are given below.
Block Diagram:
Truth Table:
Y0=S0'.S1'.S2'.A
Y1=S0.S1'.S2'.A
Y2=S0'.S1.S2'.A
Y3=S0.S1.S2'.A
Y4=S0'.S1'.S2 A
Y5=S0.S1'.S2 A
Y6=S0'.S1.S2 A
Y7=S0.S1.S3.A

1×8 De-multiplexer using 1×4 and 1×2 de-multiplexer
We can implement the 1×8 de-multiplexer using a lower order de-multiplexer. To
implement the 1×8 de-multiplexer, we need two 1×4 de-multiplexer and one 1×2 de-
multiplexer. The 1×4 multiplexer has 2 selection lines, 4 outputs, and 1 input. The 1×2
de-multiplexer has only 1 selection line.
For getting 8 data outputs, we need two 1×4 de-multiplexer. The 1×2 de-multiplexer
produces two outputs. So, in order to get the final output, we have to pass the outputs
of 1×2 de-multiplexer as an input of both the 1×4 de-multiplexer. The block diagram of
1×8 de-multiplexer using 1×4 and 1×2 de-multiplexer is given below.
1 x 16 De-multiplexer
In 1×16 de-multiplexer, there are total of 16 outputs, i.e., Y 0, Y1, …, Y16, 4 selection lines,
i.e., S0, S1, S2, and S3 and single input, i.e., A. On the basis of the combination of inputs
which are present at the selection lines S0, S1, and S2, the input will be connected to one
of these outputs. The block diagram and the truth table of the 1×16 de-multiplexer are
given below.
Block Diagram:
Truth Table:
Y0=A.S0'.S1'.S2'.S3'
Y1=A.S0'.S1'.S2'.S3
Y2=A.S0'.S1'.S2.S3'
Y3=A.S0'.S1'.S2.S3
Y4=A.S0'.S1.S2'.S3'
Y5=A.S0'.S1.S2'.S3
Y6=A.S0'.S1.S2.S3'
Y7=A.S0'.S1.S2.S3
Y8=A.S0.S1'.S2'.S3'
Y9=A.S0.S1'.S2'.S3
Y10=A.S0.S1'.S2.S3'
Y11=A.S0.S1'.S2.S3
Y12=A.S0.S1.S2'.S3'
Y13=A.S0.S1.S2'.S3
Y14=A.S0.S1.S2.S3'
Y15=A.S0.S1.S2'.S3
1×16 de-multiplexer using 1×8 and 1×2 de-multiplexer

We can implement the 1×16 de-multiplexer using a lower order de-multiplexer. To
implement the 1×16 de-multiplexer, we need two 1×8 de-multiplexer and one 1×2 de-
multiplexer. The 1×8 multiplexer has 3 selection lines, 1 input, and 8 outputs. The 1×2
de-multiplexer has only 1 selection line.
For getting 16 data outputs, we need two 1×8 de-multiplexer. The 1×8 de-multiplexer
produces eight outputs. So, in order to get the final output, we need a 1×2 de-
multiplexer to produce two outputs from a single input. Then we pass these outputs
into both the de-multiplexer as an input. The block diagram of 1×16 de-multiplexer
using 1×8 and 1×2 de-multiplexer is given below.
Encoders
The combinational circuits that change the binary information into N output lines are
known as Encoders. The binary information is passed in the form of 2 N input lines. The
output lines define the N-bit code for the binary information. In simple words,
the Encoder performs the reverse operation of the Decoder. At a time, only one input
line is activated for simplicity. The produced N-bit output code is equivalent to the
binary information.
There are various types of encoders which are as follows:
4 to 2 line Encoder:
In 4 to 2 line encoder, there are total of four inputs, i.e., Y 0, Y1, Y2, and Y3, and two
outputs, i.e., A0 and A1. In 4-input lines, one input-line is set to true at a time to get the
respective binary code in the output side. Below are the block diagram and the truth
table of the 4 to 2 line encoder.
Block Diagram:
Truth Table:
The logical expression of the term A0 and A1 is as follows:
A1=Y3+Y2
A0=Y3+Y1
8 to 3 line Encoder:
The 8 to 3 line Encoder is also known as Octal to Binary Encoder. In 8 to 3 line encoder,
there is a total of eight inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e.,
A0, A1, and A2. In 8-input lines, one input-line is set to true at a time to get the
respective binary code in the output side. Below are the block diagram and the truth
table of the 8 to 3 line encoder.
Block Diagram:
Truth Table:
The logical expression of the term A0, A1, and A2 are as follows:
A2=Y4+Y5+Y6+Y7
A1=Y2+Y3+Y6+Y7
A0=Y7+Y5+Y3+Y1

Decimal to BCD Encoder
The Octal to Binary Encoder is also known as 10 to 4 line Encoder. In 10 to 4 line
encoder, there are total of ten inputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, and Y9 and four
outputs, i.e., A0, A1, A2, and A3. In 10-input lines, one input-line is set to true at a time to
get the respective BCD code in the output side. The block diagram and the truth table
of the decimal to BCD encoder are given below.
Block Diagram:
Truth Table:
The logical expression of the term A0, A1, A2, and A3 is as follows:
A3 = Y9 + Y8
A2 = Y7 + Y6 + Y5 +Y4
A1 = Y7 + Y6 + Y3 +Y2
A0 = Y9 + Y7 +Y5 +Y3 + Y1
Priority Encoder:
4 to 2 line Priority Encoder:
In this priority encoder, there are total of 4 inputs, i.e., Y 0, Y1, Y2, and Y3, and two outputs,
i.e., A0 and A1. The Y3 has high and Y0 has low priority inputs. When more than one input
is '1' at the same time, the output will be the (binary) code corresponding to the higher
priority input. Below is the truth table of the 4 to 2 line priority encoder.
Truth Table:
The logical expression of the term A0 and A1 can be found using K-map as:
A1=Y3+Y2
A0=Y3+Y2'.Y1

Uses of Encoders:
1. These systems are very easy to use in all digital systems.

2. Encoders are used to convert a decimal number into the binary number. The objective is
to perform a binary operation such as addition, subtraction, multiplication, etc.
Decoder
The combinational circuit that change the binary information into 2 N output lines is
known as Decoders. The binary information is passed in the form of N input lines. The
output lines define the 2N-bit code for the binary information. In simple words,
the Decoder performs the reverse operation of the Encoder. At a time, only one input
line is activated for simplicity. The produced 2 N-bit output code is equivalent to the
binary information.
There are various types of decoders which are as follows:
2 to 4 line decoder:
In the 2 to 4 line decoder, there is a total of three inputs, i.e., A 0, and A1 and E and four
outputs, i.e., Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E' is set
to 1, one of these four outputs will be 1. The block diagram and the truth table of the 2
to 4 line decoder are given below.
Block Diagram:
Truth Table:
The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:
Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

3 to 8 line decoder:
The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line
decoder, there is a total of eight outputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three
outputs, i.e., A0, A1, and A2. This circuit has an enable input 'E'. Just like 2 to 4 line
decoder, when enable 'E' is set to 1, one of these four outputs will be 1. The block
diagram and the truth table of the 3 to 8 line encoder are given below.
Block Diagram:
Truth Table:
The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:
Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

4 to 16 line Decoder
In the 4 to 16 line decoder, there is a total of 16 outputs, i.e., Y 0, Y1, Y2,……, Y16 and four
inputs, i.e., A0, A1, A2, and A3. The 3 to 16 line decoder can be constructed using either 2
to 4 decoder or 3 to 8 decoder. There is the following formula used to find the required
number of lower-order decoders.
Required number of lower order decoders=m 2/m1
m1 = 8
m2 = 16
Required number of 3 to 8 decoders= =2
Block Diagram:
Truth Table:
The logical expression of the term A0, A1, A2,…, A15 are as follows:
Y0=A0'.A1'.A2'.A3'
Y1=A0'.A1'.A2'.A3
Y2=A0'.A1'.A2.A3'
Y3=A0'.A1'.A2.A3
Y4=A0'.A1.A2'.A3'
Y5=A0'.A1.A2'.A3
Y6=A0'.A1.A2.A3'
Y7=A0'.A1.A2.A3
Y8=A0.A1'.A2'.A3'
Y9=A0.A1'.A2'.A3
Y10=A0.A1'.A2.A3'
Y11=A0.A1'.A2.A3
Y12=A0.A1.A2'.A3'
Y13=A0.A1.A2'.A3
Y14=A0.A1.A2.A3'
Y15=A0.A1.A2'.A3

Half Adder
The Half-Adder is a basic building block of adding two numbers as two inputs and
produce out two outputs. The adder is used to perform OR operation of two single bit
binary numbers. The augent and addent bits are two input states, and 'carry'
and 'sum 'are two output states of the half adder.
Block diagram
Truth Table
In the above table,
1. 'A' and' B' are the input states, and 'sum' and 'carry' are the output states.
2. The carry output is 0 in case where both the inputs are not 1.
3. The least significant bit of the sum is defined by the 'sum' bit.
The SOP form of the sum and carry are as follows:
Sum = x'y+xy'
Carry = xy
Construction of Half Adder Circuit:
In the block diagram, we have seen that it contains two inputs and two outputs.
The augent and addent bits are the input states, and carry and sum are the output
states of the half adder. The half adder is designed with the help of the following two
logic gates:
1. 2-input AND Gate.

2. 2-input Exclusive-OR Gate or Ex-OR Gate

The Sum bit is generated with the help of the Exclusive-OR or Ex-OR Gate.
The above is the symbol of the EX-OR gate. In the above diagram, 'A' and 'B' are the
inputs, and the 'SUMOUT' is the final outcome after performing the XOR operation of
both numbers.
The truth table of the EX-OR gate is as follows:

From the above table, it is clear that the XOR gate gives the result 1 when both of the
inputs are different. When both of the inputs are the same, the XOR gives the result 0.
To learn more about the XOR gate, click here.
2. 2-input AND Gate:

The XOR gate is unable to generate the carry bit. For this purpose, we use another gate
called AND Gate. The AND gate gives the correct result of the carry.
The above is the symbol of the AND gate. In the above diagram, 'A' and 'B' are the
inputs, and 'OUT' is the final outcome after performing AND operation of both numbers.
There is the following truth table of AND Gate:
From the above table, it is clear that the AND gate gives the result 1 when both of the
inputs are 1. When both of the inputs are different and 0, the AND gates gives the result
0. To learn more about the AND gate, click here.
Half-Adder logical circuit:

So, the Half Adder is designed by combining the 'XOR' and 'AND' gates and provide the
sum and carry.
There is the following Boolean expression of Half Adder circuit:
Sum= A XOR B (A+B)
Carry= A AND B (A.B)
Full Adder
The half adder is used to add only two numbers. To overcome this problem, the full
adder was developed. The full adder is used to add three 1-bit binary numbers A, B, and
carry C. The full adder has three input states and two output states i.e., sum and carry.
Block diagram
Truth Table
In the above table,
1. 'A' and' B' are the input variables. These variables represent the two significant bits which
are going to be added
2. 'Cin' is the third input which represents the carry. From the previous lower significant
position, the carry bit is fetched.
3. The 'Sum' and 'Carry' are the output variables that define the output values.
4. The eight rows under the input variable designate all possible combinations of 0 and 1
that can occur in these variables.
.
The SOP form can be obtained with the help of K-map as:
Sum = x' y' z+x' yz+xy' z'+xyz

Carry = xy+xz+yz
Construction of Half Adder Circuit:
The above block diagram describes the construction of the Full adder circuit. In the
above circuit, there are two half adder circuits that are combined using the OR gate. The
first half adder has two single-bit binary inputs A and B. As we know that, the half adder
produces two outputs, i.e., Sum and Carry. The 'Sum' output of the first adder will be the
first input of the second half adder, and the 'Carry' output of the first adder will be the
second input of the second half adder. The second half adder will again provide 'Sum'
and 'Carry'. The final outcome of the Full adder circuit is the 'Sum' bit. In order to find
the final output of the 'Carry', we provide the 'Carry' output of the first and the second
adder into the OR gate. The outcome of the OR gate will be the final carry out of the full
adder circuit.
The MSB is represented by the final 'Carry' bit.
The full adder logic circuit can be constructed using the 'AND' and the 'XOR' gate with
an OR gate.
The actual logic circuit of the full adder is shown in the above diagram. The full adder
circuit construction can also be represented in a Boolean expression.
Sum:
o Perform the XOR operation of input A and B.

o Perform the XOR operation of the outcome with carry. So, the sum is (A XOR B) XOR
Cin which is also represented as:
(A ⊕ B) ⊕ Cin
Carry:
1. Perform the 'AND' operation of input A and B.

2. Perform the 'XOR' operation of input A and B.
3. Perform the 'OR' operations of both the outputs that come from the previous two steps.
So the 'Carry' can be represented as:
A.B + (A ⊕ B)
Half Subtractor
The half subtractor is also a building block for subtracting two binary numbers. It has
two inputs and two outputs. This circuit is used to subtract two single bit binary
numbers A and B. The 'diff' and 'borrow' are two output states of the half subtractor.
Block diagram
Truth Table
The SOP form of the Diff and Borrow is as follows:
Diff= A'B+AB'
Borrow = A'B
In the above table,
o 'A' and 'B' are the input variables whose values are going to be subtracted.
o The 'Diff' and 'Borrow' are the variables whose values define the subtraction result, i.e.,
difference and borrow.
o The first two rows and the last row, the difference is 1, but the 'Borrow' variable is 0.
o The third row is different from the remaining one. When we subtract the bit 1 from the
bit 0, the borrow bit is produced.
Construction of Half Subtractor Circuit

In the block diagram, we have seen that it contains two inputs and two outputs.
The carry and sum are the output states of the half subtractor. The half subtractor is
designed with the help of the following logic gates:
1. 2-input AND gate.

3. NOT or inverter Gate

The Diff bit is generated with the help of the Exclusive-OR or Ex-OR gate.
The above is the symbol of the EX-OR gate. In the above diagram, 'A' and 'B' are the
inputs, and 'Diff' is the final outcome after performing the XOR operation of both
numbers.
The truth table of the EX-OR gate is as follows:

From the above table, it is clear that the XOR gate gives the result 1 when both of the
inputs are different. When both of the inputs are the same, the XOR gives the result 0.
To learn more about the XOR gate, click here.
2. 2-input AND gate:

The XOR gate is unable to generate the carry bit. For this purpose, we use another gate
called AND gate. The AND gate is not enough to give the correct result of 'Borrow'. We
will use the NOT gate with the 'AND' gate to get the correct result.
The above is the symbol of the AND gate. In the above diagram, 'A' and 'B' are the
inputs, and 'OUT' is the final outcome after performing AND operation of both numbers.
There is the following truth table of AND gate:
From the above table, it is clear that the AND gate gives the result 1 when both of the
inputs are 1. When both of the inputs are different and 0, the AND gates gives the result
0. To learn more about the AND gate, click here.
3. NOT or Inverter Gate:

The NOT gate is used to get the inverse output. We can combine the 'AND' and 'NOT'
gates in order to get the combinational gate 'NAND'. By inverting the input 'A' using
'NOT' gate and then use the output of the 'NOT' gate as the input of the 'AND' gate, we
can get the 'Borrow' bit.
Half-Subtractor logical circuit

So, the Half Subtractor is designed by combining the 'XOR', 'AND', and 'NOT' gates and
provide the Diff and Borrow.
The Boolean expression of the Half Adder circuit is given below:
Diff= A XOR B (A⊕B)
Borrow= not-A AND B (A'.B)
Full Subtractor
The Half Subtractor is used to subtract only two numbers. To overcome this problem, a
full subtractor was designed. The full subtractor is used to subtract three 1-bit numbers
A, B, and C, which are minuend, subtrahend, and borrow, respectively. The full subtractor
has three input states and two output states i.e., diff and borrow.
Block diagram
Truth Table
In the above table,

o 'A' and' B' are the input variables. These variables represent the two significant bits that
are going to be subtracted.
o 'Borrowin' is the third input which represents borrow.
o The 'Diff' and 'Borrow' are the output variables that define the output values.
o The eight rows under the input variable designate all possible combinations of 0 and 1
that can occur in these variables.
Note: We can simplify each of the Boolean output functions with the help of the
unique map method.
The SOP form can be obtained with the help of K-map as:
Diff=xy' z'+x' y' z+xyz+x'yz'

Borrow=x' z+x' y+yz
Construction of Full Subtractor Circuit:
The above block diagram describes the construction of the Full subtractor circuit.
In the above circuit, there are two half adder circuits that are combined using the OR
gate. The first half subtractor has two single-bit binary inputs A and B. As we know that,
the half subtractor produces two outputs, i.e., 'Diff' and 'Borrow'. The 'Diff' output of the
first subtractor will be the first input of the second half subtractor, and the 'Borrow'
output of the first subtractor will be the second input of the second half subtractor. The
second half subtractor will again provide 'Diff' and 'Borrow'. The final outcome of the
Full subtractor circuit is the 'Diff' bit. In order to find the final output of the 'Borrow', we
provide the 'Borrow' of the first and the second subtractor into the OR gate. The
outcome of the OR gate will be the final carry 'Borrow' of full subtractor circuit.
The MSB is represented by the final 'Borrow' bit.
The full subtractor logic circuit can be constructed using the 'AND', 'XOR', and NOT
gate with an OR gate.
The actual logic circuit of the full subtractor is shown in the above diagram. The full
subtractor circuit construction can also be represented in a Boolean expression.
Diff:
o Perform the XOR operation of input A and B.

o Perform the XOR operation of the outcome with 'Borrow'. So, the difference is (A XOR B)
XOR 'Borrowin' which is also represented as:
(A ⊕ B) ⊕ 'Borrowin'
Borrow:
o Perform the 'AND' operation of the inverted input A and B.

o Perform the 'XOR' operation of input A and B.
o Perform the 'OR' operations of both the outputs that come from the previous two steps.
So the 'Borrow' can be represented as:
A'.B + (A ⊕ B)
Basics of Flip Flop

A circuit that has two stable states is treated as a flip flop. These stable states are used
to store binary data that can be changed by applying varying inputs. The flip flops are
the fundamental building blocks of the digital system. Flip flops and latches are
examples of data storage elements. In the sequential logical circuit, the flip flop is the
basic storage element. The latches and flip flops are the basic storage elements but
different in working. There are the following types of flip flops:
SR Flip Flop
The S-R flip flop is the most common flip flop used in the digital system. In SR flip flop,
when the set input "S" is true, the output Y will be high, and Y' will be low. It is required
that the wiring of the circuit is maintained when the outputs are established. We
maintain the wiring until set or reset input goes high, or power is shutdown.
The S-R flip flop is the simplest and easiest circuit to understand.
Truth Table:
J-K Flip-flop
The JK flip flop is used to remove the drawback of the S-R flip flop, i.e., undefined states.
The JK flip flop is formed by doing modification in the SR flip flop. The S-R flip flop is
improved in order to construct the J-K flip flop. When S and R input is set to true, the SR
flip flop gives an inaccurate result. But in the case of JK flip flop, it gives the correct
output.
In J-K flip flop, if both of its inputs are different, the value of J at the next clock edge is
taken by the output Y. If both of its input is low, then no change occurs, and if high at
the clock edge, then from one state to the other, the output will be toggled. The JK Flip
Flop is a Set or Reset Flip flop in the digital system.
Truth Table:
D Flip Flop
D flip flop is a widely used flip flop in digital systems. The D flip flop is mostly used in
shift-registers, counters, and input synchronization.
Truth Table:
T Flip Flop
Just like JK flip-flop, T flip flop is used. Unlike JK flip flop, in T flip flop, there is only
single input with the clock input. The T flip flop is constructed by connecting both of the
inputs of JK flip flop together as a single input.
The T flip flop is also known as Toggle flip-flop. These T flip-flops are able to find the
complement of its state.
Truth Table:
SR Flip Flop
The SR flip flop is a 1-bit memory bistable device having two inputs, i.e., SET and RESET.
The SET input 'S' set the device or produce the output 1, and the RESET input 'R' reset
the device or produce the output 0. The SET and RESET inputs are labeled as S and R,
respectively.
The SR flip flop stands for "Set-Reset" flip flop. The reset input is used to get back the
flip flop to its original state from the current state with an output 'Q'. This output
depends on the set and reset conditions, which is either at the logic level "0" or "1".
The NAND gate SR flip flop is a basic flip flop which provides feedback from both of its
outputs back to its opposing input. This circuit is used to store the single data bit in the
memory circuit. So, the SR flip flop has a total of three inputs, i.e., 'S' and 'R', and current
output 'Q'. This output 'Q' is related to the current history or state. The term "flip-flop"
relates to the actual operation of the device, as it can be "flipped" to a logic set state or
"flopped" back to the opposing logic reset state.
The NAND Gate SR Flip-Flop

We can implement the set-reset flip flop by connecting two cross-coupled 2-input
NAND gates together. In the SR flip flop circuit, from each output to one of the other
NAND gate inputs, feedback is connected. So, the device has two inputs, i.e., Set 'S' and
Reset 'R' with two outputs Q and Q' respectively. Below are the block diagram and
circuit diagram of the S-R flip flop.
Block Diagram:
Circuit Diagram:
The Set State
In the above diagram, when the input R is set to false or 0 and the input S is set to true
or 1, the NAND gate Y has an input 0, which will produce the output Q' 1. The value of
Q' is faded to the NAND gate 'X' as input 'A', and now both the inputs of the NAND
gate 'X' are 1(S=A=1), which will produce the output 'Q' 0.
Now, if the input R is changed to 1 with 'S' remaining 1, the inputs of NAND gate 'Y' is
R=1 and B=0. Here, one of the inputs is also 0, so the output of Q' is 1. So, the flip flop
circuit is set or latched with Q=0 and Q'=1.
Reset State
The output Q' is 0, and output Q is 1 in the second stable state. It is given by R =1 and S
= 0. One of the inputs of NAND gate 'X' is 0, and its output Q is 1. Output Q is faded to
NAND gate Y as input B. So, both the inputs to NAND gate Y are set to 1, therefore, Q'
= 0.
Now, if the input S is changed to 0 with 'R' remaining 1, the output Q' will be 0 and
there is no change in state. So, the reset state of the flip flop circuit has been latched,
and the set/reset actions are defined in the following truth table:
From the above truth table, we can see that when set 'S' and reset 'R' inputs are set to 1,
the outputs Q and Q' will be either 1 or 0. These outputs depend on the input state S or
R before the input condition exist. So, when the inputs are 1, the states of the outputs
remain unchanged.
The condition in which both the inputs states are set to 0 is treated as invalid and must
be avoided.
JK Flip Flop
The SR Flip Flop or Set-Reset flip flop has lots of advantages. But, it has the following
switching problems:
o When Set 'S' and Reset 'R' inputs are set to 0, this condition is always avoided.
o When the Set or Reset input changes their state while the enable input is 1, the incorrect
latching action occurs.
The JK Flip Flop removes these two drawbacks of SR Flip Flop.
The JK flip flop is one of the most used flip flops in digital circuits. The JK flip flop is a
universal flip flop having two inputs 'J' and 'K'. In SR flip flop, the 'S' and 'R' are the
shortened abbreviated letters for Set and Reset, but J and K are not. The J and K are
themselves autonomous letters which are chosen to distinguish the flip flop design from
other types.
The JK flip flop work in the same way as the SR flip flop work. The JK flip flop has 'J' and
'K' flip flop instead of 'S' and 'R'. The only difference between JK flip flop and SR flip flop
is that when both inputs of SR flip flop is set to 1, the circuit produces the invalid states
as outputs, but in case of JK flip flop, there are no invalid states even if both 'J' and 'K'
flip flops are set to 1.
The JK Flip Flop is a gated SR flip-flop having the addition of a clock input circuitry. The
invalid or illegal output condition occurs when both of the inputs are set to 1 and are
prevented by the addition of a clock input circuit. So, the JK flip-flop has four possible
input combinations, i.e., 1, 0, "no change" and "toggle". The symbol of JK flip flop is the
same as SR Bistable Latch except for the addition of a clock input.
Block Diagram:
Circuit Diagram:
In SR flip flop, both the inputs 'S' and 'R' are replaced by two inputs J and K. It means
the J and K input equates to S and R, respectively.
The two 2-input AND gates are replaced by two 3-input NAND gates. The third input of
each gate is connected to the outputs at Q and Q'. The cross-coupling of the SR flip-flop
permits the previous invalid condition of (S = "1", R = "1") to be used to produce the
"toggle action" as the two inputs are now interlocked.
If the circuit is "set", the J input is interrupted from the "0" position of Q' through the
lower NAND gate. If the circuit is "RESET", K input is interrupted from 0 positions of Q
through the upper NAND gate. Since Q and Q' are always different, we can use them to
control the input. When both inputs 'J' and 'K' are set to 1, the JK toggles the flip flop as
per the given truth table.
Truth Table:
When both of the inputs of JK flip flop are set to 1 and clock input is also pulse "High"
then from the SET state to a RESET state, the circuit will be toggled. The JK flip flop work
as a T-type toggle flip flop when both of its inputs are set to 1.
The JK flip flop is an improved clocked SR flip flop. But it still suffers from
the "race" problem. This problem occurs when the state of the output Q is changed
before the clock input's timing pulse has time to go "Off". We have to keep short
timing plus period (T) for avoiding this period.
D Flip Flop
In SR NAND Gate Bistable circuit, the undefined input condition of SET = "0" and
RESET = "0" is forbidden. It is the drawback of the SR flip flop. This state:
1. Override the feedback latching action.
2. Force both outputs to be 1.
3. Lose the control by the input, which first goes to 1, and the other input remains "0" by
which the resulting state of the latch is controlled.
We need an inverter to prevent this from happening. We connect the inverter between
the Set and Reset inputs for producing another type of flip flop circuit called D flip flop,
Delay flip flop, D-type Bistable, D-type flip flop.
The D flip flop is the most important flip flop from other clocked types. It ensures that at
the same time, both the inputs, i.e., S and R, are never equal to 1. The Delay flip-flop is
designed using a gated SR flip-flop with an inverter connected between the inputs
allowing for a single input D(Data).
This single data input, which is labeled as "D" used in place of the "Set" input and for the
complementary "Reset" input, the inverter is used. Thus, the level-sensitive D-type or D
flip flop is constructed from a level-sensitive SR flip flop.
So, here S=D and R= ~D(complement of D)
Block Diagram
Circuit Diagram
We know that the SR flip-flop requires two inputs, i.e., one to "SET" the output and
another to "RESET" the output. By using an inverter, we can set and reset the outputs
with only one input as now the two input signals complement each other. In SR flip flop,
when both the inputs are 0, that state is no longer possible. It is an ambiguity that is
removed by the complement in D-flip flop.
In D flip flop, the single input "D" is referred to as the "Data" input. When the data input
is set to 1, the flip flop would be set, and when it is set to 0, the flip flop would change
and become reset. However, this would be pointless since the output of the flip flop
would always change on every pulse applied to this data input.
The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data input from
the flip flop's latching circuitry. When the clock input is set to true, the D input condition
is only copied to the output Q. This forms the basis of another sequential device
referred to as D Flip Flop.
When the clock input is set to 1, the "set" and "reset" inputs of the flip-flop are both set
to 1. So it will not change the state and store the data present on its output before the
clock transition occurred. In simple words, the output is "latched" at either 0 or 1.
Truth Table for the D-type Flip Flop

Symbols ↓ and ↑ indicates the direction of the clock pulse. D-type flip flop assumed
these symbols as edge-triggers.
T Flip Flop
In T flip flop, "T" defines the term "Toggle". In SR Flip Flop, we provide only a single
input called "Toggle" or "Trigger" input to avoid an intermediate state occurrence. Now,
this flip-flop work as a Toggle switch. The next output state is changed with the
complement of the present state output. This process is known as "Toggling"'.
We can construct the "T Flip Flop" by making changes in the "JK Flip Flop". The "T Flip
Flop" has only one input, which is constructed by connecting the input of JK flip flop.
This single input is called T. In simple words, we can construct the "T Flip Flop" by
converting a "JK Flip Flop". Sometimes the "T Flip Flop" is referred to as single input "JK
Flip Flop".
Block diagram of the "T-Flip Flop" is given where T defines the "Toggle input", and CLK
defines the clock signal input.
T Flip Flop Circuit
There are the following two methods which are used to form the "T Flip Flop":
o By connecting the output feedback to the input in "SR Flips Flop".

o We pass the output that we get after performing the XOR operation of T and
QPREV output as the D input in D Flip Flop.
Construction
The "T Flip Flop" is designed by passing the AND gate's output as input to the NOR
gate of the "SR Flip Flop". The inputs of the "AND" gates, the present output state Q,
and its complement Q' are sent back to each AND gate. The toggle input is passed to
the AND gates as input. These gates are connected to the Clock (CLK) signal. In the "T
Flip Flop", a pulse train of narrow triggers are passed as the toggle input, which changes
the flip flop's output state. The circuit diagram of the "T Flip Flop" using "SR Flip Flop" is
given below:
The "T Flip Flop" is formed using the "D Flip Flop". In D flip - flop, the output after
performing the XOR operation of the T input with the output "Q PREV" is passed as the D
input. The logical circuit of the "T-Flip Flop" using the "D Flip Flop" is given below:
The simplest construction of a D Flip Flop is with JK Flip Flop. Both the inputs of the "JK
Flip Flop" are connected as a single input T. Below is the logical circuit of the T Flip Flop"
which is formed from the "JK Flip Flop":
Truth Table of T Flip Flop

The upper NAND gate is enabled, and the lower NAND gate is disabled when the
output Q To is set to 0. make the flip flop in "set state(Q=1)", the trigger passes the S
input in the flip flop.
The upper NAND gate is disabled, and the lower NAND gate is enabled when the
output Q is set to 1. The trigger passes the R input in the flip flop to make the flip flop in
the reset state(Q=0).
Operations of T-Flip Flop
The next sate of the T flip flop is similar to the current state when the T input is set to
false or 0.
o If toggle input is set to 0 and the present state is also 0, the next state will be 0.
o If toggle input is set to 0 and the present state is 1, the next state will be 1.
The next state of the flip flop is opposite to the current state when the toggle input is
set to 1.
The "T Flip Flop" is toggled when the set and reset inputs alternatively changed by the
incoming trigger. The "T Flip Flop" requires two triggers to complete a full cycle of the
output waveform. The frequency of the output produced by the "T Flip Flop" is half of
the input frequency. The "T Flip Flop" works as the "Frequency Divider Circuit."
In "T Flip Flop", the state at an applied trigger pulse is defined only when the previous
state is defined. It is the main drawback of the "T Flip Flop".
The "T flip flop" can be designed from "JK Flip Flop", "SR Flip Flop", and "D Flip Flop"
because the "T Flip Flop" is not available as ICs. The block diagram of "T Flip Flop" using
"JK Flip Flop" is given below:
Master-Slave JK Flip Flop
In "JK Flip Flop", when both the inputs and CLK set to 1 for a long time, then Q output
toggle until the CLK is 1. Thus, the uncertain or unreliable output produces. This
problem is referred to as a race-round condition in JK flip-flop and avoided by ensuring
that the CLK set to 1 only for a very short time.
Explanation
The master-slave flip flop is constructed by combining two JK flip flops. These flip flops
are connected in a series configuration. In these two flip flops, the 1st flip flop work as
"master", called the master flip flop, and the 2nd work as a "slave", called slave flip flop.
The master-slave flip flop is designed in such a way that the output of the "master" flip
flop is passed to both the inputs of the "slave" flip flop. The output of the "slave" flip
flop is passed to inputs of the master flip flop.
In "master-slave flip flop", apart from these two flip flops, an inverter or NOT gate is also
used. For passing the inverted clock pulse to the "slave" flip flop, the inverter is
connected to the clock's pulse. In simple words, when CP set to false for "master", then
CP is set to true for "slave", and when CP set to true for "master", then CP is set to false
for "slave".
Working:
o When the clock pulse is true, the slave flip flop will be in the isolated state, and the
system's state may be affected by the J and K inputs. The "slave" remains isolated until
the CP is 1. When the CP set to 0, the master flip-flop passes the information to the slave
flip flop to obtain the output.
o The master flip flop responds first from the slave because the master flip flop is the
positive level trigger, and the slave flip flop is the negative level trigger.
o The output Q'=1 of the master flip flop is passed to the slave flip flop as an input K when
the input J set to 0 and K set to 1. The clock forces the slave flip flop to work as reset,
and then the slave copies the master flip flop.
o When J=1, and K=0, the output Q=1 is passed to the J input of the slave. The clock's
negative transition sets the slave and copies the master.
o The master flip flop toggles on the clock's positive transition when the inputs J and K set
to 1. At that time, the slave flip flop toggles on the clock's negative transition.
o The flip flop will be disabled, and Q remains unchanged when both the inputs of the JK
flip flop set to 0.
Timing Diagram of a Master Flip Flop:

o When the clock pulse set to 1, the output of the master flip flop will be one until the
clock input remains 0.
o When the clock pulse becomes high again, then the master's output is 0, which will be
set to 1 when the clock becomes one again.
o The master flip flop is operational when the clock pulse is 1. The slave's output remains 0
until the clock is not set to 0 because the slave flip flop is not operational.
o The slave flip flop is operational when the clock pulse is 0. The output of the master
remains one until the clock is not set to 0 again.
o Toggling occurs during the entire process because the output changes once in the cycle.
Registers
A Register is a collection of flip flops. A flip flop is used to store single bit digital data.
For storing a large number of bits, the storage capacity is increased by grouping more
than one flip flops. If we want to store an n-bit word, we have to use an n-bit register
containing n number of flip flops.
The register is used to perform different types of operations. For performing the
operations, the CPU use these registers. The faded inputs to the system will store into
the registers. The result returned by the system will store in the registers. There are the
following operations which are performed by the registers:
Fetch:
It is used
o To take the instructions given by the users.

o To fetch the instruction stored into the main memory.
Decode:
The decode operation is used to interpret the instructions. In decode, the operation
performed on the instructions is identified by the CPU. In simple words, the decode
operation is used to decode the instructions.
Execute:
The execution operation is used to store the result produced by the CPU into the
memory. After storing this result, it is displayed on the user screen.
Types of Registers
There are various types of registers which are as follows:
MAR or Memory Address Register
The MAR is a special type of register that contains the memory address of the data and
instruction. The main task of the MAR is to access instruction and data from memory in
the execution phase. The MAR stores the address of the memory location where the
data is to be read or to be stored by the CPU.
Program Counter
The program counter is also called an instruction address register or instruction pointer.
The next memory address of the instruction, which is going to be executed after
completing the execution of current instruction is contained in the program counter. In
simple words, the program counter contains the memory address of the location of the
next instruction.
Accumulator Register
The CPU mostly uses an accumulator register. The accumulator register is used to store
the system result. All the results will be stored in the accumulator register when the CPU
produces some results after processing.
MDR or Memory Data Register

Memory Data Register is a part of the computer's control unit. It contains the data that
we want to store in the computer storage or the data fetched from the computer
storage. The MDR works as a buffer that contains anything for which the processor is
ready to use it. The MDR contains the copied data of the memory for the processor.
Firstly the MDR holds the information, and then it goes to the decoder.
The data which is to be read out or written into the address location is contained in
the Memory Data Register.
The data is written in one direction when it is fetched from memory and placed into the
MDR. In write instruction, the data place into the MDR from another CPU register. This
CPU register writes the data into the memory. Half of the minimal interface between the
computer storage and the microprogram is the memory data address register, and the
other half is the memory data register.
Index Register
The Index Register is the hardware element that holds the number. The number adds
to the computer instruction's address to create an effective address. In CPU, the index
register is a processor register used to modify the operand address during the running
program.
Memory Buffer Register

Memory Buffer Register is mostly called MBR. The MBR contains the Metadata of the
data and instruction written in or read from memory. In simple words, it adds is used to
store the upcoming data/instruction from the memory and going to memory.
Data Register
The data register is used to temporarily store the data. This data transmits to or from a
peripheral device.
Shift Register
A group of flip flops which is used to store multiple bits of data and the data is moved
from one flip flop to another is known as Shift Register. The bits stored in registers
shifted when the clock pulse is applied within and inside or outside the registers. To
form an n-bit shift register, we have to connect n number of flip flops. So, the number of
bits of the binary number is directly proportional to the number of flip flops. The flip
flops are connected in such a way that the first flip flop's output becomes the input of
the other flip flop.
A Shift Register can shift the bits either to the left or to the right. A Shift Register,
which shifts the bit to the left, is known as "Shift left register", and it shifts the bit to
the right, known as "Right left register".
The shift register is classified into the following types:
o Serial In Serial Out

o Serial In Parallel Out
o Parallel In Serial Out
o Parallel In Parallel Out
o Bi-directional Shift Register
o Universal Shift Register
Serial IN Serial OUT

In "Serial Input Serial Output", the data is shifted "IN" or "OUT" serially. In SISO, a single
bit is shifted at a time in either right or left direction under clock control.
Initially, all the flip-flops are set in "reset" condition i.e. Y 3 = Y2 = Y1 = Y0 = 0. If we pass
the binary number 1111, the LSB bit of the number is applied first to the Din bit. The D3
input of the third flip flop, i.e., FF-3, is directly connected to the serial data input D3. The
output Y3 is passed to the data input d2 of the next flip flop. This process remains the
same for the remaining flip flops. The block diagram of the "Serial IN Serial OUT" is
given below.
Block Diagram:
Operation
When the clock signal application is disabled, the outputs Y 3 Y2 Y1 Y0 = 0000. The LSB bit
of the number is passed to the data input Din, i.e., D3. We will apply the clock, and this
time the value of D3 is 1. The first flip flop, i.e., FF-3, is set, and the word is stored in the
register at the first falling edge of the clock. Now, the stored word is 1000.
The next bit of the binary number, i.e., 1, is passed to the data input D 2. The second flip
flop, i.e., FF-2, is set, and the word is stored when the next negative edge of the clock
hits. The stored word is changed to 1100.
The next bit of the binary number, i.e., 1, is passed to the data input D 1, and the clock is
applied. The third flip flop, i.e., FF-1, is set, and the word is stored when the negative
edge of the clock hits again. The stored word is changed to 1110.
Similarly, the last bit of the binary number, i.e., 1, is passed to the data input D 0, and the
clock is applied. The last flip flop, i.e., FF-0, is set, and the word is stored when the
clock's negative edge arrives. The stored word is changed to 1111.
Truth Table
Waveforms
Serial IN Parallel OUT
In the "Serial IN Parallel OUT" shift register, the data is passed serially to the flip flop,
and outputs are fetched in a parallel way. The data is passed bit by bit in the register,
and the output remains disabled until the data is not passed to the data input. When
the data is passed to the register, the outputs are enabled, and the flip flops contain
their return value
Below is the block diagram of the 4-bit serial in the parallel-out shift register. The
circuit having four D flip-flops contains a clear and clock signal to reset these four flip
flops. In SIPO, the input of the second flip flop is the output of the first flip flop, and so
on. The same clock signal is applied to each flip flop since the flip flops synchronize
each other. The parallel outputs are used for communication.
Block Diagram
Parallel IN Serial OUT
In the "Parallel IN Serial OUT" register, the data is entered in a parallel way, and the
outcome comes serially. A four-bit "Parallel IN Serial OUT" register is designed below.
The input of the flip flop is the output of the previous Flip Flop. The input and outputs
are connected through the combinational circuit. Through this combinational circuit, the
binary input B0, B1, B2, B3 are passed. The shift mode and the load mode are the two
modes in which the "PISO" circuit works.
Load mode
The bits B0, B1, B2, and B3 are passed to the corresponding flip flops when the second,
fourth, and sixth "AND" gates are active. These gates are active when the shift or load
bar line set to 0. The binary inputs B0, B1, B2, and B3 will be loaded into the respective
flip-flops when the edge of the clock is low. Thus, parallel loading occurs.
Shift mode
The second, fourth, and sixth gates are inactive when the load and shift line set to 0. So,
we are not able to load data in a parallel way. At this time, the first, third, and fifth gates
will be activated, and the shifting of the data will be left to the right bit. In this way,
the "Parallel IN Serial OUT" operation occurs.
Block Diagram
Parallel IN Parallel OUT
In "Parallel IN Parallel OUT", the inputs and the outputs come in a parallel way in the
register. The inputs A0, A1, A2, and A3, are directly passed to the data inputs D0, D1, D2,
and D3 of the respective flip flop. The bits of the binary input is loaded to the flip flops
when the negative clock edge is applied. The clock pulse is required for loading all the
bits. At the output side, the loaded bits appear.
Block Diagram
Bidirectional Shift Register
The binary number after shifting each bit of the number to the left by one position will
be equivalent to the number produced by multiplying the original number by 2. In the
same way, the binary number after shifting each bit of the number to the right by one
position will be equivalent to the number produced by dividing the original number by
2.
For performing the multiplication and division operation using the shift register, it is
required that the data should be moved in both the direction, i.e., left or right in the
register. Such registers are called the "Bidirectional" shift register.
Below is the diagram of 4-bit "bidirectional" shift register where DR is the "serial right

shift data input", DL is the "left shift data input", and M is the "mode select input".
Block Diagram
Operations
1) Shift right operation(M=1)
o The first, third, fifth, and seventh AND gates will be enabled, but the second, fourth, sixth,
and eighth AND gates will be disabled.
o The data present on the data input DR is shifted bit by bit from the fourth flip flop to the
first flip flop when the clock pulse is applied. In this way, the shift right operation occurs.
2) Shift left operation(M=0)
o The second, fourth, sixth and eighth AND gates will be enabled, but the AND gates first,
third, fifth, and seventh will be disabled.
o The data present on the data input DR is shifted bit by bit from the first flip flop to the
fourth flip flop when the clock pulse is applied. In this way, the shift right operation
occurs.
Universal Shift Register
A register where the data is shifted in one direction is known as the "uni-
directional" shift register. A register in which the data is shifted in both the direction is
known as "bi-directional" shift register. A "Universal" shift register is a special type of
register that can load the data in a parallel way and shift that data in both directions, i.e.,
right and left.
The input M, i.e., the mode control input, is set to 1 to perform the parallel loading
operation. If this input set to 0, then the serial shifting operation is performed. If we
connect the mode control input with the ground, then the circuit will work as a "bi-
directional" register. The diagram of the universal shift register is given below. When
the input is passed to the serial input, the register performs the "serial left" operation.
When the input is passed to the input D, the register performs the serial right operation.
Block Diagram
Counters
A special type of sequential circuit used to count the pulse is known as a counter, or a
collection of flip flops where the clock signal is applied is known as counters.
The counter is one of the widest applications of the flip flop. Based on the clock pulse,
the output of the counter contains a predefined state. The number of the pulse can be
counted using the output of the counter.
Truth Table
There are the following types of counters:
o Asynchronous Counters
o Synchronous Counters
Asynchronous or ripple counters

The Asynchronous counter is also known as the ripple counter. Below is a diagram of
the 2-bit Asynchronous counter in which we used two T flip-flops. Apart from the T flip
flop, we can also use the JK flip flop by setting both of the inputs to 1 permanently. The
external clock pass to the clock input of the first flip flop, i.e., FF-A and its output, i.e., is
passed to clock input of the next flip flop, i.e., FF-B.
Block Diagram
Signal Diagram
Operation
1. Condition 1: When both the flip flops are in reset condition.

Operation: The outputs of both flip flops, i.e., QA QB, will be 0.
2. Condition 2: When the first negative clock edge passes.
Operation: The first flip flop will toggle, and the output of this flip flop will change from
0 to 1. The output of this flip flop will be taken by the clock input of the next flip flop.
This output will be taken as a positive edge clock by the second flip flop. This input will
not change the second flip flop's output state because it is the negative edge triggered
flip flop.
So, QA = 1 and QB = 0
3. Condition 3: When the second negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this flip flop will change
from 1 to 0. This output will be taken as a negative edge clock by the second flip flop.
This input will change the second flip flop's output state because it is the negative edge
triggered flip flop.
So, QA = 0 and QB = 1.
4. Condition 4: When the third negative clock edge is applied.
from 0 to 1. This output will be taken as a positive edge clock by the second flip flop.
This input will not change the second flip flop's output state because it is the negative
edge triggered flip flop.
5. Condition 5: When the fourth negative clock edge is applied.
from 1 to 0. This output will be taken as a negative edge clock by the second flip flop.
This input will change the output state of the second flip flop.
Synchronous counters
In the Asynchronous counter, the present counter's output passes to the input of the
next counter. So, the counters are connected like a chain. The drawback of this system is
that it creates the counting delay, and the propagation delay also occurs during the
counting stage. The synchronous counter is designed to remove this drawback.
In the synchronous counter, the same clock pulse is passed to the clock input of all the
flip flops. The clock signals produced by all the flip flops are the same as each other.
Below is the diagram of a 2-bit synchronous counter in which the inputs of the first flip
flop, i.e., FF-A, are set to 1. So, the first flip flop will work as a toggle flip-flop. The output
of the first flip flop is passed to both the inputs of the next JK flip flop.
Logical Diagram
Signal Diagram
Operation
1. Condition 1: When both the flip flops are in reset condition.

Operation: The outputs of both flip flops, i.e., Q A QB, will be 0.
2. Condition 2: When the first negative clock edge passes.
Operation: The first flip flop will be toggled, and the output of this flip flop will be
changed from 0 to 1. When the first negative clock edge is passed, the output of the first
flip flop will be 0. The clock input of the first flip flop and both of its inputs will set to 0.
In this way, the state of the second flip flop will remain the same.
3. Condition 2: When the second negative clock edge is passed.
Operation: The first flip flop will be toggled again, and the output of this flip flop will be
changed from 1 to 0. When the second negative clock edge is passed, the output of the
first flip flop will be 1. The clock input of the first flip flop and both of its inputs will set to
1. In this way, the state of the second flip flop will change from 0 to 1.
4. Condition 2: When the third negative clock edge passes.
Operation: The first flip flop will toggle from 0 to 1, but at this instance, both the inputs
and the clock input set to 0. Hence, the outputs will remain the same as before.
5. Condition 2: When the fourth negative clock edge passes.
Operation: The first flip flop will toggle from 1 to 0. At this instance, the inputs and the
clock input of the second flip flop set to 1. Hence, the outputs will change from 1 to 0.
In symbolic notation, it is used to describe the micro-operations transfer among

registers. It is a kind of intermediate representation (IR) that is very close to
assembly language, such as that which is used in a compiler.The term
“Register Transfer” can perform micro-operations and transfer the result of
operation to the same or other register.
Micro-operations :
The operation executed on the data store in registers are called micro-
operations. They are detailed low-level instructions used in some designs to
implement complex machine instructions.
Register Transfer :
The information transformed from one register to another register is
represented in symbolic form by replacement operator is called Register
Transfer.
Replacement Operator :
In the statement, R2 <- R1, <- acts as a replacement operator. This statement
defines the transfer of content of register R1 into register R2.
There are various methods of RTL –

1. General way of representing a register is by the name of the register
enclosed in a rectangular box as shown in (a).

2. Register is numbered in a sequence of 0 to (n-1) as shown in (b).

3. The numbering of bits in a register can be marked on the top of the
box as shown in (c).

4. A 16-bit register PC is divided into 2 parts- Bits (0 to 7) are assigned
with lower byte of 16-bit address and bits (8 to 15) are assigned with
higher bytes of 16-bit address as shown in (d).

Basic symbols of RTL :

Symbol Description Example
Letters and MAR, R1,

Numbers Denotes a Register R2
R1(8-bit)
R1(0-7)
() Denotes a part of register
<- Denotes a transfer of information R2 <- R1
R1 <- R2
R2 <- R1
, Specify two micro-operations of Register Transfer
P : R2 <- R1
if P=1
: Denotes conditional operations
Naming Operator Denotes another name for an already existing

(:=) register/alias Ra := R1
Register Transfer Operations:

The operation performed on the data stored in the registers are referred to as
register transfer operations.
There are different types of register transfer operations:
1. Simple Transfer – R2 <- R1
The content of R1 are copied into R2 without affecting the content of R1. It is
an unconditional type of transfer operation.
2. Conditional Transfer –
It indicates that if P=1, then the content of R1 is transferred to R2. It is a
unidirectional operation.
3. Simultaneous Operations –
If 2 or more operations are to occur simultaneously then they are separated
with comma (,).

If the control function P=1, then load the content of R1 into R2 and at the same
clock load the content of R2 into R1.
us structures in computer plays important role in connecting the internal

components of the computer. The bus in the computer is the shared
transmission medium. This means multiple components or devices use the same
bus structure to transmit the information signals to each other.
At a time only one pair of devices can use this bus to communicate with each
other successfully. If multiple devices transmit the information signal over the
bus at the same time the signals overlap each other and get jumbled.
Bus Structure in Computer Architecture

A system bus has typically from fifty to hundreds of distinct lines where each
line is meant for a certain function. These lines can be categories into three
functional groups i.e., data lines, address lines, and control lines. Let us discuss
them one by one each.
1. Data Lines
Data lines coordinate in transferring the data among the system components.
The data lines are collectively called data bus. A data bus may have 32 lines, 64
lines, 128 lines, or even more lines. The number of lines present in the data bus
defines the width of the data bus.
Each data line is able to transfer only one bit at a time. So the number of data
lines in a data bus determines how many bits it can transfer at a time. The
performance of the system also depends on the width of the data bus.
2. Address Lines
The content of the address lines of the bus determines the source or
destination of the data present on the data bus. The number of address lines
together is referred to as address bus. The number of address lines in the
address bus determines its width.
The width of the address bus determines the memory capacity of the system.
The content of address lines is also used for addressing I/O ports. The higher-
order bits determine the bus module and the lower ordered bits determine the
address of memory locations or I/O ports.
Whenever the processor has to read a word from the memory it simply places
the address of the corresponding word on the address line.
3. Control Lines
The address lines and data lines are shared by all the components of the
system so there must some means to control the use and access of data and
address lines. The control signals placed on the control lines control the use
and access to address and data lines of the bus. The control signal consists of
the command and timing information. Here the command in the control signal
specify the operation that has to be performed. And the timing information
over the control signals specify till when the data and address information is
valid .
The control lines include the lines for:
 Memory Write: This command causes the data on the data bus to be

placed over the addressed memory location.
 Memory Read: This command causes the data on the addressed memory
location to be placed on the data bus.
 I/O Write: The command over this control line causes the data on the
data bus to be placed over the addressed I/O port.
 I/O Read: The command over this control line causes the data from the
addressed I/O port to be placed over the data bus.
 Transfer ACK: This control line indicates the data has been received
from the data bus or is placed over the data bus.
 Bus Request: This control line indicates that the component has
requested control over the bus.
 Bus Grant: This control line indicates that the bus has been granted to
the requesting component.
 Interrupt Request: This control line indicates that interrupts are pending.
 Interrupt ACK: This control line provides acknowledgment when the
pending interrupt is serviced.
 Clock: This control line is used to synchronize the operations.
 Reset: The bit information issued over this control line initializes all the
modules.
If a component connected to the bus wishes to send data to another

connected component, it first has to acquire control over the bus, and then it
can transfer the data to another component over the bus. The same happen
when a component request data from another component.
During the transfer of data between two components, one component act as a
master and other act as a slave. The device initiating the data transfer is
referred to as master and usually, it is a processor, or sometimes it may be
some other device or component. The component addressed by the master
component is referred to as a slave.
Timing in Bus
As we have seen that the control lines of the bus also provide timing
information along with the command. Well, the way of deriving the timing
information over the control line can be categorized in two ways:
1. Synchronous Bus
With the synchronous bus scheme, all the devices or components connected
to the bus derive timing information over the control line referred to as
the bus clock. Over the bus clock line, the clock transmits an alternating
sequence of 1s and 0s at a regular interval. Here a single 1-0 transmission is
considered as a clock cycle or bus cycle.
All the devices or components connected to the bus can read this bus clock
line and all the events start at the starting the clock cycle. Here the
transmitting component and the receiving component are synchronized using
the clock. The data is sent or received at a constant rate and therefore used for
high-speed transmission.
2. Asynchronous Bus
In this asynchronous bus scheme, the transmitter and the receiver component
are not synchronized by the clock. Instead, the data transfer is controlled using
a handshake protocol between the master component and the slave
component.
Here, the component initiating the data transfer i.e. master component when
gets ready for data transfer indicates this by activating its master-ready line
and places the address and command information over the bus.
Then all the connected component decodes the address on the address line to
recognize which component is being addressed by the master component.
Now the addressed component performs the required operation and notifies
the processor by activation its slave ready-line. Once the master recognizes
the activated slave ready-line it removes its control over the bus.
In this way occurrence of one event on the bus is followed by and depends on
the occurrence of a previous event.
I/O Interface of Input Device Connected to Bus

In the section ahead we will discuss how these three things over the bus are
decoded by the I/O interface.
Each I/O device interface has a set of registers with unique addresses.
Whenever the processor puts an address over the address line of the bus, it is
examined by all the devices connected to the bus. Whichever device
recognizes this address responds to the control operations issued on the
control lines of the bus.
The processor issues read/write operation over the control lines of the bus
and the data corresponding to the read and write operation is transmitted over
the data lines of the bus. Consider that we have an input device keyboard and
some data from the keyboard has to be issued to the processor, the machine
instruction for the same is:
LOAD R2, DATAIN
Here the DATAIN is the data register of the Keyboard. This instruction reads
the content from DATAIN register of the keyboard and transfers the content
to the R2 register of the processor. Similarly, the instruction below:
STORE R2, DATAOUT
Here consider that the DATAOUT register is the data register of a display
device. So, this instruction will transfer the content of register R2 of the
processor to the data register of the display device.
The control register and the status register of the I/O device interface have
information relevant to the operation performed on or by the I/O device. The
address decoder, control circuitry and the registers of the I/O interface
coordinate in transferring the content to or from the I/O device.
Shift micro-operations
Shift micro-operations are those micro-operations that are used for serial
transfer of information. These are also used in conjunction with arithmetic
micro-operation, logic micro-operation, and other data-processing operations.
There are three types of shifts micro-operations:
1. Logical :
It transfers the 0 zero through the serial input. We use the symbols shl for
logical shift-left and shr for shift-right.
1. Logical Shift Left –
In this shift one position moves each bit to the left one by one. The
Empty least significant bit (LSB) is filled with zero (i.e, the serial input),
and the most significant bit (MSB) is rejected.
2. Right Logical Shift –
In this one position moves each bit to the right one by one and the
least significant bit(LSB) is rejected and the empty MSB is filled with
zero.
2. Arithmetic :
This micro-operation shifts a signed binary number to the left or to the right
position. In an arithmetic shift-left, it multiplies a signed binary number by 2 and
In an arithmetic shift-right, it divides the number by 2.
1. Left Arithmetic Shift –
In this one position moves each bit to the left one by one. The empty
least significant bit (LSB) is filled with zero and the most significant bit
(MSB) is rejected. Same as the Left Logical Shift.
2. Right Arithmetic Shift –
In this one position moves each bit to the right one by one and the
least significant bit is rejected and the empty MSB is filled with the
value of the previous MSB.
3. Circular :
The circular shift circulates the bits in the sequence of the register around the
both ends without any loss of information.
1. Left Circular Shift –
2. Right Circular Shift –
Arithmetic Micro-operations
In general, the Arithmetic Micro-operations deals with the operations performed on
numeric data stored in the registers.
The basic Arithmetic Micro-operations are classified in the following categories:
1. Addition
2. Subtraction
3. Increment
4. Decrement
5. Shift
Some additional Arithmetic Micro-operations are classified as:
1. Add with carry

2. Subtract with borrow
3. Transfer/Load, etc.
The following table shows the symbolic representation of various Arithmetic Micro-
operations.
Symbolic Representation Description
R3 ← R1 + R2 The contents of R1 plus R2 are transferred to R3.
R3 ← R1 - R2 The contents of R1 minus R2 are transferred to R3.
R2 ← R2' Complement the contents of R2 (1's complement)
R2 ← R2' + 1 2's complement the contents of R2 (negate)
R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2 (subtraction)
R1 ← R1 + 1 Increment the contents of R1 by one
R1 ← R1 - 1 Decrement the contents of R1 by one

Logic Gates

Uploaded by

Copyright:

Available Formats

Logic Gates

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Logic Gates

Uploaded by

Copyright:

Available Formats

Introduction to Basic Gates and Functions

Types of Basic Logic Gates

The truth table of a NAND gate is given as;

The truth table of a NOR gate is as follows;

Exclusive-OR gate (XOR Gate)

The truth table of an XOR gate is;

Exclusive-NOR Gate (XNOR Gate)

The Boolean expression of the XNOR gate

Conjunction or AND operation

Negation or Not operation

Operator Symbol Precedence

NOT ‘ (or) ¬ Highest

AND . (or) ∧ Middle

A conjunction B or A AND B, satisfies A ∧ B = True, if A = B = True or else A ∧ B = False.

A disjunction B or A OR B, satisfies A ∨ B = False, if A = B = False, else A ∨ B = True.

Negation A or ¬A satisfies ¬A = False, if A = True and ¬A = True if A = False

Boolean Algebra Terminologies

Literal: A literal may be a variable or a complement of a variable.

Boolean Algebra Truth Table

True True True True

True False False True

False False False False

Boolean Algebra Rules

The complement of a variable is represented by an overbar.

Laws of Boolean Algebra

Those six laws are explained in detail here.

Boolean Algebra Theorems

De Morgan’s First Law:

De Morgan’s First Law states that (A.B)’ = A’+B’.

The last two columns show that (A.B)’ = A’+B’.

Hence, De Morgan’s First Law is proved.

De Morgan’s Second Law:

De Morgan’s Second law states that (A+B)’ = A’. B’.

The last two columns show that (A+B)’ = A’. B’.

Hence, De Morgan’s second law is proved.

According to Demorgan’s law, we can write the above expressions as

From Commutative law:

From Complement law

Question 2: Draw a truth table for A(B+D).

Solution: Given expression A(B+D).

SOP & POS

Sum of Products (SOP):

Product of Sums (POS):

As the name suggests, it is formed by multiplying(AND operation) the sum terms.

A way of representing boolean A way of representing boolean

It is sum of minterms. Minterms are It is product of maxterms. Maxterms are

Introduction of K-Map (Karnaugh Map)

K-map SOP form for 3 variables

K-map 4 variable POS form

 The output of a Combinational Circuit depends entirely on the present input.

Feedback A Combinational Circuit The output of a Sequential Circuit, on

Complexity It is very less complex in This type of circuit is always more

There are the following characteristics of the combinational logic circuit:

There are various types of the multiplexer which are as follows:

The logical expression of the term Y is as follows:

Logical circuit of the above expression is given below:

Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

Logical circuit of the above expression is given below:

Logical circuit of the above expression is given below:

8 ×1 multiplexer using 4×1 and 2×1 multiplexer