ACPL-C87B, ACPL-C87A, ACPL-C870

Precision Optically Isolated Voltage Sensor

Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product

Description Features
The ACPL-C87B/C87A/C870 voltage sensors are optical  Advanced Sigma-Delta (Σ-Δ) Modulation Technology
isolation amplifiers designed specifically for voltage  Unity Gain 1 V/V, ±0.5% High Gain Accuracy (ACPL-C87B)
sensing. Its 2 V input range and high 1 GΩ input impe-
dance, makes it well suited for isolated voltage sensing  1 GΩ Input Impedence
requirements in electronic power converters applications  0 to 2 V Nominal Input Range
including motor drives and renewable energy systems.  -35 ppm/°C Low Gain Drift
In a typical voltage sensing implementation, a resistive
voltage divider is used to scale the DC-link voltage to suit  21 μV /°C Offset Voltage Drift
the input range of the voltage sensor. A differential output  0.1% Non-Linearity Max
voltage that is proportional to the input voltage is created  Active-High Shutdown Pin
on the other side of the optical isolation barrier.
 100 kHz Wide Bandwidth
For general applications, the ACPL-C87A (±1% gain
 3 V to 5.5 V Wide Supply Range for Output Side
tolerance) and the ACPL-C870 (±3% gain tolerance)
are recommended. For high precision requirements,  -40° C to +105° C Operating Temperature Range
the ACPL-C87B (±0.5% gain tolerance) can be used. The  15 kV/s Common-Mode Transient Immunity
ACPL-C87B/C87A/C870 family operates from a single 5 V
 Compact, Auto-Insertable Stretched SO-8 Package
supply and provides excellent linearity. An active-high
shutdown pin is available which reduces the IDD1 current  Safety and Regulatory Approvals:
to only 15 μA, making them suitable for battery-powered – IEC/EN/DIN EN 60747-5-5: 1414 Vpeak working
and other power-sensitive applications. insulation voltage
The high common-mode transient immunity (15 kV/s) – UL 1577: 5000 Vrms/1 min double protection rating
of the ACPL-C87B/C87A/C870 provides the precision and – CSA: Component Acceptance Notice #5
stability needed to accurately monitor DC-link voltage in
high noise environments. Combined with superior optical Applications
coupling technology, the ACPL-C87B/C87A/C870 imple-
ments sigma-delta (Σ-Δ) modulation, chopper stabilized  Isolated Voltage Sensing in AC and Servo Motor Drives
amplifiers, and differential outputs to provide unequaled  Isolated DC-Bus Voltage Sensing in Solar Inverters,
isolation-mode noise rejection, low offset, high gain Wind Turbine Inverters
accuracy and stability. This performance is delivered in a  Isolated Sensor Interfaces
compact, auto-insertable Stretched SO-8 (SSO-8) package
that meets worldwide regulatory safety standards.  Signal Isolation in Data Acquisition Systems
 General Purpose Voltage Isolation

CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Functional Diagram
Table 1. Pin Description
VDD1 1 8 VDD2
Pin No. Symbol Description
VIN 2 7 VOUT+
1 VDD1 Supply voltage for input side
(4.5 V to 5.5 V), relative to GND1
SHDN 3 6 VOUT–
2 VIN Voltage input
GND1 4 SHIELD 5 GND2 3 SHDN Shutdown pin (Active High)
4 GND1 Input side ground
Figure 1.
5 GND2 Output side ground
NOTE: A 0.1 μF bypass capacitor must be connected between pins 1 and
4 and between pins 5 and 8. 6 VOUT- Negative output
7 VOUT+ Positive output
8 VDD2 Supply voltage for output side
(3 V to 5.5 V), referenced to GND2

Ordering Information
ACPL-C87B/C87A/C870 is UL recognized with 5000 Vrms/1 minute rating per UL 1577.
Table 2.
Option Tape & IEC/EN/DIN EN
Part number (RoHS Compliant) Package Surface Mount Reel 60747-5-5 Quantity
ACPL-C87B -000E Stetched X X 80 per tube
ACPL-C87A -500E SO-8 X X X 1000 per reel
ACPL-C870

To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example:
ACPL-C87A-500E to order product of Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5
Safety Approval and RoHS compliance.
Contact your Avago sales representative or authorized distributor for information.

2
Package Outline Drawing
Stretched SO-8 Package (SSO-8)
RECOMMENDED LAND PATTERN

5.850 ± 0.254
(0.230 ± 0.010)
PART NUMBER
DATE CODE
8 7 6 5 12.650
(0.498)

C87B 6.807 ± 0.127

RoHS-COMPLIANCE YWW (0.268 ± 0.005)
INDICATOR EEE 1.905
(0.075)
1 2 3 4
0.64
(0.025) 1.590 ± 0.127
LOT ID (0.063 ± 0.005)
7°
0.450 45°
(0.018)
3.180 ± 0.127
(0.125 ± 0.005)

0.750 ± 0.250
0.200 ± 0.100 (0.0295 ± 0.010) 0.254 ± 0.100
0.381 ± 0.127 (0.010 ± 0.004)
(0.015 ± 0.005) (0.008 ± 0.004) 11.50 ± 0.250
1.270 (0.453 ± 0.010)
(0.050) BSG
Dimensions in millimeters and (inches).

Note:
Lead coplanarity = 0.1 mm (0.004 inches).
Figure 2. SSO-8 Package Floating lead protrusion = 0.25mm (10mils) max.

Recommended Pb-Free IR Profile

Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.

Regulatory Information
The ACPL-C87B/C87A/C870 is approved by the following organizations:
IEC/EN/DIN EN 60747-5-5
Approval with Maximum Working Insulation Voltage VIORM = 1414 Vpeak.
UL
Approval under UL 1577, component recognition program up to VISO = 5000 Vrms/1 min. File 55361.
CSA
Approval under CSA Component Acceptance Notice #5, File CA 88324

3
Table 3. Insulation and Safety Related Specifications
Parameter Symbol Value Unit Conditions
Minimum External Air Gap L(101) 8.0 mm Measured from input terminals to output terminals,
(External Clearance) shortest distance through air
Minimum External L(102) 8.0 mm Measured from input terminals to output terminals,
Tracking (External Creepage) shortest distance path along body
Minimum Internal Plastic Gap 0.5 mm Through insulation distance, conductor to conductor,
(Internal Clearance) usually the direct distance between the photoemitter
and photodetector inside the optocoupler cavity
Tracking Resistance CTI > 175 V DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking Index)
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Table 4. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics [1]

Description Symbol Value Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms I-IV
for rated mains voltage ≤ 300 Vrms I-IV
for rated mains voltage ≤ 450 V rms I-IV
for rated mains voltage ≤ 600 Vrms I-IV
for rated mains voltage ≤ 1000 Vrms I-III
Climatic Classification 55/105/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage (Pending Qualification) VIORM 1414 Vpeak
Input to Output Test Voltage, Method b VPR 2652 Vpeak
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC
Input to Output Test Voltage, Method a VPR 2262 Vpeak
VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage (Transient Overvoltage, tini = 60 sec) VIOTM 8000 Vpeak
Safety-limiting values (Maximum values allowed in the event of a failure)
Case Temperature TS 175 °C
Input Current [2] IS,INPUT 230 mA
Output Power [2] PS,OUTPUT 600 mW
Insulation Resistance at TS, VIO = 500 V RS ≥ 109 
Notes:
1. Insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the
application.

4
Table 5. Absolute Maximum Rating
Parameter Symbol Min. Max. Units
Storage Temperature TS -55 +125 °C
Ambient Operating Temperature TA -40 +105 °C
Supply Voltage VDD1, VDD2 -0.5 6.0 V
Steady-State Input Voltage [1, 3] VIN -2 VDD1 + 0.5 V
Two-Second Transient Input Voltage [2] VIN -6 VDD1 + 0.5 V
Logic Input VSD -0.5 VDD1 + 0.5 V
Output Voltages VOUT+, VOUT− -0.5 VDD2 + 0.5 V
Lead Solder Temperature 260° C for 10 sec., 1.6 mm below seating plane
Notes:
1. DC voltage of up to -2 V on the inputs does not cause latch-up or damage to the device.
2. Transient voltage of 2 seconds up to -6 V on the inputs does not cause latch-up or damage to the device.
3. Absolute maximum DC current on the inputs = 100 mA, no latch-up or device damage occurs.

Table 6. Recommended Operating Conditions

Parameter Symbol Min. Max. Units
Ambient Operating Temperature TA -40 +105 °C
VDD1 Supply Voltage VDD1 4.5 5.5 V
VDD2 Supply Voltage VDD2 3.0 5.5 V
Input Voltage Range[1] VIN 0 2.0 V
Shutdown Enable Voltage VSD VDD1 – 0.5 VDD1 V
Notes:
1. 2 V is the nominal input range. Full scale input range (FSR) is 2.46 V.

5
Table 7. Electrical Specifications
Unless otherwise noted, TA = -40° C to +105° C, VDD1 = 4.5 V to 5.5 V, VDD2 = 3.3 V to 5.5 V, VIN = 0 – 2 V, and VSD = 0 V.
Parameter Symbol Min. Typ.[1] Max. Unit Test Conditions/Notes Fig.
DC CHARACTERISTICS
Input Offset Voltage VOS -9.9 -0.3 9.9 mV TA = 25° C 3, 4
Magnitude of Input Offset |dVOS/dTA| 21 V/°C TA = –40° C to +105° C 5
Change vs. Temperature ; Direct short across inputs.
Gain (ACPL-C87B, ±0.5%) G0 0.995 1 1.005 V/V TA = 25° C; VDD2 = 5 V; 6, 7
Note 2.
0.994 0.999 1.004 V/V TA = 25° C; VDD2 = 3.3 V; 6, 7
Note 2.
Gain (ACPL-C87A, ±1%) G1 0.99 1 1.01 V/V TA = 25° C; Note 2. 6, 7
Gain (ACPL-C870, ±3%) G3 0.97 1 1.03 V/V TA = 25° C; Note 2. 6, 7
Magnitude of Gain Change dG/dTA -35 ppm/°C TA = -40° C to +105° C 8
vs. Temperature
Nonlinearity NL 0.05 0.1 % VIN = 0 to 2 V, TA = 25° C 9, 10
Magnitude of NL Change |dNL/dTA| 0.0002 %/°C TA = -40° C to +105° C 11
vs. Temperature
INPUTS AND OUTPUTS
Recommended Input Range VINR 2 V Referenced to GND1
Full-Scale Differential Voltage FSR 2.46 V Referenced to GND1
Input Range
Shutdown Logic Low VIL 0.8 TA = 25° C
Input Voltage
Shutdown Logic High VIH VDD – 0.5 5 TA = 25° C
Input Voltage
Input Bias Current IIN -0.1 -0.0015 A VIN = 0 V
Magnitude of IIN Change dIIN/dTA 1 nA/°C
vs. Temperature
Equivalent Input Impedance RIN 1000 M
Output Common-Mode VOCM 1.23 V VOUT+ or VOUT–
Voltage
Output Voltage Range VOUTR Vocm ± V VSD = 0 V. Note 4. 13
1.23
Output Short-Circuit Current |IOSC| 30 mA VOUT+ or VOUT–,
shorted to GND2 or VDD2
Output Resistance ROUT 36  VOUT+ or VOUT–

6
Table 7. Electrical Specifications (continued)
Unless otherwise noted, TA = -40° C to +105° C, VDD1 = 4.5 V to 5.5 V, VDD2 = 3.3 V to 5.5 V, VIN = 0 – 2 V, and VSD = 0 V.
Parameter Symbol Min. Typ.[1] Max. Unit Test Conditions/Notes Fig.
AC CHARACTERISTICS
Vout Noise Nout 0.013 mVrms Vin = 0 V; 12
Output low-pass filtered
to 180 KHz. Note 3.
Small-Signal Bandwidth (-3 dB) f–3 dB 70 100 kHz Guaranteed by design
Input to Output 50%-10% tPD10 2.2 3.0 s Step input. 18
Propagation Delay 50%-50% tPD50 3.7 5.5 s Step input. 18
50%-90% tPD90 5.3 6.5 s Step input. 18
Output Rise/Fall Time (10%-90%) tR/F 2.7 4.0 s Step input (tPD90 - tPD10)
Shutdown Delay tSD 25 40 s Vin = 2 V 17
Enable Delay tON 150 200 s
Common Mode Transient Immunity CMTI 10 15 kV/s VCM = 1 kV, TA = 25° C
Power Supply Rejection PSR -78 dB 1 Vpp 1 kHz sine wave
ripple on VDD1,
differential output
POWER SUPPLIES
Input Side Supply Current IDD1 10.5 15 mA VSD = 0 V
15 A VSD = 5 V
IDD2 6.5 12 mA 5 V supply
6.1 11 mA 3.3 V supply
Notes:
1. All Typical values are under Typical Operating Conditions at TA = 25° C, VDD1 = 5 V, VDD2 = 5 V.
2. Gain is defined as the slope of the best-fit line of differential output voltage (VOUT+ – VOUT-) versus input voltage over the nominal range, with offset
error adjusted.
3. Noise is measured at the output of the differential to single ended post amplifier.
4. When is VSD = 5 V or when shutdown is enabled, Vout+ is close to 0V and Vout- is at close to 2.46 V. This is similar to when VDD1 is not supplied.

Table 8. Package Characteristics

Parameter Symbol Min Typ Max Units Test Conditions Note
Input-Output Momentary VISO 5000 Vrms RH < 50%, t = 1 min., 1, 2
Withstand Voltage TA = 25° C
Resistance (Input-Output) RI-O > 1012  VI-O = 500 VDC 3
Capacitance (Input-Output) CI-O 0.5 pF f = 1 MHz 3
Notes:
1. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second (leakage detection
current limit, II-O ≤ 5 μA). This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-
5-5 Insulation Characteristic Table.
2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating, refer to the IEC/EN/DIN EN 60747-5-5 insulation characteristics table and your equipment level
safety specification.
3. This is a two-terminal measurement: pins 1–4 are shorted together and pins 5–8 are shorted together.

7
Typical Performance Plots
All ±3(sigma symbol) plots are based on characterization test result at the point of product release. For guaranteed
specification, refer to the respective Electrical Specifications section.
5 2
4 1.5
3
1
2
0.5
Offset (mV)

Offset (mV)
0 0
-1 -0.5
-2
-1
-3
-4 -1.5
-5 -2
4.5 5 5.5 3 3.5 4 4.5 5 5.5
Vdd1(V) Vdd2 (V)
Figure 3. Input Offset vs Supply VDD1 Figure 4. Input Offset vs Supply VDD2

10 1.003
M+3
8
Mean 1.002
6
M- 3
4 1.001
Offset (mV)

2
Gain (V/V)

0 1.000
-2
0.999
-4
-6 0.998
-8
- 10 0.997
-55 -35 -15 5 25 45 65 85 105 125 4.5 5 5.5
Temp (qC) Vdd1 (V)
Figure 5. Input Offset vs Temperature Figure 6. Gain vs Supply VDD1

1.003 1.00300

1.002 1.00200

1.001 1.00100
Gain (V/V)
Gain (V/V)

1.000 1.00000

0.999 0.99900

0.998 0.99800

0.997 0.99700
3 3.5 4 4.5 5 5.5 -55 -35 -15 5 25 45 65 85 105 125
Vdd2 (V) Temp (qC)
Figure 7. Gain vs Supply VDD2 Figure 8. Gain vs Temperature

8
 0.1 0.1

0.08 0.08

0.06 0.06
NL (%)

NL (%)
0.04 0.04

0.02 0.02

0 0
4.5 5 5.5 3 3.5 4 4.5 5 5.5
Vdd1 (V) Vdd2 (V)
Figure 9. Non-Linearity vs Supply VDD1 Figure 10. Non-Linearity vs Supply VDD2

0.1 17
0.09 15 Vin = 0 V
Vin = 1 V
0.08 13 Vin = 2 V
0.07
AC Noise (mVrms) 11
0.06
9
NL (%)

0.05
7
0.04
0.03 5
0.02 3
0.01 1
0 -1
-55 -35 -15 5 25 45 65 85 105 125 0 20 40 60 80 100 120 140 160
Temp (qC) Freq Filter (khz)
Figure 11. Non-Linearity vs Temperature Figure 12. AC noise vs Filter Freq vs Vin

3 1
VOUT+
2.5 VOUT– 0

-1
2
VOUT+, VOUT–

Gain (dB)

-2
1.5
-3
1
-4
0.5 -5

0 -6
0 0.5 1 1.5 2 2.5 3 1000 10000 100000
VIN Bandwidth (Hz)
Figure 13 VIN vs VOUT+, VOUT- Figure 14. Frequency Response

9
 200 6
180
160 5
140 4

Prog Delay (PS)

Phase (deg)

120
100 3
80
60 2
TPLH 50-10
40 1 TPLH 50-50
20 TPLH 50-90
0 0
1000 10000 100000 -55 -35 -15 5 25 45 65 85 105 125
Bandwidth (Hz) Temp (qC)

Figure 15. Phase Response Figure 16. Propagation Delay vs Temperature

5V
VSD 0V
2V
Vin tSD tON
0V
+2 V
VOut Diff 0V
-2.46 V

Figure 17. Shutdown And Wakeup Input To Output Timing Diagram. VOut Diff = VOut+ - VOut-

2V
VIN
0V
2V
VOut Diff
0V
TPLH50-10
TPLH50-50
TPLH50-90

Figure 18. Input to Output Propagation Delay Timing Diagram. VOut Diff = VOut+ - VOut-

10
Definitions Application Information
Gain Application Circuit
Gain is defined as the slope of the best-fit line of differen- The typical application circuit is shown in Figure 19.
tial output voltage (VOUT+ – VOUT-) over the nominal input The ACPL-C87X voltage sensor is often used in photo-
range, with offset error adjusted out. voltaic (PV) panel voltage measurement and tracking in
PV inverters, and DC bus voltage monitoring in motor
Nonlinearity drivers. The high voltage across rails needs to be scaled
Nonlinearity is defined as half of the peak-to-peak output down to fit the input range of the iso-amp by choosing R1
deviation from the best-fit gain line, expressed as a per- and R2 values according to appropriate ratio.
centage of the full-scale differential output voltage.
The ACPL-C87X senses the single-ended input signal
Common Mode Transient Immunity, CMTI, also known and produces differential outputs across the galvanic
isolation barrier. The differential outputs (Vout+, Vout-)
as Common Mode Rejection
can be connected to an op-amp to convert to a single-
CMTI is tested by applying an exponentially rising/falling ended signal or directly to two ADCs. The op-amp used in
voltage step on pin 4 (GND1) with respect to pin 5 (GND2). the external post-amplifier circuit should be of sufficiently
The rise time of the test waveform is set to approximately high precision so that it does not contribute a significant
50 ns. The amplitude of the step is adjusted until the dif- amount of offset or offset drift relative to the contribu-
ferential output (VOUT+ – VOUT-) exhibits more than a 200 tion from the isolation amplifier. Generally, op-amps with
mV deviation from the average output voltage for more bipolar input stages exhibit better offset performance
than 1μs. The ACPL-C87x will continue to function if more than op-amps with JFET or MOSFET input stages.
than 10 kV/μs common mode slopes are applied, as long
In addition, the op-amp should also have enough
as the breakdown voltage limitations are observed.
bandwidth and slew rate so that it does not adversely
Power Supply Rejection, PSR affect the response speed of the overall circuit. The post-
amplifier circuit includes a pair of capacitors (C4 and C5)
PSRR is the ratio of differential amplitude of the ripple
that form a single-pole low-pass filter; these capacitors
outputs over power supply ripple voltage, referred to the
allow the bandwidth of the post-amp to be adjusted in-
input, expressed in dB.
dependently of the gain and are useful for reducing the
output noise from the isolation amplifier.
The gain-setting resistors in the post-amp should have a
tolerance of 1% or better to ensure adequate CMRR and
adequate gain tolerance for the overall circuit. Resistor
networks can be used that have much better ratio toler-
ances than can be achieved using discrete resistors. A
resistor network also reduces the total number of compo-
nents for the circuit as well as the required board space.

C5
100 pF
L1

VDD1 U1 VDD2 R6 V+
1 VDD1 VDD2 8 10K, 1%
R1
R3
2 VIN VOUT+ 7 10K,1%
ACPL-C87X C3 R4 Vout
R2 3 SHDN VOUT- 6 100 nF 10K,1%
C1 C2 U2
10K 100 pF 100 nF OPA237
4 GND1 GND2 5

V-
GND1 GND2 R5
C4
100 pF 10K, 1%
L2

GND2
Figure 19. Typical application circuit.

11
Measurement Accuracy and Power Dissipation of the Resistive Divider
The input stage of the typical application circuit in Figure consumes about 12 mW, assuming VIN is set at 2 V. If the R2
19 can be simplified as the diagram shown in Figure 20. is reduced to 10 kΩ to reduce error to 0.001%, the power
R2 and RIN, input resistance of the ACPL-C87X, create a consumption will increase to about 120 mW. In energy
current divider that results in an additional measurement efficiency critical applications such as PV inverters and
error component that will add on to the tot on top of the battery-powered applications, this trade-off between
device gain error. With the assumption that R1 and RIN measurement accuracy and power dissipation in the
have a much higher value than R2, the resulting error can resistive string provides flexibility in design priority.
be estimated to be R2/RIN.
Isolated Temperature Sensing using Thermistor
With RIN of 1 GΩ for the ACPL-C87X, this additional mea-
surement error is negligible with R2 up to 1 MΩ, where the IGBTs are an integral part of a motor or servo drive system
error is approximately 0.1%. Though small, it can be further and because of the high power that they usually handle,
reduced by reducing the R2 to 100 kΩ (error of 0.01% it is essential that they have proper thermal management
approximately), or 10 kΩ (error of 0.001% approximately). and are sufficiently cooled. Long term overload conditions
However with lower R2, a drawback of higher power dis- could raise the IGBT module temperature permanently or
sipation in the resistive divider string needs to be consid- failure of the thermal management system could subject
ered, especially in higher voltage sensing applications. For the module to package overstress and lead to catastrophic
example, with 600 V DC across L1 and L2 and R2 of 100 kΩ failures. One common way to monitor the temperature
for 0.01% measurement error, the resistive divider string of the module is through using a NTC type thermistor
mounted onto the IGBT module. Some IGBT module man-
ufacturers also have IGBTs that comes with the thermistor
integrated inside the module. In some cases, it is necessary
to isolate this thermistor to provide added isolation and
insulation due to the high power nature of the IGBTs. The
R1 ACPL-C87x voltage sensor can be used to easily meet
RIN such a requirement, while providing good accuracy and
non-linearity. Figure. 21 shows an example of such an
implementation. The ACPL-C87x is used to isolate the
+
thermistor voltage which is later fed by the post amp
+–

R2
GND stage to an ADC onboard the microcontroller (MCU) to
determine the module temperature. The thermistor needs
to be biased in way that its voltage output will optimize
ACPL-C87x
the 2 V input range of the ACPL-C87x across the intended
Figure 20. Simplified Input Stage. temperature measurement range.

HV+

U
V Vdd
W

+
+–

GND

HV- Post ADC

ACPL-C87x Amp
NTC Thermistor
MCU
IGBT Module
Figure 21. Thermistor sensing in IGBT Module

12
Power Supplies and Bypassing
A power supply of 5 V is required to power the ACPL-C87x As shown in Figure 22, 100 nF bypass capacitors (C2, C3)
input side VDD1. In many motor drive DC bus voltage should be located as close as possible to the pins of the
sensing applications, this 5 V supply is most often obtained isolation amplifier. The bypass capacitors are required
from the same supply used to power the power transistor because of the high-speed digital nature of the signals
gate drive circuit using an inexpensive 78L05 three-ter- inside the isolation amplifier. A 100 pF bypass capacitor
minal regulator. To help attenuate high frequency power (Cin) is also recommended at the input pins due to the
supply noise or ripple, a resistor or inductor can be used switched-capacitor nature of the input circuit. The input
in series with the input of the regulator to form a low-pass bypass capacitor Cin also forms part of the anti-aliasing
filter with the regulator’s input bypass capacitor. filter, which is recommended to prevent high-frequency
noise from aliasing down to lower frequencies and inter-
In some other applications a dedicated supply might be
fering with the input signal. When R1 is far greater than R2,
required to supply the VDD1. These applications include
the low-pass anti-aliasing filter corner frequency can be
photovoltaic (PV) inverter voltage tracking and measure-
calculated by 1/(2πR2Cin). The input filter also performs
ment, temperature sensor signal isolation. In these cases
an important reliability function – it reduces transient
it is possible to add an additional winding on an existing
spikes from ESD events flowing through the high voltage
transformer. Otherwise, some sort of simple isolated
rails.
supply can be used, such as a line powered transformer or
a high-frequency DC-DC converter module.

HV+

R1
Floating
Positive Supply
IN OUT
78L05
5V
C1 C2
0.1μF 0.1μF
VDD1 VDD2

VIN VOUT+
Gate Drive
ACPL-C87A C3
Circuit Cin 0.1μF
R2 SHDN VOUT-
0.1nF
GND1 GND2
HV-

Figure 22. Recommended Power Supply and Bypassing

13
PC Board Layout
The design of the printed circuit board (PCB) should any stray coupling by maintaining the maximum possible
follow good layout practices, such as keeping bypass distance between the input and output sides of the circuit
capacitors close to the supply pins, keeping output signals and ensuring that any ground or power plane on the PC
away from input signals, the use of ground and power board does not pass directly below or extend much wider
planes, etc. In addition, the layout of the PCB can also than the body of the ACPL-C87A. The placement of the
affect the isolation transient immunity (CMTI) of the ACPL- input capacitor which forms part of the anti-aliasing filter
C87x, primarily due to stray capacitive coupling between together with the resistor network should also be placed
the input and the output circuits. To obtain optimal CMTI as close as possible to the Vin pin.
performance, the layout of the PC board should minimize

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AV02-3563EN - September 5, 2016
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ACPL-C870-000E ACPL-C87A-000E ACPL-C87B-500E