SUBJECT CODE : 310243

As per Revised Syllabus of

Savitribai Phule Pune University

Choice Based Credit System (CBCS)
T.E. (Computer) Semester - V

Systems Programming
and Operating System

Iresh A. Dhotre
M.E. (Information Technology)
Ex-Faculty, Sinhgad College of Engineering,
Pune
Anuradha A. Puntambekar
M.E. (Computer)
Formerly Assistant Professor in
P.E.S. Modern College of Engineering,
Pune

Rupesh G. Mahajan
M.E. (Computer)
Assistant Professor,
Dr. D. Y. Patil Institute of Technology, Pimpri,
Pune

® ®
TECHNICAL
PUBLICATIONS
SINCE 1993 An Up-Thrust for Knowledge

(i)
Systems Programming and Operating System

Subject Code : 310243

T.E. (Computer Engineering) Semester - V

ã Copyright with I. A. Dhotre and A. A. Puntambekar

All publishing rights (printed and ebook version) reserved with Technical Publications. No part of this book
should be reproduced in any form, Electronic, Mechanical, Photocopy or any information storage and
retrieval system without prior permission in writing, from Technical Publications, Pune.

Published by :
® ®
Amit Residency, Office No.1, 412, Shaniwar Peth,
TECHNICAL Pune - 411030, M.S. INDIA, Ph.: +91-020-24495496/97
PUBLICATIONS
SINCE 1993 An Up-Thrust for Knowledge Email : sales@technicalpublications.org Website : www.technicalpublications.org

Printer :
Yogiraj Printers & Binders
Sr.No. 10/1A,
Ghule Industrial Estate, Nanded Village Road,
Tal. - Haveli, Dist. - Pune - 411041.

ISBN 978-93-91567-04-0

SPPU 19
9 789391 567040

9789391567040 [1] (ii)

(iv)
(v)
 TM

TECHNICAL PUBLICATIONS - An up thrust for knowledge

 Application programs Highest level

High level languages

Operating systems

Assembly language

Machine language Lowest level

 Printer - 2

I/O Processor - 1

Disk
I/O Processor - 2
Memory

Printer - 1
CPU - 1

CPU - 2
Other I/O 0
channel
Memory
controller 1
Input/Output
channel 2
Memory address
register

Memory buffer
register

Other
CPU

Location counter
Working
registers
Data
Instruction register Instruction

General
registers

Instruction
interpreter

Central processing unit

Operation Register Memory
code (op) number (reg) location (addr)
 Arg Index
Opcode (8 bits) register register Address (24 bits)
(4 bits) (4 bits)

Arg Index
Opcode (8 bits) register register Base (4 bits) Offset (12 bits)
(4 bits) (4 bits)
 Sign
bit

0 1 15

Sign
Integer
bit

0 1 31

Decimal Decimal Decimal Sign

1 to 16 bytes
digit (4 bits) digit (4 bits) digit (4 bits) (4 bits)

Zone code Decimal Zone code Decimal Variable Sign Decimal

(4 bits) digit (4 bits) (4 bits) digit (4 bits) bits (4 bits) digit (4 bits)

Sign Characteristics Fraction

0 1 7 8 31

Sign Characteristics Fraction (Variable size)

0 1 7 8 63

Character codes Character codes 1 to 256 bytes Character codes

(8 bits) (8 bits) (variable size) (8 bits)
 RR
Operation code R1 R2
0 7 8 11 12 15
(R1 = Register operands 1 and R2 = Register operands 2)

RX
Operation code R1 X2 B2 D2
0 7 8 11 12 15 16 19 20 31
(R1 = Register operand 1, X2, B2 and D2 = Storage operand 2)

RS
Operation code R1 R3 B2 D2
0 7 8 11 12 15 16 19 20 31
(R1 = Register operand 1, R3 = Register operand 3, B2 and D2 = Storage operand 2)
SI
Operation code I2 B1 D1
0 7 8 15 16 19 20 31
(I2 = Immediate operand 2, B1 and D1 = Storage operand 1)

SS
Operation code Length B1 D1 B2 D2
0 7 8 15 16 19 20 31 32 35 36 47
(B1, D1 = Storage operand 1, B2 and D2 = Storage operand 2)
 Computer users

Program Removing Package

compilation error executing

System software

Computer hardware
 Users

Editor Loader Word Application software

System
software

Operating system

Hardware interface

Hardware
 Source
program

Assembler

Object
code

Linker

Executable
code

Loader
Source Target
Compiler
program program
 Interpreter
Source Intermediate
code code

Preprocessing Processing
User application 1 User application 2 User application 3

System call interface

System System
calls calls

Device Device
calls calls

Device controller or bus controller

Device controller

Device 1 Device 2 Device 3

 User

Kernel

Device driver

Computer hardware
 User process

/dev/xxx
User space

Kernel space
Device driver

Physical device
 Assembler Object Linker
Source code
program

Executable
code

Loader
Sign Opcode Register Main memory operand
operand
 Label Opcode Operands ; Comments

Optional Mandatory
 Source
program

Analysis
phase

Mnemonics Table Symbol table

Mnemonics Opcode Length Symbol Address
Transfer
Control
Da

a
ss

ac e
t

ces cc
s Synthesis Data a
phase

Target
program
 Source program

Pass 1
Control transfer

Data Intermediate
structure code

ta
Da ess
c
ac
Pass II

Target program


 Pass 2 Pass 1 Pass 2
Pass 1
Wastage of
memory Data structures Data structures

Data structures Data structures Work area Work area

Work area Work area

(a) Variant I (b) Variant II

  

 

 
 

 

 
 Source
program
(user)

Pass I

Opcode
table
Source
program
Symbol
table

Intermediate
Literal code
table

Pass II

Program Required
listing target
program
Flowchart for Pass 1
Start

Pass 1

Initialize LC

END
Read card DS EQU USING
DC
DROP
Adjust LC Calculate operand
field
Search
Yes
Pseudo-op table Assign storage
Assign value to locations to
No L = Length of symbol in label literals
data field field
Search
Machine-op table Reset
copy file

L = Length
Go to
Pass 2

Process literals

Symbol Yes
in label Assign current value
field of LC to symbol
?
N

LC = LC+L

Write copy of card

for Pass 2
Flowchart for Pass 2
START

Pass 2

Initialize LC

Read card
form file copy

Search Yes
pseudo-op table DS EQU DROP END
DC START USING
No Adjust LC Evaluate
to proper operand
Search
machine-op table alignment
Shows base
reg. number
Get op-code byte Form constant Enter base unavailable
and format code, DC DC and insert in
or reg. no. and
L = Length assembled value into
DS program base table
DS
Type of
instruction L = length
RR of data field
Printing listing
Evaluate both
register expressions
A
and insert into RX
2nd byte
Evaluate register and
index expressions
and insert into
''Punch''
2nd byte
assembled
instruction Generates literals
for entries in
Calculate effective Literal Table
Display address of operand
A assembly
listing line STOP
D+C (B) = EA

LC = LC+L
Put B&D into
bytes 3 and 4
 Program
Source Load-and-go
loaded
program assembler
in memory

Assembler

Object
Source Translator deck Object program
program (Assembler) or object Loader ready for
program execution

Memory
Symbol Value

LENGTH 100C

RDREC 2013 

THREE 1003

ZERO 1006

WRREC 201F 

EOF 100D

ENDFIL 201C 

RETADR 1009

BUFFER 100F

CLOOP 2012

FIRST 200F


Symbol Value

LENGTH 100C

RDREC 203D

THREE 1003

ZERO 1006

WRREC 201F 2031 

EOF 1000

ENDFIL 2024

RETADIR 1009

BUFFER 100F

CLOOP 2012

FIRST 200F

MAXLEN 203A

NPUT 2039

EXIT 2050 

RLOOP 2043
 TM

TECHNICAL PUBLICATIONS - An up thrust for knowledge

 Macro expansion

Lexical expansion Semantic expansion

 


 MACRO
 ADD1 & arg

 L 1, & arg

 A 1, = F '1'
 ST 1, & arg
 MEND


 MACRO
 ADDS & arg1, & arg2, arg3

 ADD1 & arg1

 ADD1 & arg2
 ADD1 & arg3
 MEND


 ARGTAB

1 F1

2 BUFFER

3 LENGTH







 Program
with macro Macro Target
preprocessor Assembler program
definitions
and calls

Program
without
macros
 Pass 1

R Read
End pseudo-op

Search Found others GO TO

Pseudo-op Table Type ? PASS 2
MACRO
Not
pseudo-op

Search Process macro Process

Macro Name Table definition pseudo-ops
Not

Search R R
Machine-op Table
Found, macro call

Process Set up marco

machine stack frame,etc.
instruction

R R
 Pass 1

MDTC = 1

MNTC = 1

Read next
source card

MACRO No Write copy of

pseudo-op source card
?

Yes End
No
pseudo-op
?
Read next
source card Yes

Go to
PASS 2
Enter macro name
and current value
of MDTC in MNT

Read next
source card
MNTC = MNTC+1

Substitute index
Prepare argument notation for
list array arguments

Enter macro name Enter line into

card into MDT MDT

MDTC = MDTC+1
MDTC = MDTC+1

Yes MEND No
pseudo-op
?
 Pass 2

Read next source

card

Search MNT for match

with operation code

Macro
No Write into expanded
name found
source card file
?

Yes End
No
pseudo-op
MDTP = MDT index ?
from MNT entry
Yes

Supply expanded
Set up argument source file to
list array assembler

MDTP = MDTP +1

Get line from

MDT

Substitute arguments
from macro call

Yes MEND No Write expanded

pseudo-op source card
?
 Input Output
Compiler
Source Target program
program

Compiler
Source Target
Analysis Synthesis
program program
 Lexical Analysis

id1 : = id2 + id3 * 2

Syntactical Analysis

:=

id1 +

id2 *

id3 2

Symantic Analysis

:=

id1 +

id2 *

int to float

Intermediate code generation

t1 : = id3 * 2
t2 : = id2 + t1
id1 : = t2

Code generation

MUL #2.0, R0
ADD R0, R1
MOV R1, id1
 

total +

count 

 rate 10






 
 
 Source
program

Lexical Analysis phase

analyzer

Syntax analyzer

Semantic
analyzer

Symbol table Intermediate Error detection

management code generator and handling

Synthesis
Code optimizer phase

Code generator

Target machine code

 Input processing in compiler Output

a = b+c  60

Lexical analyzer

id1 = id2+id3  60 Token stream

Syntax analyzer

id1 +
Syntax tree
id2 
id3 60

Semantic analyzer

id1 +
Semantic tree
id2 
id3 int to float

60
a
Intermediate code
b generator

c t1 : = inttofloat (60)
. t2 : = id3  t1
. Intermediate code
. t3 : = id2 + t2
id1: = t3
Symbol table
Code optimizer

t1 := id3  60.0
Optimized code
id1 : = id2 + t1

Code generator

MOVF id3, R2
MULF #60.0, R2
MOVF id2,R1 Machine code
ADDF R2, R1
MOVF R1, id1
 Data

Source Output
program
1. Symbol table 2. Data store 3. Data manipulation routine
Source program Result
Interpreter

Data
Source program Result
Preprocessor Interpreter

Intermediate Data
code
 TM

TECHNICAL PUBLICATIONS - An up thrust for knowledge

 Object
Source Translator deck Object program
program (Assembler) or object Loader ready for
program execution

Memory
 User Compile
Program for
program and go
execution
loader

Assembler

Main memory
Source Object
program Translator program 1

Executable object
Loader
code

Source Object
program Translator program 2

Loader
program

Main memory
Object program
for MAIN
1000
MAIN
Absolute 2000
loader
5000
SUM
Object program 7000
for SUM

Memory
 Object
Source Relocating program
Assembler
program loader + Inter segment
references
 32 bit

OP R1 X2 A2

8 4 4 16

This is an address of operand,

which is direct address instruction
Absolute Relative
address address
/*un-utilized space*/

100 0 BC 15, 148 /*declaration for FACT routine*/

104 4 BC 15, 226 /*declaration for ERR routine*/
108 8 ST 14,136
112 12 L 1, 140 /*load literal value which is stored
at address 140*/

116 16 BAL 14,100 /*Call routine FACT declared at

address 100 */
120 20 C 1, 144 /*Compare with the value 24(fact(4))
which is at address 144*/
124 24 BC 7,104 /*Transfer to ERR routine at address 104*/
128 28 L 14,136
132 32 BCR 15,14 /*return control to caller*/
134 34 /*un-utilized space*/
136 36 /*Temporary location*/
140 40 4 /*literal value*/
144 44 24 /*literal value*/
148 FACT /* FACT routine is loaded at address 148*/
.
.
.

226 ERR /* FACT routine is loaded at address 226*/

.
.
.
 48 28

relative Address of
Location TABLE is at 28 th byte
from beginning .
 ESD

Assembler TXT Loader

RLD

END
 S1 (16K)

S2 (14k) S3 (8k)

S4 (20k) S5 (12k) S6 (16k)

S7 (16k)

S8 (12k) S9 (18k)

S1
16
S2 S3
24 S4 S5 S6

30
36
40 Free
44 Space
S7

60

S8 S9
72
78
80
 Start

Read the card

Set variable CURLOC

to the address specified by
column 3-5 of
text card.

What
0 is the type 1
of
card?

Set variable LNG to the Transfer to

value specified location CURLOC
by column 2

Move LNG bytes of

text from
characters 8 - 72
to CURLOC
 Source program Translated program

MAIN START

USING *, 15 0 L 1, 99(0, 15)

Base register 15 L 1, TMPVAL
is used
...
...
TMPVAL DC F '10' 99 10

Full word END

constant
99 bytes away
from start.
Program 1
Program 2
 /*un-utilized space*/
104
. .
. .
. .
144 134 core addr + rel.add(PG1ENT2)
=104+30
=134
148 139 core addr +(Rel. addr(PG1ENT1)+15)
=104+(20+15)
=139

152 7 Rel. addr(PG1ENT2-PG1ENT1-3)

=30–20–3 =7
156 168 core addr of PG2
=168
160 232 Rel. addr(PG2ENT1+PG2-PG1ENT1+4)
(184+168–124+4)=232
164 /*un-utilized space*/
168
. .
. .
. .
192 134 core addr + rel.add(PG1ENT2)
=104+30=134
196 124 core addr + rel.add(PG1ENT1)
=104+20=124
200 7 Rel. addr(PG1ENT2-PG1ENT1-3)
=30–20–3 =7

Code loaded in the memory

 ID Core address(4 bytes)
1 104
2 124
3 134
4 168
. .
. .
. .
254 …
255 …

Maximum 255
entries are allowed.
 Copy of
object program

Program
Assembler / Object Pass I Pass II gets loaded
compiler deck / program of loader of loader here for
execution.

Global external
symbol table
Core memory
 Local
external
symbol
array (LESA)

Copy of
object deck

A
S
S
Program
E
Object deck loaded in
M Pass 1 Pass 2
memory
B
for execution
L
E
R Program
Printed load address
(PLA) Memory
load
map

Initial program
load address
Global
(IPLA)
external
symbol
Table
(GEST)

Loader
 PLA  IPLA

Read the object

deck card by card

Write copy of
card for pass 2

TXT / RLD
What
is the type LDT / EOF
Go to pass 2
END of card ?
PLA  PLA + SLENGTH

ESD

What
ER is the LD
type of
ESD

SD

VALUE  PLA VALUE  PLA + ADDR

SLENGTH  LENGTH

Is
No symbol entry Yes
in GEST ?

Store symbol Raise error

name and value "Duplicate symbol"
in GEST.

Print symbol name

and value for
load map
 Pass 2

PLA  IPLA

EXADDR  IPLA

Read the card

from copy of object deck

LDT / EOF Transfer to

Copy text to the TXT
location EXADDR
location PLA + ADDR What
is the type
ESD END
of card ?
RLD

ER Is
LD ESD ADDR Yes
type Search GEST specified?
? for symbol
EXADDR
SD PLA + ADDR
No
SLENGTH  LENGTH
PLA  PLA + SLENGTH

Is
Set
symbol
LESA (ID) = PLA Get VALUE from
present ?
LESA (ID)
No

Yes
What –
+ is
ERROR flag ?

SET ADD VALUE to Subtract VALUE

LESA (ID) = VALUE contents of location from contents of
PLA + ADDR location PLA + ADDR
 Compiled .OBJ Compiled time
file

LINKER

Stack DLL uses

DLL
Program's stack

time
run
Finished
program

Program's heap DLL heap

MEMORY
 TM

TECHNICAL PUBLICATIONS - An up thrust for knowledge

 Users

Editor Loader Word

System
software

Operating system

Hardware interface

Hardware

I/O controller 1 Keyboard

OS kernel I/O controller 2 Printer

User I/O controller 3 Mouse

area for I/O controller 4 Display
program
and data I/O controller 5 Disk
storage
Main memory
Processor Processor
#1 #2
Computer system
 Types of operating systems

Single user Multiuser Multitasking Multithreading Multiprocessing

Mobile Operating System Examples

Android Windows RIM iPhone

Linux Palm OS Symbian OS
OS mobile Blackberry OS
 Job1 Job2 Job3
Space for OS/Batch monitor
(Device driver, interrupt
processing, sequencing) Resident area

Space for user data and program Transient area

User 1

Job
User 2
Job Batch 1
Jobs
Computer
User 3 Job Jobs
Operator Batch 3 Computer

Job
User 4
Jobs Batch 2
b
Jo
User 5
Job

User 6
b
Jo

User 7
b
Jo

User 8
Operating system
kernel

Program 1

Program 2

Program 3

Free space

Program 4

Program 5

Free space
 Operating system
kernel
CPU

Program 1
ALU Performing I/O
Program 2 operation
(Blocking state)
Cache
Program 3
(Executing by CPU)
Waiting for CPU
Program 4 Hard disk
(Secondary storage device)
Un-allocated space
 Host
computer

Terminal Terminal Terminal

 Gateway

LAN
Internet

LAN
 Request Request
Client Client
Response Response

Server
Request
Client
Request
Response Client
Response
Peer Peer

Peer Peer
 Higher
Environment variables
address

Stack region 1
Stack
Start
pointer

End
Dynamic / heap region

Space for un-initialized data region

Space for initialized data region

Lower Code or text region

address
 Process identification

Priority number

Program counter

Memory allocation

I/O status information

List of open files

Accounting information

Number of registers

Process state

PID PCB

1 PCB

2 PCB

3 PCB

N–1 PCB

N PCB

Process table
New
state Interrupted Terminated
Admitted Exit state

Ready Running
state state

Scheduler dispatch

Event completion I/O or

or Input/Output event wait
completion Waiting
state
 New
admitted
activated dispatched

Ready, Ready Running

suspended suspended
interrupted
exit
Event Event
complete complete
suspended Event
wait Terminated
Blocked,
suspended Blocked

activated
 Heavy weight process

Thread
Register

Stack

Mask

Data
Address space and
Local global information
information
 letes
I/O comp

ing Blocked
Dispatch lock
I/O b
Start Run completes
New Ready Running Dead
Yield Sleep
Sleeping
Wa
it
Noti
fy
Tim
e slice Waiting
exp
ires

Thread library
User
space

Kernel
space Processor
 User
space

User threads

Kernel
space

Processor
User thread 1

User thread 2

User thread 3
Task 1

Task 2

Task 3

Thread
library

User space
Kernel space
Kernel Kernel Kernel
level level level
thread 1 thread 2 thread 3
User thread 1

User thread 2

User thread 3
Process A

Task 1

Task 3
Task 2
User space

Thread library
with scheduler

Kernel space

Kernel
thread
 User thread 1

User thread 2

User thread 3
Task 2
Ta

k3
sk

s
Thread library

Ta
1
with scheduler
User space
Kernel space

Kernel level Kernel level Kernel level Kernel level Kernel level
thread 1 thread 2 thread 3 thread 4 thread 5
 Header

First

Last / Tail Waiting Waiting

PCB PCB No.

No.
Open files

Priority
 Long term scheduling

New processes Ready queue

Short term Central Exit / End

P 5 P 3 P4 P 1 processing
scheduling
unit

Suspended
process

Time out
s
ur

Interrupt from
cc

Waiting for Event

higher priority
to

an interrupt wait
en

process
Ev

I/O Queue for Request for

completed I/O I/O

Child Child process fork ( )

terminate perform its task system call
 P1 P2 P3
0 14 16 20

Sum of P1 , P2 and P3 waiting time

3
0 14 16
3

P2 P3 P1
0 2 6 20
 Sum of P1 , P2 and P3 waiting time
3
6 0 2
3

P1 P2 P3 P4 P5

0 4 11 14 17 22
0 4 11 14 17 46
5 5

4 11 14 17 22 68
5 5
 P2 P4 P1 P3

0 2 6 11 17
6 0 11 2 19
4 4

11 2 17 6 36
4 4
 P3 P4 P1 P2

0 6 10 15 17

10 15 0 6 31
4 4

15 17 6 10 48
4 4
 P1 P2 P3 P4 P1 P3 P4 P1 P3

0 2 4 6 8 10 12 14 15 17
10 2 11 10 33
4 4

15 4 17 14 50
4 4
 P1 P2 P4 P1 P3

0 1 3 7 12 20

6 0 10 0 16
4 4
12 2 18 4 36
4 4
 P1 P4 P2 P3
0 8 10 16 17

P2 P3 P4 P2 P1
0 2 3 5 9 17

P1

P2

P3

P4

P1 P4 P2 P3
0 6 9 13 21
 P1 P2 P1 P4 P3 P2 P1 P4 P3 P3 P3
0 2 4 6 8 10 12 14 15 17 19 21

P1 P1

P2 P2

P3 P3

P4 P4

A A B A B C B C D B C E D B C E D B D D
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
4 16 11 14 8
5
 TM

TECHNICAL PUBLICATIONS - An up thrust for knowledge

 Entry section

Remainder section Critical section

Exit section

Entry section
Critical section
Exit section
Remainder section
Monitor entry queue
Shared data

Condition variable
Local to
X
monitor
Y

Entry methods
Only one active
at any moment
called from
outside monitor

Local methods

Code
initialization
Monitor entry queue
Thread waiting to enter the monitor

Shared data

Condition variable

Local to
monitor

Entry method
Only one active
at any moment
called from
outside monitor

Local methods

Code
initialization
reader writer
1 1

reader Shared writer

2 2
 data

 
reader writer
R W
 Add data Take data
items items
Producer Consumer

(Increment counter) (Decrement counter)

Shared buffer
Producer Consumer

(Waiting)

Buffer full

Producer Consumer

(Waiting)

Buffer empty
Producer Consumer

Buffer partially empty

 P1

Food
P2
P5

P4 P3
 Thinks a Lock left Lock Eat for a
while fork first right fork while
Philosopher

Unlock Unlock left

right fork fork
Process
 P R

Request Held by
P P

(a) Request edge (b) Claim edge

P1 P2
R1 R2

P1 P3

R3

R1 R2

P2 P4
 R1

R2

R3

P1 P1
R1

R1 R2

R2

P2 P2

(P1 , P2 , P3 , P4 ) (R 1 , R 2 , R 3 , R 4 )

R1

R2

R3

R4

R5

R2 R3

P1 P2 P3 P4

R1
R4
 P1 Pk D1 Dk
H1 Hk
P1 P2 Pk P1
M1 Mn P1 Pn

H 1 ... H k Di
Mi Hi + Di
M 1 ... M k
Pk+ 1 Pn

Mi M k+ 1 ... M n

M 1 ... M n M 1 ... M k M k+ 1 ... M n

 n n n n
Mi Hi Di Hi Di
i= 1 i= 1 i= 1 i= 1

Unsafe
state Safe
state

Deadlock
 Rj Pi

n
Allocation (Pi )
i 1
 (P1 , P2 , P3 , P4 , P5 )
(R 1 , R 2 , R 3 ) R1 R2
R3

P1

need i available i
P3
 P2 P4 P5 P1 P3

R1 R2 R3 R4 R1 R2 R3 R4 R1 R2 R3 R4

P0

P1

P2

P3

P4

P1
 P0 P2 P3 P4 P1

P1
 R1 R2 R3 R1 R2 R3
P1
P2
P3

P1

P3 , P2 , P1
 (1 1 0)

R1 R2 R1 R2 R1 R2

P1

P2

P3

P2 , P4 , P1 , P3
P0

P1

P2

P3
P0

P1

P2

P3

P1

P4

P0
P1
P2
P3
P4

P0
P1
P2
P3
P4

P1
P2
 P0 P3 P4 P1 P2
P1

P0

P1

P2

P3

P4

P0

P1

P2

P3

P4

P4

P0

P1

P2

P3

P4
 P3 P2
P3 P2

P1

P1

(a) Resource allocation (b) Wait for graph

graph

Pi  Pj
Pi Pj
 TM

TECHNICAL PUBLICATIONS - An up thrust for knowledge

 N
2 User
process 6

Free space

Free space

User
Limit process 1
+
User Allocated space
base
process 4 for process
Base Free space

Operating
system
kernel
0
Primary
memory
 Memory
Source Linkage
Compiler Loader image
program editor of program

Load
Compile time Execution
time time
 Relocation Main memory
register
Kernel
(y)
free
Logical Physical
+
Processor address address
(x) Relocation (x + y) free

Memory Data
management
unit
Process control
information Process control
block
Entry point
to program Jump
Program instruction

Reference
Data to data
Current top
of stack
Stack
Primary memory

Kernel
16 m

16 m

16 m

16 m
 Kernel Kernel Kernel
16 M 16 M 16 M

Program 1 Program 1
16 M 16 M
Free Program 2
space 10 M
48 M Free
space Free space
32 M 22 M
(a) (b) (c)

Kernel Kernel Kernel

16 M 16 M 16 M
Program 1
Program 1 Program 1
16 M
16 M 16 M
Program 5
Program 2 7M
Program 2
10 M Free space
10 M
3M
Program 3
Program 3
Program 3 8M
8M
8M
Program 4 Program 4
12 M 12 M
Free space
14 M Free space Free space
2M 2M
(d) (e) (f)
 0
Operating
system
4000
Program 1
Base register
5000
value
Program 2
7000
Free space

7000 – 5000 = 2000 (Limit register value)

 Processor

Logical
address(x)

Limit N
x<y Error
register
generates
(y)
Y

Limit
register (x + z)
(z)
Physical
address
OS
Free

Primary
memory
Operating Operating Operating
system system system

Program 1 Program 1 Program 1

(10 MB) (10 MB) (10 MB)

Program 2 Program 2
(15 MB) (15 MB)
Free space
Program 3
Free space (12 MB)
Free space

Operating Operating
system system

Program 1 Program 1
(10 MB) (10 MB)

Free space

Free space Program 2

(15 MB)

Free space
Operating Operating
system system

Program 1 Program 1
24 MB 24 MB

Free space Program 4

32 MB 30 MB
Internal
Free space
Program N fragmentation
40 MB Program N
40 MB
Before After

Operating
system

Program 1 Program 91
24 MB (52 MB)

Free space (New process with

32 MB size 52 MB)
Program N
40 MB

Free space
20 MB
Operating system Operating system

Program 1 Program 1

Free space Program 2

Program 2 Program 4

Program 4
Free space
Free space
 6 kB 6 kB 6 kB 6 kB

14 kB 14 kB 14 kB 12 kB
2 kB

12 kB
19 kB 19 kB 9 kB
7 kB

11 kB 11 kB 11 kB

13 kB 12 kB 13 kB 13 kB

Primary Best fit Worst fit First fit

memory
 1 MB Initially

512 kB 512 kB

256 kB 25 kB 512 kB

100 kB 128 kB 256 kB 512 kB 100 kB Request

0 kB 128 kB 256 kB 300 kB 300 kB Request

512 kB 300 kB 100 kB Returned

2N
2k
 2k
2k 2 k+ 1
2k
 Page number (P) Displacement or offset (D)

Page number (P) Page offset (D) Virtual address

Address
translation

Physical page number Page offset Physical address

 Physical
Logical address Physical address memory

Page number Displacement X Displacement

CPU (d) (d)
(p)

Page table

Page
number

X
 Page frame
number

Process P1
0 0 13
1 1 7
2 2 5
3 3 6
4 4 2
5 5 8
6 6 9
7 7 0
Page table
for process
P1

Physical Page
address frame
000000
P1
100000 1
Virtual Virtual Page
address page number Page frame 101000 100
0000 0 0 FFD
102000 101
01000 1 100 P2
1
2 103 103000 102
02000
LDA 003200 2
3 FFF 104000 103
03000
3

200
FFF200
C FFE000 FFE
P0
FFF000 FFF
P3

Memory
 Frame Protection
Index
number bit
0 4 Valid

1 2 Invalid
Main
2 5 Valid memory
3 7 Valid

4 1 Valid

5 3 Invalid
CPU Offset Offset

Page Primary
table memory

TLB
 2 12
2 32 2 12
2 20

Virtual address
Page directory + P t d
entries 10 bits 10 bits 12 bits

Page table
a
X

Y
W
X +
X+W Y'

Page Displacement
Outer frame
page table
Physical address
 CPU
Byte
Virtual
address To primary
D memory
Displacement

Hash table
Hash (f)
function
 Main
Heap
program Library
function

Thread
stack
Thread
stack
Symbol
table
Library
Add ( ) function
 Segment number Offset

Segment table

Limit Base
address

Segment Displacement
CPU
number (s) (d)

Logical address

Memory

Yes Physical
d limit +
address

No

Error
 Process P1

OS

Segment table Shared

segment in
between P1 and P2
Process P2

Segment table Physical memory

 2 24
210
28
2 10
28 2 10 2 18
2 18
 2 29

23

28

2 29
2 29 2 8 2 29 8 2 21 21

28

Main

memory

Address
space

Virtual
memory Hard disk
 Primary
memory
Virtual address
space OS

Memory

Management
unit Secondary
storage
device
 Phys l
Virtual ical sica
CPU MMU Phy
addre ess
address ss addr
Cache Primary
memory memory Disk
DMA
 Swap P2 out
Image for
P2

Image for Swap P1 in

P1

Secondary Physical memory

storage disk

P2 P2
P2
P2

P1
P1
 pi w i pi wi
pi

pi w i
pi
pi

wi

Primary
memory
OS

Process
removed
from memory
Secondary
storage
Process device
loaded into
memory
 Frame Valid-invalid bit

0 1

1 0

2 1 Primary
memory
3 1

4 0

5 1

Page table
Add R1
Page table

Reference
Error Operating Search Secondary
Restart 0 system storage
kernel device

Primary memory

to
in
M t

g
od ab

n ry
di mo
ify le

a
Lo me
pa
ge

Free
space
Hit rate Hit time Miss rate Miss time
Hit time Miss rate Miss penalty
Memory access time * (1 – p) p * page fault service time
 si wi
si wi
Processor
utilization Thrashing begins

Degree of
multiprogramming

t


CPU time

Page
referenced
 2 2 3 4 7 6 7 7 6 4 5 5 5 3 3 4 4 4 4 4
t3
t1 t2

Working set for process

WS(t1) = { 2, 3, 4, 6 ,7 } WS(t2) = {5, 3, 4}
WS(t3) = {6, 7, 4, 5, 3}

ti

0 1 2 3 0 1 2 3 0 1 2 3 4 5 6 7
t3
t1 t2

WS(t1) = { 0, 1, 2, 3 }
WS(t2) = { 3, 0, 1, 2, 4, 5, 6, 7 }
WS(t3) = { 1, 2, 3, 0, 4, 5 }
 R1 R2 R3 R4 R1 R2 R3 R4 R1 R2 R3 R4

P0

P1

P2

P3

P4

P1
9 789391 567040
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