MM74HC123A Dual Retriggerable Monostable Multivibrator

September 1983
Revised February 1999

MM74HC123A
Dual Retriggerable Monostable Multivibrator
General Description put pulse equation is simply: PW = (REXT) (CEXT); where
PW is in seconds, R is in ohms, and C is in farads. All
The MM74HC123A high speed monostable multivibrators
inputs are protected from damage due to static discharge
(one shots) utilize advanced silicon-gate CMOS technol-
by diodes to VCC and ground.
ogy. They feature speeds comparable to low power Schot-
tky TTL circuitry while retaining the low power and high
noise immunity characteristic of CMOS circuits. Features
Each multivibrator features both a negative, A, and a posi- ■ Typical propagation delay: 25 ns
tive, B, transition triggered input, either of which can be ■ Wide power supply range: 2V–6V
used as an inhibit input. Also included is a clear input that
■ Low quiescent current: 80 µA maximum (74HC Series)
when taken low resets the one shot. The MM74HC123A
can be triggered on the positive transition of the clear while ■ Low input current: 1 µA maximum
A is held LOW and B is held HIGH. ■ Fanout of 10 LS-TTL loads
The MM74HC123A is retriggerable. That is it may be trig- ■ Simple pulse width formula T = RC
gered repeatedly while their outputs are generating a pulse ■ Wide pulse range: 400 ns to ∞ (typ)
and the pulse will be extended. ■ Part to part variation: ±5% (typ)
Pulse width stability over a wide range of temperature and
■ Schmitt Trigger A & B inputs enable infinite signal input
supply is achieved using linear CMOS techniques. The out-
rise and fall times.

Ordering Code:
Order Number Package Number Package Description
MM74HC123AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC123ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC123AMTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC123AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Timing Component

Pin Assignment for DIP, SOIC, SOP and TSSOP

Note: Pin 6 and Pin 14 must be hard-wired to GND.

Top View

© 1999 Fairchild Semiconductor Corporation DS005206.prf www.fairchildsemi.com

MM74HC123A

Truth Table
Inputs Outputs
Clear A B Q Q
L X X L H
X H X L H


X X L L H
↑

H L
↓

H H
↑ L H
H =
HIGH Level
L =
LOW Level
↑ =
Transition from LOW-to-HIGH


↓ =
Transition from HIGH-to-LOW
= One HIGH Level Pulse
= One LOW Level Pulse
X = Irrelevant

Logic Diagram

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 MM74HC123A
Absolute Maximum Ratings(Note 1) Recommended Operating
(Note 2) Conditions
Supply Voltage (VCC) −0.5V to +7.0V Min Max Units
DC Input Voltage (VIN) −1.5V to VCC +1.5V Supply Voltage (VCC) 2 6 V
DC Output Voltage (VOUT) −0.5V to VCC +0.5V DC Input or Output Voltage 0 VCC V
Clamp Diode Current (IIK, IOK) ±20 mA (VIN, VOUT)
DC Output Current, per pin (IOUT) ±25 mA Operating Temperature Range (TA) −40 +85 °C
DC VCC or GND Current, per pin (ICC) ±50 mA Input Rise or Fall Times
Storage Temperature Range (TSTG) −65°C to +150°C (Clear Input)
Power Dissipation (PD) (tr, tf) VCC = 2.0V 1000 ns
(Note 3) 600 mW VCC = 4.5V 500 ns
S.O. Package only 500 mW VCC = 6.0V 400 ns
Lead Temperature (TL) Note 1: Maximum Ratings are those values beyond which damage to the
device may occur.
(Soldering 10 seconds) 260°C
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation Temperature Derating: Plastic “N” Package: −
12mW/°C from 65°C to 85°C

DC Electrical Characteristics (Note 4)

TA = 25°C TA = −40 to 85°C TA = −55 to 125°C
Symbol Parameter Conditions VCC Units
Typ Guaranteed Limits
VIH Minimum HIGH Level Input 2.0V 1.5 1.5 1.5 V
Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum LOW Level Input 2.0V 0.3 0.3 0.3 V
Voltage 4.5V 0.9 0.9 0.9 V
6.0V 1.2 1.2 1.2 V
VOH Minimum HIGH Level VIN = VIH or VIL
Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VIN = VIH or VIL V
|IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum LOW Level VIN = VIH or VIL
Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VIN = VIH or VIL V
|IOUT| ≤ 4 mA 4.5V 0.2 0.26 0.33 0.4 V
|IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maximum Input Current VIN = VCC or GND 6.0V ±0.5 ±5.0 ±5.0 µA
(Pins 7, 15)
IIN Maximum Input Current VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
(all other pins)
ICC Maximum Quiescent Supply VIN = VCC or GND 6.0V 8.0 80 160 µA
Current (standby) IOUT = 0 µA
ICC Maximum Active Supply VIN= VCC or GND 2.0V 36 80 110 130 µA
Current (per R/CEXT = 0.5VCC 4.5V 0.33 1.0 1.3 1.6 mA
monostable) 6.0V 0.7 2.0 2.6 3.2 mA
Note 4: For a power supply of 5V ±10% the worst-case output voltages (VOH, VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when design-
ing with this supply. Worst-case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage current
(IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

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MM74HC123A
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
Symbol Parameter Conditions Typ Limit Units

tPLH Maximum Trigger Propagation Delay 22 33 ns

A, B or Clear to Q
tPHL Maximum Trigger Propagation Delay 25 42 ns
A, B or Clear to Q
tPHL Maximum Propagation Delay, Clear to Q 20 27 ns
tPLH Maximum Propagation Delay, Clear to Q 22 33 ns
tW Minimum Pulse Width, A, B or Clear 14 26 ns
tREM Minimum Clear Removal Time 0 ns
tWQ(MIN) Minimum Output Pulse Width CEXT = 28 pF 400 ns
REXT = 2 kΩ
tWQ Output Pulse Width CEXT = 1000 pF 10 µs
REXT = 10 kΩ

AC Electrical Characteristics
CL = 50 pF tr = tf = 6 ns (unless otherwise specified)
TA = 25°C TA = −40 to 85°C TA = −55 to 125°C
Symbol Parameter Conditions VCC Units
Typ Guaranteed Limits
tPLH Maximum Trigger Propagation 2.0V 77 169 194 210 ns
Delay, A, B or Clear to Q 4.5V 26 42 51 57 ns
6.0V 21 32 39 44 ns
tPHL Maximum Trigger Propagation 2.0V 88 197 229 250 ns
Delay, A, B or Clear to Q 4.5V 29 48 60 67 ns
6.0V 24 38 46 51 ns
tPHL Maximum Propagation Delay 2.0V 54 114 132 143 ns
Clear to Q 4.5V 23 34 41 45 ns
6.0V 19 28 33 36 ns
tPLH Maximum Propagation Delay 2.0V 56 116 135 147 ns
Clear to Q 4.5V 25 36 42 46 ns
6.0V 20 29 34 37 ns
tW Minimum Pulse Width 2.0V 57 123 144 157 ns
A, B, Clear 4.5V 17 30 37 42 ns
6.0V 12 21 27 30 ns
tREM Minimum Clear 2.0V 0 0 0 ns
Removal Time 4.5V 0 0 0 ns
6.0V 0 0 0 ns
tTLH, tTHL Maximum Output 2.0V 30 75 95 110 ns
Rise and Fall Time 4.5V 8 15 19 22 ns
6.0V 7 13 16 19 ns
tWQ(MIN) Minimum Output CEXT = 28 pF 2.0V 1.5 µs
Pulse Width REXT = 2 kΩ 4.5V 450 ns
REXT = 6 kΩ (VCC = 2V) 6.0V 380 ns
tWQ Output Pulse Width CEXT = 0.1 µF Min 5.0V 1 0.9 0.86 0.85 ms
REXT = 10 kΩ Max 5.0V 1 1.1 1.14 1.15 ms
CIN Maximum Input 12 20 20 20 pF
Capacitance (Pins 7 & 15)
CIN Maximum Input 6 10 10 10 pF
Capacitance (other inputs)
CPD Power Dissipation (Note 5) 70 pF
Capacitance
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC V CC, and the no load dynamic current consumption,
IS = CPD VCC f + I CC.

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 MM74HC123A
Theory of Operation

1POSITIVE EDGE TRIGGER

2NEGATIVE EDGE TRIGGER
3POSITIVE EDGE TRIGGER
4POSITIVE EDGE RE-TRIGGER (PULSE LENGTHENING)
5RESET PULSE SHORTENING
6CLEAR TRIGGER
FIGURE 1.

TRIGGER OPERATION the value of CEXT, REXT, or the duty cycle of the input
As shown in Figure 1 and the logic diagram, before an waveform.
input trigger occurs, the one shot is in the quiescent state
with the Q output LOW, and the timing capacitor CEXT com- RETRIGGER OPERATION
pletely charged to VCC. When the trigger input A goes from The MM74HC123A is retriggered if a valid trigger occurs 3
VCC to GND (while inputs B and clear are held to VCC) a followed by another trigger 4 before the Q output has
valid trigger is recognized, which turns on comparator C1 returned to the quiescent (zero) state. Any retrigger, after
and Nchannel transistor N11. At the same time the output the timing node voltage at the R/CEXT pin has begun to rise
latch is set. With transistor N1 on, the capacitor C EXT rap- from VREF1, but has not yet reached VREF2, will cause an
idly discharges toward GND until VREF1 is reached. At this increase in output pulse width T. When a valid retrigger is
point the output of comparator C1 changes state and tran- initiated 4, the voltage at the R/CEXT pin will again drop to
sistor N1 turns off. Comparator C1 then turns off while at VREF1 before progressing along the RC charging curve
the same time comparator C2 turns on. With transistor N1 toward VCC. The Q output will remain HIGH until time T,
off, the capacitor CEXT begins to charge through the timing after the last valid retrigger.
resistor, REXT, toward VCC. When the voltage across CEXT Because the trigger-control circuit flip-flop resets shortly
equals VREF2, comparator C2 changes state causing the after CX has discharged to the reference voltage of the
output latch to reset (Q goes LOW) while at the same time lower reference circuit, the minimum retrigger time, trr is a
disabling comparator C2. This ends the timing cycle with function of internal propagation delays and the discharge
the monostable in the quiescent state, waiting for the next time of CX:
trigger.
A valid trigger is also recognized when trigger input B goes
from GND to VCC (while input A is at GND and input clear
is at VCC2). The MM74HC123A can also be triggered when Another removal/retrigger time occurs when a short clear
clear goes from GND to VCC (while A is at GND and B is at pulse is used. Upon receipt of a clear, the one shot must
VCC6). charge the capacitor up to the upper trip point before the
one shot is ready to receive the next trigger. This time is
It should be noted that in the quiescent state CEXT is fully dependent on the capacitor used and is approximately:
charged to VCC causing the current through resistor REXT
to be zero. Both comparators are “off” with the total device
current due only to reverse junction leakages. An added
feature of the MM74HC123A is that the output latch is set
via the input trigger without regard to the capacitor voltage.
Thus, propagation delay from trigger to Q is independent of

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MM74HC123A
RESET OPERATION
These one shots may be reset during the generation of the clear input is held low, any trigger inputs that occur will be
output pulse. In the reset mode of operation, an input pulse inhibited and the Q and Q outputs of the output latch will
on clear sets the reset latch and causes the capacitor to be not change. Since the Q output is reset when an input low-
fast charged to VCC by turning on transistor Q1 5. When level is detected on the Clear input, the output pulse T can
the voltage on the capacitor reaches VREF2, the reset latch be made significantly shorter than the minimum pulse width
will clear and then be ready to accept another pulse. If the specification.

Typical Output Pulse Typical 1ms Pulse Width

Width vs. Timing Components Variation vs. Supply

Typical Distribution of Output Minimum REXT vs.

Pulse Width, Part to Part Supply Voltage

Typical 1ms Pulse Width

Variation vs. Temperature

Note: R and C are not subjected to temperature. The C is polypropylene.

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 MM74HC123A
Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D

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MM74HC123A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16

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 MM74HC123A Dual Retriggerable Monostable Multivibrator
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E

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