Gate Level Modeling

• Net-list description
– built-in primitives gates
IN1
OUT1
IN2 X

module my_gate(OUT1, IN1, IN2);

output OUT1; Internal Signal
input IN1, IN2;
wire X;
and (X, IN1, IN2); Any internal net must be defined as wire
not (OUT1, X);
endmodule
 A Full Adder
module fadd (co, s, a, b, c);
input a, b ,c ;
output co, s ;
wire n1, n2, n3;
xor (n1, a, b) ;
xor (s, n1, c) ;
nand (n2, a, b) ;
nand (n3,n1, c) ;
nand (co, n3,n2) ;

endmodule
MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 103
 DATAFLOW MODELING
❑ Data flow level description of a digital circuit is at higher level, it makes the
circuit description more compact as compared to design through gate
primitives

❑ Design implement using data flow modeling uses a continuous assignment

statement and Verilog provides different operators to perform a function

❑ The assignment statement start with the keyword assign and results are
assigned to nets

❑ Continuous assignment – most basic statement used to drive value onto net

Syntax: assign LHS_target=RHS_expression

Example: wire c,a,b; //net declaration

assign c=a&b; //continuous assignment

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 104

 DATAFLOW MODELING

HALF ADDER

module halfadder(s,c,a,b);
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 108

 Full Adder
A
S
module fadd (S, Cout, A, B, Cin); B
output S, Cout; Cin
input A, B, Cin;

assign S = A ^(B ^ Cin); Cout

assign Cout = (A & B) | (A & Cin) | (B & Cin);

endmodule

Sum, Cin  (A  B)
Carry, Cout = AB+ ACin + BCin .
 DATAFLOW MODELING

HALF ADDER FULL ADDER

module halfadder(s,c,a,b); module fa_da(a,b,cin,sum,cout);

input a,b; input a,b,cin;
output s,c; output sum,cout;
assign s=a^b; assign sum=a^b^cin;
assign c=a&b; assign cout=(a&cin)|(b&cin)|(a&b);
endmodule endmodule

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 108

 DATAFLOW MODELING
BINARY TO GRAY CODE CONVERTER

module binary_to_gray(g,b);
input [3:0]b;
output[3:0]g;
assign g[3]= b[3];
assign g[2]= b[2]^b[3];
assign g[1]= b[1]^b[2];
assign g[0]= b[0]^b[1];
endmodule

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 110

Implement the function f = ∑ (0, 1, 2, 5, 13, 15)
using Verilog HDL
Draw the circuit diagram of the following Verilog code
Draw the circuit diagram of the following Verilog code
Draw the circuit diagram of the following Verilog code
Draw the circuit diagram of the following Verilog code
MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 76
 BEHAVIORAL MODELING
❑ Behavioral model enables you to describe the system at a higher
level of abstraction

❑ All we need to do is to describe the behavior of our design

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 78

 simpleBehavioral.v
Sensitivity trigger: when any of a, b or c changes.
Replace this statement with “initial”. Output?!

Modules are of three types: behavioral,

module aOrNotbOrc(d, a, b, c); dataflow, gate-level. Behavioral
modules contain code in procedural blocks.
output d;
input a, b, c; Statements in a procedural block cannot be
reg d, p; re-ordered without affecting the program as
these statements are executed sequentially,
always @(a or b or c) exactly like in a conventional programming
language such as C.
begin
p = a || ~b; Ports are of three types: input, output, inout.
d = p || c; Each must be declared. Each port also has a
end data type: either reg or wire (net). Default is wire.
endmodule Inputs and inouts are always wire. Output ports
that hold their value are reg, otherwise wire.
More later…
One port register, one internal register.
Wires are part of the more general class of nets.
However, the only nets we shall design with are wires.
 Structural Vs Procedural
Structural Procedural
• textual description of circuit • Think like C code
• order does not matter
• Order of statements are
• Starts with assign statements important
• Starts with initial or always
• Harder to code statement
• Need to work out logic
• Easy to code
• Can use case, if, for

reg c, d;
always@ (a or b or c)
wire c, d;
begin
assign c =a & b;
c =a & b;
assign d = c |b;
d = c |b;
42 end
 Structural Vs Procedural
wire c, d; reg c, d;
assign c =a & b; always@ (a or b or c)
assign d = c |b; begin
c =a & b;
d = c |b;
end

43
 BEHAVIORAL MODELING
❑ Behavioral model enables you to describe the system at a higher
level of abstraction

❑ All we need to do is to describe the behavior of our design

❑ Action → How the model of our circuit should behave?
❑ Timing control → At what time do what thing & At what condition do
what thing

❑ Verilog supports the following construct to model circuit

behavior
❑ Procedural block
❑ Procedural assignment
❑ Timing controls
❑ Block statement
❑ Conditional statement

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 78

 BEHAVIORAL MODELING
PROCEDURAL BLOCK - INITIAL STATEMENT
❑ Initial statement causes procedural statement to executes only once and it begin
its execution at start of simulation time 0.

❑ Sequential block (begin-end) is the most commonly used procedural statement,

that is it wait for a certain time until an event occurs
Syntax: initial [timing_controls] procedural statements
Example: initial #2 a=0

Example: //initial statement with sequential block

reg a,b;
initial
begin
a=1`b0;
b=1`b1;
#5 a=1`b1;
end;
MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 80
 BEHAVIORAL MODELING
PROCEDURAL BLOCK - ALWAYS STATEMENT
❑ For circuit synthesis we use the always block and such a block
must contain all sequential constructs

❑ Note that the statements in an always block between begin/end

are executed sequentially just as they are written

❑ Variables assigned a value inside an always block must be of type

reg or integer

❑ The if, case, for loop, and while loop must appear inside an always
block

❑ A module can have multiple blocks, but blocks cannot be nested

❑ For modules that have multiple always blocks all of the always
blocks are executed in parallel
MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 81
 BEHAVIORAL MODELING
PROCEDURAL BLOCK - ALWAYS STATEMENT
❑ Always blocks are repeated executed until simulation is stopped. Similar to
initial block it begin its execution at start of simulation time 0.

❑ This statement is used to model a block of activity that is repeated continuously

in a digital circuit. Example:

module clock_gen;
reg clock, temp;

//Initialize clock at time zero

Initial clock = 1‘b0;
Syntax: always [timing_control] procedural statement
(or) //Toggle clock every half-cycle
always @(sensitivity_list) always #10 clock = -clock;
begin
/*sequential statements always @ (posedge clock)
consisting of assignment, begin
if, case, while, and for loops */ temp=temp+1;
end end
MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 82
 BEHAVIORAL MODELING
BLOCKING vs NONBLOCKING

Blocking Non-blocking
◼ <variable> = <statement> ◼ <variable> <= <statement>

◼ Similar to C code ◼ The inputs are stored once the

procedure is triggered
◼ The next assignment waits
until the present one is ◼ Statements are executed in
finished parallel

◼ Used for combinational logic ◼ Used for flip-flops, latches and

registers

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 86

 BEHAVIORAL MODELING
BLOCKING STATEMENT - SEQUENTIAL BLOCK
❑ Block statements are used to group multiple statements to act together as one. There are
two types of blocks: sequential blocks and parallel blocks

❑ The keywords begin and end are used to group statements into sequential blocks.
❑ Sequential blocks have the following characteristics:
❑ The statements in a sequential block are processed in the order they are specified
❑ A statement is executed only after its preceding statement completes execution
❑ If delay or event control is specified, it is relative to the simulation time when the previous statement in the
block completed execution
//Illustration 1: Sequential block without delay //Illustration 2: Sequential blocks with delay
reg X, Y; reg x, y;
reg [1:0] z, w; reg [1:0] z , w;
initial initial
Begin begin
x = l'bO; x = l'bo; //completes at simulation time 0
y = l‘b1; #5 y = l'bl; //completes at simulation time 5
z = {x, y}; #10 z = {x, y}; //completes at simulation time 15
w = {y, x}; #20 w = {y, x); //completes at simulation time 35
End end

MODULE-5 ECE2003 – DIGITAL LOGIC DESIGN 87

Full Adder