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    Unit 1 - LP5

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    Unit 1 - LP5

    Uploaded by

    gokul.sengottaian1
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    UNIT 1 - LP5

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    vdvd

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    2 views14 pages

    Unit 1 - LP5

    Uploaded by

    gokul.sengottaian1
    vdvd

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 14

    Verilog Modeling

    COURSE CODE : 18EC603


    COURSE TITLE : DIGITAL VLSI SYSTEM DESIGN
    Presented by
    Dr. S Elango
    Assistant Professor
    Department of ECE
    BIT, Sathyamangalam
    Types of Modeling

    Dataflow Gatelevel Behavioural Switch Level

    1 2 3 4
    nmos, pmos
    assign and,or etc.. always Intermediate
    Equation Gate level Diagram
    Algorithm signal
    Types of Modelling

    Dataflow D Gate G
    Level
    Behaviour B
    Level
    Switch S
    Level
    Level

    Equation Logic Gates Truth Table Transistor


    Boolean Complete Behaviour & CMOS
    Equation & Logic Diagram Algorithm Schematic
    Simple & Block
    Logic Circuit Diagram
    Dataflow Modelling
    module gates( invo, ao, oo, xoo, a, b);
    input a, b;
    output ao, oo, nao, noo, xoo ;
    assign invo = ~a ;
    assign ao = a & b ;
    assign oo = a | b ;
    assign xoo = a ^ b ;
    endmodule
    4 Bit Adder
    module ripple (s,cout,a,b,cin);
    input [3:0]a,b;
    input cin;
    output [3:0]s;
    output cout;
    assign{cout,s}=a+b+cin;
    endmodule
    Logic Gates in Gate Level Modelling

    Usage :
    and (out, i1,i2);
    nand (out, i1,i2);
    or (out, i1,i2);
    nor (out, i1,i2);
    xor (out, i1,i2);
    xnor (out, i1,i2);
    Example Full Adder Using Half Adder
    Top Module Sub Module
    module fulladder (s, cout,a,b,cin); module halfadder (sum, carry, in0, in1);
    output cout,s; output sum, carry;
    input a,b,cin ; input in0, in1;
    halfadder ha1(s1,c1,a,b); // 2-input XOR gate.
    halfadder ha2(s,c2,s1,cin); xor x1 (sum, in0, in1);
    or o1(cout,c1,c2); // 2-input AND gate.
    endmodule and x2 (carry, in0, in1);
    endmodule

    c1
    s1 c2 Full Adder
    What is the Designer want ?

     Behaviour of the System


     Truth Table Verilog HDL

     Algorithm
     Input & Output Relation
     Don't Require Hardware details
    Control Statements – If & Case
     Syntax similar to C language
     Making decisions based upon certain conditions
     Conditions are used to decide statement execution
     Keyword : if and else
     Multiway Branching – Switch Case
     Too many alternatives exist
     Keyword : case, endcase and default
    Conditional Statement (if, else if, else)
     if Statement

     Syntax:
    if (condition) Example:
    if (Clk)
    Q = 0;
    procedural_statemen else
    t Q = D;

    else if (condition)
    Coding Section Example : 2:1 MUX
    module mux_2x1(a, b, sel, out); Behaviour of MUX:
    input a, b, s;
    output out;
    reg out;
    always @(a or b or s)
    begin Sensitivity List
    if (s == 1)
    out = a;
    else out = b;
    end
    endmodule
    Coding Section Example : 4:1 MUX using Case
    module MUX (C, D, E, F, S, MUX_OUT); Behaviour of MUX:
    input C, D, E, F;
    input [1:0] S;
    output MUX_OUT;
    reg MUX_OUT;
    always @(C or D or E or F or S)
    begin
    case (S)
    2'b00 : MUX_OUT = C;
    2'b01 : MUX_OUT = D;
    2'b10 : MUX_OUT = E;
    default : MUX_OUT = F;
    endcase
    end
    endmodule
    Mind Map
    Thank You!

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