Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd Logo
Upload

Welcome to Scribd!

  • 187 views

    T3 Verilog4CombinationalLogic

    Uploaded by

    0307ali
    This document provides an overview of using Verilog to model combinational logic circuits at the gate level. It discusses port declarations, data types, structural and behavioral modeling, and gives examples of modeling an XOR gate and multiplexer. It also briefly covers simulation using a test bench module to apply stimuli and display output results.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd

    T3 Verilog4CombinationalLogic

    Uploaded by

    0307ali
    187 views21 pages
    This document provides an overview of using Verilog to model combinational logic circuits at the gate level. It discusses port declarations, data types, structural and behavioral modeling, and gives examples of modeling an XOR gate and multiplexer. It also briefly covers simulation using a test bench module to apply stimuli and display output results.

    Original Description:

    This is a presentation on Verilog Combinational Logic

    Original Title

    T3_Verilog4CombinationalLogic (3)

    Copyright

    © © All Rights Reserved

    Available Formats

    PPTX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document provides an overview of using Verilog to model combinational logic circuits at the gate level. It discusses port declarations, data types, structural and behavioral modeling, and gives examples of modeling an XOR gate and multiplexer. It also briefly covers simulation using a test bench module to apply stimuli and display output results.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    187 views21 pages

    T3 Verilog4CombinationalLogic

    Uploaded by

    0307ali
    This document provides an overview of using Verilog to model combinational logic circuits at the gate level. It discusses port declarations, data types, structural and behavioral modeling, and gives examples of modeling an XOR gate and multiplexer. It also briefly covers simulation using a test bench module to apply stimuli and display output results.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 21

    EE421 DIGITAL

    SYSTEMS DESIGN

    REFERENCE:


    Verilog Programming for Implementing Combination Logic
    CE303 DIGITAL SYSTEMS II

    02 October 2009

    Abdullah Mansoor
    Dept of Electrical Engineering
    NUST School of Electrical Engineering and Computer Sciences
    (SEECS)
    Gate Level Modeling
    Used to describe Combinational Logic
    circuits using Verilog
    Coding is comparatively simpler as
    compare to higher level of modeling
    Use blocking statements
    Design Example: XOR gate
    XOR
    out1=a.b + b.a

    Design Example: XOR gate
    module <NAME> (<LIST OF PORTS>);

    //port Declarations

    //data type/variables declaration

    //functionality in terms of structural or behavioral style

    end module

    Design Example: XOR gate
    module myXOR (a, b, out1);

    //port Declarations

    //data type/variables declaration

    //functionality in terms of structural or behavioral style

    end module

    Note:
    Good programming style is to use self explanatory port names
    Do not use pre-defined keywords



    Design Example: XOR gate
    Step1: Port Declarations
    module myXOR (a, b, out1);
    input a, b;
    output out1;
    //data type/variables declaration
    //functionality in terms of structural or behavioral style
    end module

    PORT Declarations:
    input : Input port
    output: Output port
    inout: Bidirectional port
    Note: inout usually used for power supply ports or other bidirectional ports


    Design Example: XOR gate
    Step2: Data Type Declaration
    module myXOR (a, b, out1);
    input a, b;
    output out1;
    wire a_br, b_br, and1out, and2out, out1;
    //functionality in terms of structural or behavioral style
    end module

    Verilog Data Types:
    There are three important data types in addition to other data types
    available in C:
    Nets: To describe interconnection between devices
    Nets are further classified as wire, wand, wor etc.
    Registers: To represent storage elements
    Parameters: user-defined constants
    Note: To know more about data types consult sec 3.2 PAL

    Design Example: XOR gate
    Step3: Structural Implementation
    module myXOR (a, b, out1);
    input a, b;
    output out1;
    wire a_br, b_br, and1out, and2out, out1;

    not nota (a_br, a);
    not notb (b_br, a);
    and and1(and1out, a, b_br);
    and and2(and2out, b, a_br);
    or or1(out1, and1out, and2out);

    end module


    Not: Syntax for Instantiation:
    <Buit-in gates or predefined Modules> <instance_name>(interconnections;output is first then
    inputs);
    Design Example: XOR gate
    Step3: Behavioral Implementation
    module myXOR (a, b, out1);
    input a, b;
    output out1;

    assign out1=(a & ~b) | (~a & b);

    end module

    Continuous assignment:
    The RHS is assigned to LHS immediately
    (except for small delay associated in calculation)
    Continuous Assignment
    Represents true Hardware implementation
    Cannot implement some functionalities
    Edge triggering
    Sequential style code like case statements
    etc.
    These functions are added using non-
    continuous assignments

    Non-continuous assignments
    These can be implemented either using
    always or initial block in Verilog code
    Example always block
    module myXOR (a, b, out1);
    input a, b;
    output out1;
    reg out1;
    always @ (a or b) begin
    out1=(a & ~b) | (~a & b);
    end
    end module


    Register type out1. Not really a
    register. Just Verilog Syntax.
    Sensitivity list triggers action in the body
    Design Example2: 2-to-1 MUX
    /* 2-to-1 mux implementation*/
    module myMUX (a, b, select, out1);
    input a, b, select;
    output out1;
    wire select_br, and1out, and2out;

    not (select_br, select);
    and (and1out, select_br, a);
    (and2out, select, b);
    or (out1, and1out, and2out);
    end module
    Design Example3: 4-to-1 MUX

    Design Example3: 4-to-1 MUX
    /* 2-to-1 mux implementation*/
    module myMUX4 (a, b, c, d select, out1);
    input a, b, c, d;
    Input [1:0] select;
    output out1;
    wire m1, m2;
    myMUX
    m0 (.select(select[0]), .a(a), .b(b), .out(m1));
    m1 (.select(select[0]), .a(c), .b(d), .out(m2));
    m2 (.select(select[1]), .a(m1), .b(m2), .out(out1));
    end module

    Design Example3: 4-to-1 MUX
    Using Non-Continuous assignment
    /* 2-to-1 mux implementation*/
    module myMUX4 (a, b, c, d select, out1);
    input a, b, c, d;
    input [1:0] select;
    output out1;
    reg out1;
    always @ (a, b, c, d, select)
    case (select)
    2b00: out1=a;
    2b01: out1=b;
    2b10: out1=c;
    2b11: out1=d;
    end
    end module

    Simulation and Testing using Verilog

    Test Bench
    module testbench;

    //data type declaration

    //instantiate modules

    //Apply Stimulus

    //Display Results

    end module
    Test Bench MUX
    module testbench;
    //define variables
    reg a, b;
    wire out1;
    //instantiate modules
    myXOR XOR1 (a, b, out1);
    initial begin //Apply Stimulus
    a=1b0;
    b=1b0;
    #5 a=1b1;
    #5 a=1b1;
    ----------
    ----------
    #100 $stop
    end

    initial begin //Display Results
    $display(a=%b, b=%b, out1=%b, a, b , out1);
    end
    end module
    Reading Assignment:

    Sec 3.2, Sec 6.3, and 6.4
    Thank you!

    You might also like