SPC 58 NH 92 C 5
SPC 58 NH 92 C 5
– 16 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD
support
– Dual-channel FlexRay controller
– One SD/SDIO/eMMC module
– One OctalSPI module with double Chip Select
– Two independent Ethernet controllers, one 10/100Mbps and the other one
10/100Mbps or 1Gbps, compliant IEEE 802.3-2008 and OPEN RGMII EPL v2.3
– Four I2C modules
– Two PSI5 modules
• Low power capabilities:
– Versatile low power modes
– Ultra low power standby with RTC
– Smart Wake-up Unit for contact monitoring
– Fast wakeup schemes
• Dual phase-locked loops with stable clock domain for peripherals and FM modulation
domain for computational shell
• Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some
support for 2010 standard
• Boot assist Flash (BAF) supports factory programming using a serial bootload through the
asynchronous CAN or LIN/UART
• Low power supply options:
– Single internal linear regulator with external ballast
– External low voltage supply (1.2V)
• Temperature range:
– -40 °C to 105 °C
– -40 °C to 125 °C
Package 6 MB 8 MB 10 MB
Dual core Triple core Dual core Triple core Dual core Triple core
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3.1 Power domains and power up/down sequencing . . . . . . . . . . . . . . . . . 24
4.4 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.5 Electromagnetic compatibility characteristics . . . . . . . . . . . . . . . . . . . . . . 26
4.6 Temperature profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.7 Device consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.8 I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.8.1 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.8.2 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.8.3 I/O pad current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.9 Reset pad (PORST) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 44
4.10 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.10.1 PLL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.10.2 PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.10.3 PLL_ETH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.11 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.11.1 Crystal oscillator 40 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.11.2 Crystal Oscillator 32 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.11.3 RC oscillator 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.11.4 Low power RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.12 ADC system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
1 Introduction
This document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the device. To
ensure a complete understanding of the device functionality, refer also to the device
reference manual and errata sheet.
2 Description
SPC58 family 40 nm
Processing shell
Number of Cores 2
Number of checker cores 1
32 KB Instruction
Local RAM
64 KB Data
Single Precision Floating Point Yes
SIMD (LSP) Yes
VLE Yes
16 KB Instruction
Cache
8 KB Data
Streaming shell
Number of Cores 1
Number of checker cores 0
32 KB Instruction
Local RAM
64 KB Data
Single Precision Floating Point Yes
SIMD (LSP) Yes
VLE Yes
16 KB Instruction
Cache
8 KB Data
Other
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BCTU_0 PBRIDGE_2
STDBY_CTU_0 Backdoor_XBAR
eMIOS_0 XBAR_1
GST_0 XBIC_Backdoor_XBAR
SAR_ADC_12bit_0_seq XBIC_Concentrator_1 ON-Platform IP
SAR_ADC_12bit_2_seq SMPU_1, 3 OFF-Platform IP
SAR_ADC_10bit_STDBY_seq XBIC_1
SAR_ADC_12bit_SUPERVISOR_seq PCM_0
SAR_ADC_12bit_0, 2 PFLASH_1
SAR_ADC_10bit_0_STDBY SEMA42
SAR_ADC_12bit_SUPERVISOR INTC_1
PSI5_0 SWT_0, 2, 3
FLEXRAY STM_0, 2
I2C_0 eDMA_1
I2C_2 PRAM_2, 3
DSPI_0, 2, 4, 6, 8 TDM_0
LINFlex_0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22
CAN_SUB_0_MESSAGE_RAM
CAN_SUB_0_M_CAN_0, 1, 2, 3
HSMHost I/F
AIPS_2 - Peripheral Cluster 2
DTS
JDC eMIOS_1 PBRIDGE_1
STCU SAR_ADC_12bit_1_seq
JTAGM SAR_ADC_12bit_3_seq
MEMU SAR_ADC_12bit_1, 3
IMA PSI5_1
CRC_0 I2C_1
DMAMUX_0, 2 I2C_3
PSI5-S DSPI_1, 3, 5, 7, 9
PIT_0 LINFlex_1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23
PBRIDGE_0
AIPS_1 - Peripheral Cluster 1
RTC/API CAN_SUB_1_MESSAGE_RAM
XBAR_0, 2
WKPU_0 CAN_SUB_1_M_CAN_1, 2, 3, 4
SMPU 0, 2
MC_PCU FCCU
PRAM_0,1
PMC_DIG CRC_1
PFLASH_0
MC_RGM DMAMUX_1, 3
2.3 Features
On-chip modules within SPC58EHx, SPC58NHx include the following features:
• Three main CPUs, dual issue, 32-bit CPU core complexes (e200z4), one of them
having a checker core in lock-step
– Power Architecture embedded specification compliance
– Instruction set enhancement allowing variable length encoding (VLE), encoding a
mix of 16-bit and 32-bit instructions, for code size footprint reduction
– Single-precision floating point operations
– Lightweight signal processing auxiliary processing unit (LSP APU) instruction
support for digital signal processing (DSP) on Core_0, Core_1, Core_2
– 32 KB local instruction RAM and 64 KB local data RAM for Core_0, Core_1 and
Core_2
– 16 KB I-Cache and 8 KB D-Cache for Core_0, Core_1 and Core_2
– 10 MB on-chip Flash
– Supports read during program and erase operations, and multiple blocks allowing
EEPROM emulation
– Supports read while read between the two code Flash partitions.
• 1088 KB on-chip general-purpose SRAM (+ 192 KB data RAM and 96 KB instruction
RAM included in the CPUs)
• 224 KB HSM dedicated flash memory (192 KB code + 32 KB data)
• Multi channel direct memory access controllers (eDMA)
– One eDMA with 64 channels
– One eDMA with 16 channels
• One interrupt controller (INTC) in lock-step
• Dual phase-locked loops with stable clock domain for peripherals and FM modulation
domain for processing and streaming shell
• Dual crossbar switch architecture for concurrent access to peripherals, Flash, or RAM
from multiple bus masters with end-to-end ECC
• Hardware security module (HSM) compliant with EVITA full
• System integration unit lite (SIUL)
• Boot assist Flash (BAF) supports factory programming using a serial bootload through
the asynchronous CAN or LIN/UART.
• Enhanced analog-to-digital converter system with
– One supervisor 12-bit SAR analog converter
– Four separate fast 12-bit SAR analog converters
– One separate 10-bit SAR analog converter for standby mode
• Eleven deserial serial peripheral interface (DSPI) modules, one working even in low
power mode
• Twenty four LIN and UART communication interface (LINFlexD) modules
– LINFlexD_0 is a Master/Slave
– All others are Masters
• Sixteen modular controller area network (MCAN) modules all supporting flexible data
rate (CAN-FD)
• Dual-channel FlexRay controller
only difference is that, it can check for patterns sequentially (1 field at a time)
unlike fixed/register filtering which can compare in parallel and at line rate.
– TSN features:
IEEE 802.1Qbv (EST)
IEEE 802.1AS-Rev/D2.0 (timing and synchronization)
IEEE 802.3br/D3.1 (frame preemption)
IEEE 802.1Qbu/D3.1 (frame preemption)
• SD/SDIO/MMC host interface that supports:
– eMMC - MultiMedia Card Specification v4.51
– 1-bit, 4-bit, 8-bit interface
– Full backward compatibility with legacy MMC cards (0-25 MHz), 25 MB/s
– Full High Speed SDR bus mode (0-50 MHz), 50 MB/s
– Full High Speed DDR bus mode (0-50 MHz), 100 MB/s
– 3.3 V IO voltage
– SD Card Specification v3.01
– Full support for Default Speed mode (0-25 MHz), 12.5 MB/s
– Full support for High Speed (0-50 MHz) mode, 25 MB/s
– 1-bit, 4-bit interface
– 3.3 V IO voltage
– SDIO Specification v3.0
– Full support for Default Speed mode (0-25 MHz) mode, 12.5 MB/s
– Full support for High Speed (0-50 MHz) mode, 25 MB/s
– 1-bit or 4-bit interface
– 3.3 V IO voltage
The current version supports only one SD3.01/SDIO3.0/MMC4.51 card at any one
time.
• OctalSPI host interface that supports:
– SPI mode
– 1-bit, 4-bit, 8-bit interface
– SDR for 1 bit interface only (SPI mode)
– SDR and DDR for 4 and 8 bits interface (quad and Octal SPI mode)
– 3.3 V IO voltage
– Clock up to 100 MHz
– SPI NOR device with DQS mode compliant
– Hyperbus(TM) bus mode
– Compliant with “HyperBus™ Specification Low Signal Count, High
Performance DDR Bus”, June 2017, revision F
– DDR for 8-bit interface
– 3.3 V IO voltage
4 Electrical characteristics
4.1 Introduction
The present document contains the target Electrical Specification for the 40 nm family 32-bit
MCU SPC58EHx, SPC58NHx products.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” (Controller Characteristics) is included in the “Symbol”
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” (System Requirement) is included in the
“Symbol” column.
The electrical parameters shown in this document are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 3 are used and
the parameters are tagged accordingly in the tables where appropriate.
P Those parameters are guaranteed during production testing on each individual device.
C Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T Those parameters are achieved by design validation on a small sample size from typical
devices.
D Those parameters are derived mainly from simulations.
Core voltage
VDD_LV SR D operating life — –0.3 — 1.4 V
range(1)
VDD_HV_IO_MAIN
VDD_HV_OSC
VDD_HV_FLA I/O supply
SR D — –0.3 — 6.0 V
VDD_HV_IO_EMMC voltage(2)
VDD_HV_IO_ETH0
VDD_HV_IO_ETH1
ADC ground Reference to
VSS_HV_ADV SR D –0.3 — 0.3 V
voltage digital ground
ADC Supply Reference to
VDD_HV_ADV SR D –0.3 — 6.0 V
voltage(2) VSS_HV_ADV
SAR ADC
VSS_HV_ADR_S SR D ground — –0.3 — 0.3 V
reference
SAR ADC
Reference to
VDD_HV_ADR_S SR D voltage –0.3 — 6.0 V
VSS_HV_ADR_S
reference(2)
VSS_HV_ADR_S
VSS-VSS_HV_ADR_S SR D differential — –0.3 — 0.3 V
voltage
VSS_HV_ADV
VSS-VSS_HV_ADV SR D differential — –0.3 — 0.3 V
voltage
— –0.3 — 6.0
Relative to Vss –0.3 — —
I/O input voltage
VIN SR D V
range(2)(3) (4) Relative to
VDD_HV_IO and — — 0.3
VDD_HV_ADV
Digital Input pad
TTRIN SR D — — — 1 ms
transition time(5)
Maximum DC
injection current
IINJ SR T for each — –5 — 5 mA
analog/digital
PAD(6)
Maximum non-
operating
TSTG SR T Storage — –55 — 125 °C
temperature
range
Maximum
nonoperating
TPAS SR C temperature — –55 — 150(7) °C
during passive
lifetime
Maximum
No supply; storage
storage time,
temperature in
TSTORAGE SR — assembled part — — 20 years
range –40 °C to
programmed in
60 °C
ECU
Maximum solder
TSDR SR T temperature Pb- — — — 260 °C
free packaged(8)
Moisture
MSL SR T sensitivity — — — 3 —
level(9)
Typical range for
X-rays source
Maximum
during
TXRAY dose SR T cumulated — — 1 grey
inspection:80 ÷
XRAY dose
130 KV; 20 ÷
50 μA
1. VDD_LV: allowed 1.335 V - 1.400 V for 60 seconds cumulative time at the given temperature profile. Remaining time allowed
1.260 V - 1.335 V for 10 hours cumulative time at the given temperature profile. Remaining time as defined in Section 4.3:
Operating conditions.
2. VDD_HV: allowed 5.5 V – 6.0 V for 60 seconds cumulative time at the given temperature profile, for 10 hours cumulative
time with the device in reset at the given temperature profile. Remaining time as defined in Section 4.3: Operating
conditions.
3. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current
condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin
to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3 V can be used for nominal
calculations.
4. Relative value can be exceeded if design measures are taken to ensure injection current limitation (parameter IINJ).
5. This limitation applies to pads with digital input buffer enabled. If the digital input buffer is disabled, there are no maximum
limits to the transition time.
6. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in
Section 4.8.3: I/O pad current specifications.
7. 175°C are allowed for limited time. Mission profile with passive lifetime temperature >150°C have to be evaluated by ST to
confirm that are granted by product qualification.
8. Solder profile per IPC/JEDEC J-STD-020D.
9. Moisture sensitivity per JDEC test method A112.
Operating
FSYS(2) SR P system clock — — — 200 MHz
frequency(3)
Operating
TA_125 Grade(4) SR D Ambient — –40 — 125 °C
temperature
Junction
TJ_125 Grade(4) SR P temperature TA = 125 °C –40 — 150 °C
under bias
Ambient
TA_105 Grade(4) SR D temperature — –40 — 105 °C
under bias
Operating
TJ_105 Grade(4) SR D Junction TA = 105 °C –40 — 130 °C
temperature
Core supply
VDD_LV SR P — 1.14 1.20 1.26(6) (7) V
voltage(5)
VDD_HV_IO_MAIN
VDD_HV_IO_EMMC
VDD_HV_IO_ETH0 IO supply
SR P — 3.0 — 5.5 V
VDD_HV_IO_ETH1 voltage
VDD_HV_FLA
VDD_HV_OSC
ADC supply
VDD_HV_ADV SR P — 3.0 — 5.5 V
voltage
ADC ground
VSS_HV_ADV-
SR D differential — –25 — 25 mV
VSS voltage
SAR ADC
VDD_HV_ADR_S SR P reference — 3.0 — 5.5 V
voltage
SAR ADC
VDD_HV_ADR_S- reference
SR D — — — 25 mV
VDD_HV_ADV differential
voltage
SAR ADC
ground
VSS_HV_ADR_S SR P — VSS_HV_ADV V
reference
voltage
VSS_HV_ADR_S
VSS_HV_ADR_S-
SR D differential — –25 — 25 mV
VSS_HV_ADV
voltage
Slew rate on
VRAMP_LV SR D core power VDD_LV — — 20 V/ms
supply pins
Slew rate on
VRAMP_HV SR D HV power — — — 100 V/ms
supply
I/O input
VIN SR P — 0 — 5.5 V
voltage range
Injection
current (per
pin) without Digital pins and
IINJ1 SR T –3.0 — 3.0 mA
performance analog pins
degradation(8)
(9) (10)
Dynamic
Injection
current (per
Digital pins and
IINJ2 SR D pin) with –10 — 10 mA
analog pins
performance
degradation(10)
(11)
1. The ranges in this table are design targets and actual data may vary in the given range.
2. The PRAM pipeline gasket has to be kept enabled through bit PCM*/BYP_GSKT_XBAR*_TO_PRAMC* to keep system
work at maximum speed; The maximum frequency will go to half if the pipeline gasket is bypassed.
3. Maximum operating frequency is applicable to the cores and platform of the device. See the Clock Chapter in the
Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks on the device.
4. In order to evaluate the actual difference between ambient and junction temperatures in the application, refer to
Section 5.5: Package thermal characteristics.
5. Core voltage as measured on device pin to guarantee published silicon performance.
6. Core voltage can exceed 1.26 V with the limitations provided in Section 4.2: Absolute maximum ratings, provided that
HVD134_C monitor reset is disabled.
7. 1.260 V - 1.290 V range allowed periodically for supply with sinusoidal shape and average supply value below or equal to
1.236 V at the given temperature profile.
8. Full device lifetime. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these
limits. See Section 4.2: Absolute maximum ratings for maximum input current for reliability requirements.
9. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pins is
above the supply rail, current will be injected through the clamp diode to the supply rails. For external RC network
calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.
10. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in
Section 4.8.3: I/O pad current specifications.
11. Positive and negative Dynamic current injection pulses are allowed up to this limit. See the dedicated chapters for the
different specification limits. See the Absolute Maximum Ratings table for maximum input current for reliability
requirements. Refer to the following pulses definitions: Pulse1 (ISO 7637-2:2011), Pulse 2a (ISO 7637-2:2011 5.6.2), Pulse
3a (ISO 7637-2:2011 5.6.3), Pulse 3b (ISO 7637-2:2011 5.6.3).
VDD_HV_IO_
MAIN VDD_HV_IO_ VDD_HV_IO_ VDD_HV_IO_
VDD_LV VDD_HV_ADV VDD_HV_ADR
VDD_HV_FLA ETH0 ETH1 EMMC
VDD_HV_OSC
VDD_LV(1) ok ok ok ok ok ok
VDD_HV_IO_MAIN
VDD_HV_FLA ok ok ok ok ok ok
VDD_HV_OSC(2)
Supply1
During power-up, all functional terminals are maintained in a known state as described in
the device pinout Microsoft Excel file attached to the IO_Definition document.
C TJ = 40 °C — — 24
D TJ = 25 °C — — 16
D Leakage current on the TJ = 55 °C — — 36
IDD_LKG(2),(3) CC mA
D VDD_LV supply TJ = 95 °C — — 110
D TJ = 120 °C — — 220
P TJ = 150 °C — — 500
Dynamic current on
the VDD_LV supply,
IDD_LV(3) CC P — — — 550 mA
very high consumption
profile(4)
Total current on the
IDD_HV CC P fMAX — — 100 mA
VDD_HV supply(4)
Dynamic current on
IDD_LV_GW CC T the VDD_LV supply, — — — 350 mA
gateway profile(5)
Dynamic current on
IDD_HV_GW CC T the VDD_HV supply, — — — 35 mA
gateway profile(5),(6)
Dynamic current on
IDD_LV_BCM CC T the VDD_LV supply, — — — 285 mA
body profile(7)
Dynamic current on
IDD_HV_BCM CC T the VDD_HV supply, — — — 40 mA
body profile(7),(6)
Main Core dynamic
IDD_MAIN_CORE_AC CC T fMAX — — 55 mA
current(8)
Checker Core dynamic
IDD_CHKR_CORE_AC CC T fMAX — — 35 mA
operating current
HSM platform dynamic
IDD_HSM_AC CC T fMAX/2 — — 30 mA
operating current(9)
Dynamic current on
the VDD_LV supply
IDDHALT(10) CC T — — 106 150 mA
+Total current on the
VDD_HV supply
Dynamic current on
the VDD_LV supply
IDDSTOP(11) CC T — — 14.5 60 mA
+Total current on the
VDD_HV supply
D TJ = 25 °C — 130 380
C Total standby mode TJ = 40 °C — — 550 µA
(12) current on VDD_LV and
IDDSTBY8 CC D TJ = 55 °C — — 820
VDD_HV supply, 8 KB
D RAM(13) TJ = 120 °C — 1.37 4
mA
P TJ = 150 °C — 2.9 8
D TJ = 25 °C — 150 530 µA
C Total standby mode TJ = 40 °C — — 790 µA
(12) current on VDD_LV and
IDDSTBY128 CC D TJ = 55 °C — — 1.2 mA
VDD_HV supply,
D 128 KB RAM(13) TJ = 120 °C — — 5.5
mA
P TJ = 150 °C — — 11
D TJ = 25 °C — 190 680 µA
C Total standby mode TJ = 40 °C — — 1 mA
current on VDD_LV and
IDDSTBY256(12) CC D TJ = 55 °C — — 1.5
VDD_HV supply,
D 256 KB RAM(13) TJ = 120 °C — 2.3 7 mA
P TJ = 150 °C — 5 14
SSWU running over all
STANDBY period with
IDDSSWU1 CC D OPC/TU commands TJ = 40 °C — 1 3.5 mA
execution and keeping
ADC off(14)
SSWU running over all
STANDBY period with
OPC/TU/ADC
IDDSSWU2 CC D TJ = 40 °C — 3.5 5 mA
commands execution
and keeping ADC
on(15)
1. The ranges in this table are design targets and actual data may vary in the given range.
2. The leakage considered is the sum of core logic and RAM memories. The contribution of analog modules is not considered,
and they are computed in the dynamic IDD_LV and IDD_HV parameters.
3. IDD_LKG (leakage current) and IDD_LV (dynamic current) are reported as separate parameters, to give an indication of the
consumption contributors. The tests used in validation, characterization and production are verifying that the total
consumption (leakage + dynamic) is lower or equal to the sum of the maximum values provided (IDD_LKG + IDD_LV). The
two parameters, measured separately, may exceed the maximum reported for each, depending on the operative conditions
and the software profile used.
4. Use case: 3 x e200Z4 @200 MHz with all locksteps on, HSM @100 MHz, all IPs clock enabled, Flash access with prefetch
disabled, Flash consumption includes parallel read and program/erase, all SARADC in continuous conversion, DMA
continuously triggered by ADC conversion, 4 DSPI / 8 CAN / 8 LINFlex / FlexRay / ENET0 / ENET1 / eMMC and OctoSPI
transmitting, RTC and STM running, 2 x EMIOS running (8 channels in OPWMT mode), FIRC, SIRC, FXOSC, PLL0-1
running. The switching activity estimated for dynamic consumption does not include I/O toggling, which is highly dependent
on the application. Details of the software configuration are available separately. The total device consumption is IDD_LV +
IDD_HV + IDD_LKG for the selected temperature.
5. GW use case: three cores running @200 MHz, no lockstep, HSM @100 MHz, INTC enabled, 1 EDMA triggered by ADC,
PLL0 @200 MHz PLL1 @200 MHz, XOSC = 8/40 MHz, FLASH read only 25%, 12 x CAN running @40 MHz data
4 Mbps/1 Mbps/500 Kbps, 2 x SARADC running @15 MHz with 16 conversion channels, ETH 1 Gbps, OctoSPI @200 Mhz
data 100 MB/sec, all other peripherals frozen.
6. IDD_HV_BCM and IDD_HV_GW consumption measured is averaged in time, by considering non-concurrent peaks from all the
IP contributors (ADCs, FLASH, PADS, PMC, TSENS, Oscillators). Please consider IDD_HV parameter as peak value. IO
consumption contribution may vary, depending on the application loads differences vs the validation board used.
7. BCM use case: two cores running @160 MHz, no lockstep, HSM @80 MHz, INTC enabled, 1 EDMA triggered by ADC,
PLL0 @200 MHz PLL1 @160 MHz, XOSC = 8/40 MHz, FLASH read only 25%, 4 x CAN running @40 MHz data 4 Mbps,
5 x DSPI running @100 MHz data 4 Mbps, 2 EMIOS running @100 MHz - 12 PWM period=3 KHz, 5 x SARADC running
@15 MHz with 23 conversion channels, 10 LIN/UART baud-rate 115200, all other peripherals frozen.
8. Dynamic consumption of one core, including the dedicated I/D-caches and I/D-MEMS contribution.
9. Dynamic consumption of the HSM module, including the dedicated memories, during the execution of Electronic Code
Book crypto algorithm on 1 block of 16 byte of shared RAM.
10. Flash in Low Power. Sysclk at 160 MHz, PLL0_PHI at 160 MHz, XTAL at 40 MHz, FIRC 16 MHz ON, RCOSC1M off.
MCAN: instances: 0, 1, 2, 3, 4, 5, 6 ON (configured but no reception or transmission), Ethernet ON (configured but no
reception or transmission), ADC ON (continuously converting). All others IPs clock-gated.
11. Sysclk = RC16 MHz, RC16 MHz ON, RC1 MHz ON, PLL OFF. All possible peripherals off and clock gated. Flash in power
down mode.
12. The consumption numbers shown here in IDD standby section are considering standby regulator specs, in case of external
regulator mode, the consumption numbers can be higher.
13. STANDBY mode: device configured for minimum consumption, RC16 MHz off, RC1 MHz on.
14. SSWU1 mode adder: FIRC = ON, SSWU clocked at 8 MHz and running over all STANDBY period, ADC off. The total
standby consumption can be obtained by adding this parameter to the IDDSTBY parameter for the selected memory size
and temperature.
15. SSWU2 mode adder: FIRC = ON, SSWU clocked at 8 MHz and running over all STANDBY period, ADC on in continuous
conversion. The total standby consumption can be obtained by adding this parameter to the IDDSTBY parameter for the
selected memory size and temperature.
Weak configuration Provides a good compromise between transition time and low electromagnetic emission.
Provides transition fast enough for the serial communication channels with controlled
Medium configuration
current to reduce electromagnetic emission.
Strong configuration Provides fast transition speed; used for fast interface.
Provides maximum speed and controlled symmetric behavior for rise and fall transition.
Very strong
Used for fast interface including Ethernet, SDMMC, OctalSPI and FlexRay interfaces
configuration
requiring fine control of rising/falling edge jitter.
Ultra strong Provides very high speed interfaces till 125 MHz. Used for fast interface including
configuration Ethernet, SDMMC, OctalSPI and FlexRay interfaces.
Input only pads These low input leakage pads are associated with the ADC channels.
These pads (LP pads) are active during STANDBY. They are configured in CMOS level
logic and this configuration cannot be changed. Moreover, when the device enters the
STANDBY mode, the pad-keeper feature can be activated for LP pads. It means that:
– if the pad voltage level is above the pad keeper high threshold, a weak pull-up resistor
Standby pads
is automatically enabled
– if the pad voltage level is below the pad keeper low threshold, a weak pull-down resistor
is automatically enabled.
For the pad-keeper high/low thresholds please consider (VDD_HV_IO_MAIN / 2) +/-20%.
Note: Each I/O pin on the device supports specific drive configurations. See the signal description
table in the device reference manual for the available drive configurations for each I/O pin.
PMC_DIG_VSIO register has to be configured to select the voltage level (3.3 V or 5.0 V) for
each IO segment.
Logic level is configurable in running mode while it is CMOS not-configurable in STANDBY
for LP (low power) pads, so if a LP pad is used to wakeup from STANDBY, it should be
configured as CMOS also in running mode in order to prevent device wrong behavior in
STANDBY.
The SPC58EHx, SPC58NHx microcontroller has many GPIOs in double bonding; this
feature is in place for all packages but FPBGA386. Indeed some IO PADS are bonded
together within the package, in order to provide different alternative functions to the same
pin/ball.
The application shall enable only one pad at a time for each pin/ball in double bonding, in
order to avoid high current consumption, due to electrical contention, and reliability issues
of the pad drivers.
Refer to the SPC58EHx, SPC58NHx IO_ definition document, where double bonded
ball/pins are clearly identified, paying attention during software design to strictly avoid the
above situation depicted of electrical contention.
VIN
VDD
VIH
VHYS
VIL
VINTERNAL
(SIUL register)
TTL
CMOS
COMMON
Weak Pull-
VDD_HV_IO = 5.0 V ±
RWPD CC D down 29 — 60 KΩ
10%
resistance
Weak Pull-
VDD_HV_IO = 3.3 V ±
RWPD CC D down 19 — 60 KΩ
10%
resistance
1. Maximum current when forcing a change in the pin level opposite to the pull configuration.
2. Minimum current when keeping the same pin level state than the pull configuration.
Note: When the device enters into standby mode, the LP pads have the input buffer switched-on.
As a consequence, if the pad input voltage VIN is VSS<VIN<VDD_HV, an additional
consumption can be measured in the VDD_HV domain. The highest consumption can be
seen around mid-range (VIN ~=VDD_HV/2), 2-3 mA depending on process, voltage and
temperature.
This situation may occur if the PAD is used as a ADC input channel, and VSS<VIN<VDD_HV.
The applications should ensure that LP pads are always set to VDD_HV or VSS, to avoid
the extra consumption. Please refer to the device pinout IO definition excel file to identify the
low-power pads which also have an ADC function.
VINTERNAL
(SIUL register)
VHYS
Vout tSKEW20-80
90%
80%
20%
10%
tR20-80
tF20-80
tR10-90
tF10-90
CL = 25 pF
VDD = 5.0 V ± 10% — — 2 MHz
Maximum output V = 3.3 V ± 10%
DD
Fmax_W CC T frequency for
Weak type PADs CL = 50 pF
VDD = 5.0 V ± 10% — — 1 MHz
VDD = 3.3 V ± 10%
CL = 25 pF
Transition time VDD = 5.0 V + 10% 25 — 120 ns
output pin VDD = 3.3 V + 10%
tTR_W CC T weak
configuration, CL = 50 pF
10%-90% VDD = 5.0 V ± 10 % 50 — 240 ns
VDD = 3.3 V ± 10 %
Difference
between rise
|tSKEW_W| CC T — — — 25 %
and fall time,
90%-10%
Maximum DC VDD = 5.0 V ± 10%
IDCMAX_W CC D — — 0.5 mA
current VDD = 3.3 V ± 10%
Sum of CL = 25 pF
— — 9
transition time VDD = 5.0 V ± 10%
20–80% output
ΣtTR20-80_V CC T ns
pin VERY CL = 15 pF
STRONG — — 9
VDD = 3.3 V ± 10%
configuration
Difference CL = 25 pF
|tSKEW_V| CC T between rise 0 — 1.2 ns
VDD = 5.0 V ± 10%
and fall delay
CL = 25 pF
1 — 6
VDD = 5.0 V ± 10%
10–90%
threshold CL = 50 pF
transition time 2 — 12
VDD = 5.0 V ± 10%
tTR_U CC T output pin ns
ULTRA CL = 25 pF
1 — 6
STRONG VDD = 3.3 V ± 10%
configuration
CL = 50 pF
2 — 11
VDD = 3.3 V ± 10%
20–80% CL = 25 pF
0.8 — 4.5
threshold VDD = 5.0 V ± 10%
transition time
tTR20-80_U CC T output pin CL = 8 pF ns
ULTRA Td = 0.25 ns
— — 1
STRONG Zo = 50 Ω
configuration VDD = 3.3 V ± 10%
TTL threshold
transition time
for output pin in
ULTRA CL = 25 pF
tTRTTL_U CC T 0.88 — 5 ns
STRONG VDD = 3.3 V ± 10%
configuration
(Ethernet
standard)
Sum of CL = 25 pF
— — 9
transition time VDD = 5.0 V ± 10%
20–80% output
ΣtTR20-80_U CC T ns
pin ULTRA CL = 15 pF
STRONG — — 9
VDD = 3.3 V ± 10%
configuration
Difference CL = 25 pF
|tSKEW_U| CC T between rise 0 — 1.2 ns
VDD = 5.0 V ± 10%
and fall delay
In order to ensure device functionality, the sum of the dynamic and static current of the I/O
on a single segment should remain below the IDYNSEG maximum value.
Pad mapping on each segment can be optimized using the pad usage information provided
on the I/O Signal Description table.
Average consumption(2)
CL = 25 pF, 50 MHz,
— — 23
VDD = 5.0 V ± 10%
RMS I/O current for ULTRA CL = 50 pF, 25 MHz,
IRMS_U CC D — — 23 mA
STRONG configuration VDD = 5.0 V ± 10%
CL = 12 pF (lumped),
— — 24
125 MHz, VDD = 3.3 V ± 10%
Dynamic consumption(3)
VDD
VDD_POR
PORST
VIH
VIL
VPORST
VDD
VIH
VHYS
VIL
internal
reset
filtered by
filtered by filtered by unknown reset
hysteresis lowpass filter lowpass filter state device under hardware reset
WFRST WFRST
WNFRST
1 2 3a 3b 3c
4.10 PLLs
Three phase-locked loop (PLL) modules are implemented to generate system, ethernet and
auxiliary clocks on the device.
Figure 7 depicts the integration of the system and auxiliary PLLs. Refer to device Reference
Manual for more detailed schematic.
IRCOSC PLL0_PHI
PLL0 PLL0_PHI1
XOSC
PLL1_PHI
PLL1
4.10.1 PLL0
4.10.2 PLL1
PLL1 is a frequency modulated PLL with Spread Spectrum Clock Generation (SSCG)
support.
4.10.3 PLL_ETH
This PLL provides a clock that is not frequency modulated to Ethernet1 IP for managing
Delay-on-Source for its Tx clock. The input sources for PLL_ETH are:
1. XOSC
2. ETH1_RX clock div1/div5 based on speed
3. Divided clock from PLL0, derived from CGM_AC2_DC1
Note: PLL_ETH is another instance of PLL0 so the electrical characteristics for PLL_ETH are
similar to PLL0, the main difference is PHI0 has to be programmed always to generate
500 MHz.
4.11 Oscillators
VDD
Channel
Sampling
Selection
RSW1 RAD
VSS_HV_ADR
RCMSW Common mode
RSW1: Channel Selection Switch Impedance switch
The above scheme can be used as approximation circuitry for external filtering definition.
All specifications in the following table valid for the full input voltage range for the analog
inputs.
SARB channels — 2
CP2 CC D Internal routing capacitance SARn 10-bit channels — 0.5 pF
SARn 12-bit channels — 1
SARn 12bit — 5
CS CC D SAR ADC sampling capacitance pF
SARn 10bit — 2
SARB channels 0 1.8
RSWn CC D Analog switches resistance SARn 10-bit channels 0 0.8 kΩ
SARn 12-bit channels 0 1.8
Run mode
— 15
VDD_HV_ADR_S ≤ 5.5 V
ADC low reference
IADCREFL(5) CC D Power Down mode µA
current — 1
VDD_HV_ADR_S ≤ 5.5 V
ADC comparator mode — 20.5
P V Run mode — 4
IADV_S(5) CC DD_HV_ADV power mA
D supply current Power Down mode — 0.04
TJ < 150 °C,
T VDD_HV_ADV > 3 V, –2 2
VDD_HV_ADR_S > 3 V
TJ < 150 °C,
P VDD_HV_ADV > 3 V, –3 3
VDD_HV_ADR_S > 3 V
Total unadjusted error LSB
TUE10 CC
in 10-bit configuration(6) TJ < 150 °C, (10b)
T VDD_HV_ADV > 3 V, –3 3
3 V > VDD_HV_ADR_S > 2 V
High frequency mode,
TJ < 150 °C,
D –3 3
VDD_HV_ADV > 3 V,
VDD_HV_ADR_S > 3 V
SPC58EHx
X — X — X X X
SPC58NHx
1. The application can select between the internal or external regulator mode, by controlling the EXTREG_SEL pin of the
device. If EXTREG_SEL is connected to VDD_HV_IO_MAIN, the external regulator mode is selected.
2. In external regulator mode, the auxiliary and clamp regulators can be optionally enabled, to support the compensation of
overshoots and undershoots in the supply. In internal regulator mode, the auxiliary and clamp regulators are always active.
3. Standby regulator is automatically activated when the device enters standby mode.
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Common Components
Power-up, before
CC P 1.12 1.20 1.28
trimming, no load
VMREG Main regulator output voltage V
After trimming,
CC P 1.08 1.18 1.23
maximum load
Main regulator current provided to
VDD_LV domain
After trimming,
VSBY CC P Standby regulator output voltage 1.02 1.06 1.26 V
maximum load
Standby regulator current
IDDSBY CC T — — — 50 mA
provided to VDD_LV domain
VDD_xxx
VHVD
VLVD
TVMFILTER TVMFILTER
HVD TRIGGER
(INTERNAL)
TVMFILTER TVMFILTER
LVD TRIGGER
(INTERNAL)
PowerOn Reset HV
VPOR200_C CC P VDD_HV_IO_MAIN — 1.80 2.18 2.40 V
Minimum Voltage Detectors HV
VMVD270_C CC P VDD_HV_IO_MAIN — 2.71 2.76 2.80 V
VMVD270_F CC P VDD_HV_FLA — 2.71 2.76 2.80 V
VMVD270_SBY CC P VDD_HV_IO_MAIN (in Standby) — 2.71 2.76 2.80 V
Low Voltage Detectors HV
VLVD290_C CC P VDD_HV_IO_MAIN — 2.89 2.94 2.99 V
VLVD290_F CC P VDD_HV_FLA — 2.89 2.94 2.99 V
VLVD290_IE CC P VDD_HV_EMMC — 2.89 2.94 2.99 V
VLVD290_AS CC P VDD_HV_ADV (ADCSAR pad) — 2.89 2.94 2.99 V
VLVD290_IE1 CC P VDD_HV_IO_ETH1 — 2.89 2.94 2.99 V
1. Even if LVD/HVD monitor reaction is configurable, the application ensures that the device remains in the operative
condition range, and the internal LVDx monitors are disabled by the application. Then an external voltage monitor with
minimum threshold of VDD_LV(min) = 1.08 V measured at the device pad, has to be implemented.
For HVDx, if the application disables them, then they need to grant that VDD_LV and VDD_HV voltage levels stay withing
the limitations provided in Section 4.2: Absolute maximum ratings.
2. The values reported are Trimmed values, where applicable.
3. See Figure 12. Transitions shorter than minimum are filtered. Transitions longer than maximum are not filtered, and will be
delayed by TVMFILTER time. Transitions between minimum and maximum can be filtered or not filtered, according to
temperature, process and voltage variations.
0 f < 30
1 f < 60
2 f < 90
(1)
000 3 f < 120
4 f < 150
5 f < 180
6 f < 200
0 f < 30
1 f < 60
2 f < 90
100(2) 3 f < 120
4 f < 150
5 f < 180
6 f < 200
2 55 <f< 80
3 55 <f< 120
(3)
001 4 55 <f< 150
5 55 <f< 180
6 55 <f< 200
1. STD pipelined.
2. No pipeline.
3. Pipeline with 1 Tck address anticipation.
Lifetime
Initial max
Symbol Characteristics(1)(2) Typical max(5) Unit
Typ(3) C end of C
All
25 °C life(4) < 1 K < 250 K
(6) temp C
(7) cycles cycles
Lifetime
Initial max
Symbol Characteristics (1)(2) Typical max(5) Unit
Typ(3) C end of C
All
25 °C life(4) < 1 K < 250 K
(6) temp C
(7) cycles cycles
5. Lifetime maximum program & erase times apply across the voltages and temperatures and occur after the specified
number of program/erase cycles. These maximum values are characterized but not tested or guaranteed.
6. Initial factory condition: < 100 program/erase cycles, 25 °C typical junction temperature and nominal (± 5%) supply
voltages.
7. Initial maximum “All temp” program and erase times provide guidance for time-out limits used in the factory and apply for
less than or equal to 100 program or erase cycles, –40 °C < TJ < 150 °C junction temperature and nominal (± 5%) supply
voltages.
8. Rate computed based on 256 KB sectors.
9. Only code sectors, not including EEPROM.
10. Time between suspend resume and next suspend. Value stated actually represents Min value specification.
11. Timings guaranteed by design.
12. AIC is done using system clock, thus all timing is dependent on system frequency and number of wait states. Timing in the
table is calculated at max frequency.
All the Flash operations require the presence of the system clock for internal
synchronization. About 50 synchronization cycles are needed: this means that the timings of
the previous table can be longer if a low frequency system clock is used.
4.16 AC Specifications
All AC timing specifications are valid up to 150 °C, except where explicitly noted.
TCK
2
3 2
1 3
TCK
TMS, TDI
7 8
TDO
TCK
10
JCOMP
TCK
11 13
Output
Signals
12
Output
Signals
14
15
Input
Signals
MCKO
6
MDO
MSEO Output Data Valid
EVTO
TCK
EVTI
EVTO 9
TCK
EVTI
EVTO 9 7 7
8 8
TCK
11
13
12
14
TMS, TDI
15
16
TDO
IRQ
1 2
D_CLKOUT
IRQ
1 2
DSPI_0, DSPI_1,
DSPI_2, DSPI_3,
10
Full duplex – Classic timing (Table 44) DSPI_6, DSPI_7,
DSPI_8, DSPI_9
DSPI_4, DSPI_5 17
DSPI_0, DSPI_1,
DSPI_2, DSPI_3,
10
Full duplex – Modified timing (Table 45) DSPI_6, DSPI_7,
DSPI_8, DSPI_9
4.16.2.1 DSPI master mode full duplex timing with CMOS pads
Table 44. DSPI CMOS master classic timing (full duplex and output only)
MTFE = 0, CPHA = 0 or 1
Condition Value(1)
# Symbol C Characteristic Unit
Pad drive(2) Load (CL) Min Max
Table 44. DSPI CMOS master classic timing (full duplex and output only)
MTFE = 0, CPHA = 0 or 1 (continued)
Condition Value(1)
# Symbol C Characteristic Unit
Pad drive(2) Load (CL) Min Max
tCSC tASC
PCSx
tSDC tSCK
SCK Output
(CPOL = 0)
tSDC
SCK Output
(CPOL = 1)
tSUI
tHI
tSUO tHO
3&6[
6&.2XWSXW
&32/
6&.2XWSXW
&3 2/
W68, W+,
W682 W+2
tPCSC tPASC
PCSS
PCSx
Table 45. DSPI CMOS master modified timing (full duplex and output only)
MTFE = 1, CPHA = 0 or 1
Condition Value(1)
# Symbol C Characteristic Unit
Pad drive(2) Load (CL) Min Max
Table 45. DSPI CMOS master modified timing (full duplex and output only)
MTFE = 1, CPHA = 0 or 1 (continued)
Condition Value(1)
# Symbol C Characteristic Unit
Pad drive(2) Load (CL) Min Max
Table 45. DSPI CMOS master modified timing (full duplex and output only)
MTFE = 1, CPHA = 0 or 1 (continued)
Condition Value(1)
# Symbol C Characteristic Unit
Pad drive(2) Load (CL) Min Max
10. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.
tCSC tASC
PCSx
tSDC tSCK
SCK Output
(CPOL = 0)
tSDC
SCK Output
(CPOL = 1)
tSUI
tHI
tSUO tHO
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
tSUO tHO
tPCSC tPASC
PCSS
PCSx
Table 46. DSPI CMOS slave timing — full duplex — normal and modified transfer formats
(MTFE = 0/1)
Condition
# Symbol C Characteristic Min Max Unit
Pad Drive Load
Figure 28. DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 0
tASC
tCSC
SS
tSCK
SCK Input
(CPOL = 1)
tA tSUO tHO
tDIS
tSUI tHI
Figure 29. DSPI slave mode — modified transfer format timing (MFTE = 0/1) CPHA = 1
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
tSUO
tA
tHO tDIS
tSUI
tHI
4.16.3.1 MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%.
There is no minimum frequency requirement. The system clock frequency must be at least
equal to or greater than the RX_CLK frequency.
Note: In the following table, all timing specifications are referenced from RX_CLK = 1.4 V to the
valid input levels, 0.8 V and 2.0 V.
M3
RX_CLK (input)
M4
RXD[3:0] (inputs)
RX_DV
RX_ER
M1 M2
M7
TX_CLK (input)
M5
M8
TXD[3:0] (outputs)
TX_EN
TX_ER
M6
CRS, COL
M9
4.16.3.4 MII and RMII serial management channel timing (MDIO and MDC)
The Ethernet functions correctly with a maximum MDC frequency of 2.5 MHz.
M14 M15
MDC (output)
M10
MDIO (output)
M11
MDIO (input)
M12
M13
4.16.3.5 MII and RMII serial management channel timing (MDIO and MDC)
The Ethernet functions correctly with a maximum MDC frequency of 2.5 MHz.
Note: In the following table, all timing specifications are referenced from MDC = 1.4 V (TTL levels)
to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is
referenced from MDC = 50% to 2.2 V/3.5 V input and output levels.
Note: In the following table, all timing specifications are referenced from MDC = 1.4 V (TTL levels)
to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is
referenced from MDC = 50% to 2.2 V/3.5 V input and output levels.
M14 M15
MDC (output)
M10
MDIO (output)
M11
MDIO (input)
M12
M13
Note: In the following table, all timing specifications are referenced from REF_CLK = 1.4 V to the
valid input levels, 0.8 V and 2.0 V.
R3
REF_CLK (input)
R4
RXD[1:0] (inputs)
CRS_DV
R1 R2
R7
REF_CLK (input)
R5
R8
TXD[1:0] (outputs)
TX_EN
R6
4.16.4.1 TxEN
TxEN
80%
20%
dCCTxENFALL dCCTxENRISE
PE_Clk
TxEN
dCCTxEN10 dCCTxEN01
4.16.4.2 TxD
TxD
dCCTxD50%
80%
50%
20%
dCCTxDFALL dCCTxDRISE
Note: In the following table, specifications valid according to FlexRay EPL 3.0.1 standard with
20%–80% levels and a 10 pF load at the end of a 50 Ohm, 1 ns stripline. Please refer to the
Very Strong I/O pad specifications.
PE_Clk*
TxD
dCCTxD10 dCCTxD01
4.16.4.3 RxD
16 5
3:1 majority voting
8 10
80 6 13.33
Limited voting on one
5 sample with configurable 16
sampling point
4 20
16 6.25
3:1 majority voting
8 12.5
100 6 16.67
Limited voting on one
5 sample with configurable 20
sampling point
4 25
PER_CLK
1 — CC D Start condition hold time 2 —
Cycle(1)
2 — CC D Clock low time 8 — PER_CLK Cycle
3 — CC D Bus free time between Start and Stop condition 4.7 — µs
4 — CC D Data hold time 0.0 — ns
5 — CC D Clock high time 4 — PER_CLK Cycle
6 — CC D Data setup time 0.0 — ns
7 — CC D Start condition setup time (for repeated start condition only) 2 — PER_CLK Cycle
8 — CC D Stop condition setup time 2 — PER_CLK Cycle
1. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the
device reference manual for more detail.
• Output parameters are valid for CL = 25 pF, where CL is the external load to the device
(lumped). The internal package capacitance is accounted for, and does not need to be
subtracted from the 25 pF value.
• Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may
reduce operating speeds and may cause incorrect operation.
• Programming the IBFD register (I2C bus Frequency Divider) with the maximum
frequency results in the minimum output timings listed. The I2C interface is designed to scale
the data transition time, moving it to the middle of the SCL low period. The actual position is
affected by the pre-scale and division values programmed in the IBC field of the IBFD
register.
PER_CLK
1 — CC D Start condition hold time 6 —
Cycle(1)
2 — CC D Clock low time 10 — PER_CLK Cycle
3 — CC D Bus free time between Start and Stop condition 4.7 — µs
4 — CC D Data hold time 7 — PER_CLK Cycle
5 — CC D Clock high time 10 — PER_CLK Cycle
6 — CC D Data setup time 2 — PER_CLK Cycle
7 — CC D Start condition setup time (for repeated start condition only) 20 — PER_CLK Cycle
8 — CC D Stop condition setup time 10 — PER_CLK Cycle
1. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the
device reference manual for more detail.
2 5
SCL
6 8
4
1 3
7
SDA
tw(CKH) 45 — 55 ns
OctoSPI clock high and
—
tw(CKL) low time 45 — 55
5 Package information
eTQFP144 Production
eLQFP176 Production
FPBGA302 Production
FPBGA386 Production
OLIHDXJPHQWHG
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Note: number, dimensions and positions of grooves are for reference only.
The tolerance that controls the position of the For flange-molded packages, this tolerance also
terminal pattern with respect to Datum A and B. The applies for basic dimensions D1 and E1. For
aaa center of the tolerance zone for each terminal is packages tooled with intentional terminal tip
defined by basic dimension e as related to Datum A protrusions, aaa does not apply to those
and B. protrusions.
The bilateral profile tolerance that controls the
position of the plastic body sides. The centers of the
bbb —
profile zones are defined by the basic dimensions D
and E.
The unilateral tolerance located above the seating
This tolerance is commonly know as the
ccc plane where in the bottom surface of all terminals
“coplanarity” of the package terminals.
must be located.
The tolerance that controls the position of the
This tolerance is normally compounded with
ddd terminals to each other. The centers of the profile
tolerance zone defined by “b”.
zones are defined by basic dimension e.
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Ө 0° 3.5° 7°
Ө1 0° — —
Ө2 10° 12° 14°
Ө3 10° 12° 14°
(15)
A — — 1.60
(12)
A1 0.05 — 0.15
A2(15) 1.35 1.40 1.45
(8),(9),(11)
b 0.17 0.22 0.27
(11)
b1 0.17 0.20 0.23
c(11) 0.09 — 0.20
c1(11) 0.09 — 0.16
D(4) 26.00 BSC
(2),(5)
D1 24.00 BSC
(13)
D2 — — 8.97
D3(14) 7.30 — —
e 0.50 BSC
(4)
E 26.00 BSC
E1(2),(5) 24.00 BSC
E2(13) — — 8.97
(14)
E3 7.30 — —
L 0.45 0.60 0.75
L1 1.00 REF
N(16) 176
R1 0.08 — —
R2 0.08 — 0.20
S 0.20 —
aaa(1),(18) 0.20
(1),(18)
bbb 0.20
(1),(18)
ccc 0.08
ddd(1),(18) 0.08
Note: number, dimensions and positions of grooves are for reference only.
The tolerance that controls the position of For flange-molded packages, this tolerance
the terminal pattern with respect to Datum A also applies for basic dimensions D1 and
aaa and B. The center of the tolerance zone for E1. For packages tooled with intentional
each terminal is defined by basic dimension terminal tip protrusions, aaa does not apply
e as related to Datum A and B. to those protrusions.
The bilateral profile tolerance that controls
the position of the plastic body sides. The
bbb —
centers of the profile zones are defined by
the basic dimensions D and E.
The unilateral tolerance located above the
This tolerance is commonly know as the
ccc seating plane where in the bottom surface of
“coplanarity” of the package terminals.
all terminals must be located.
The tolerance that controls the position of
the terminals to each other. The centers of This tolerance is normally compounded with
ddd
the profile zones are defined by basic tolerance zone defined by “b”.
dimension e.
(6)
A(1) — — 1.80
A1 0.35 — —
A2 — 0.50 —
A4 — — 0.80
D 16.85 17.00 17.15
D1 — 15.20 —
E 16.85 17.00 17.15
E1 — 15.20 —
e — 0.80 —
(2)
b 0.50 0.55 0.60
Z — 0.90 —
aaa — — 0.15
bbb — — 0.10
(3)
ddd — — 0.12
eee(4) — — 0.15
(5)
fff — — 0.08
located on true position as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone. Each tolerance zone fff in the array is contained
entirely in the respective zone eee above. The axis of each ball must lie simultaneously
in both tolerance zones.
6. The terminal A1 corner must be identified on the top surface by using a corner chamfer,
ink or metalized markings, or other feature of package body or integral heats lug.
A distinguishing feature is allowable on the bottom surface of the package to identify
the terminal A1 corner. Exact shape of each corner is optional.
(6)
A(1) — — 1.8
A1 0.35 — —
A2 — 0.50 —
A4 — — 0.80
D 18.85 19.00 19.15
D1 — 16.80 —
E 18.85 19.00 19.15
E1 — 16.80 —
e — 0.80 —
(2)
b 0.50 0.55 0.60
Z — 1.10 —
aaa — — 0.15
bbb — — 0.10
(3)
ddd — — 0.12
eee(4) — — 0.15
(5)
fff — — 0.08
located on true position as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone. Each tolerance zone fff in the array is contained
entirely in the respective zone eee above. The axis of each ball must lie simultaneously
in both tolerance zones.
6. The terminal A1 corner must be identified on the top surface by using a corner chamfer,
ink or metalized markings, or other feature of package body or integral heats-lug.
A distinguishing feature is allowable on the bottom surface of the package to identify
the terminal A1 corner. Exact shape of each corner is optional.
5.5.1 eTQFP144
Table 70. Thermal characteristics for 144 exposed pad eTQFP package
Symbol C Parameter(1) Conditions Value Unit
RθJA CC D Junction-to-Ambient, Natural Convection(2) Four layer board (2s2p) 21.3 °C/W
(3)
RθJB CC D Junction-to-board — 8.1 °C/W
RθJCtop CC D Junction-to-case top(4) — 5.4 °C/W
RθJCbottom CC D Junction-to-case bottom(5) — 1 °C/W
ΨJT CC D Junction-to-package top(6) Natural convection 1 °C/W
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation
without any interface resistance.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
5.5.2 LQFP176
Table 71. Thermal characteristics for 176 exposed pad LQFP package
Symbol C Parameter(1) Conditions Value Unit
(2)
RθJA CC D Junction-to-Ambient, Natural Convection Four layer board (2s2p) 20.6 °C/W
RθJB CC D Junction-to-board(3) — 8.6 °C/W
(4)
RθJCtop CC D Junction-to-case top — 7.2 °C/W
(5)
RθJCbottom CC D Junction-to-case bottom — 1 °C/W
ΨJT CC D Junction-to-package top(6) Natural convection 1 °C/W
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation
without any interface resistance.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
5.5.3 FPBGA302
5.5.4 FPBGA386
Equation 1
TJ = TA + (RθJA * PD)
where:
TA = ambient temperature for the package (°C)
RθJA = junction-to-ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The thermal resistance values used are based on the JEDEC JESD51 series of standards
to provide consistent values for estimations and comparisons. The differences between the
values determined for the single-layer (1s) board compared to a four-layer board that has
two signal layers, a power and a ground plane (2s2p), demonstrate that the effective
thermal resistance is not a constant. The thermal resistance depends on the:
• Construction of the application board (number of planes)
• Effective size of the board which cools the component
• Quality of the thermal and electrical connections to the planes
• Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using
fewer vias to connect the package to the planes reduces the thermal performance. Thinner
planes also reduce the thermal performance. When the clearance between the vias leaves
the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for
the tightly packed printed circuit board. The value obtained on a board with the internal
planes is usually within the normal range if the application board has:
• One oz. (35 micron nominal thickness) internal planes
• Components are well separated
• Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the
surrounding components. In addition, the ambient temperature varies widely within the
application. For many natural convection and especially closed box applications, the board
temperature at the perimeter (edge) of the package is approximately the same as the local
air temperature near the device. Specifying the local ambient conditions explicitly as the
board temperature provides a more precise description of the local ambient conditions that
determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following
equation:
Equation 2
TJ = TB + (RθJB * PD)
where:
TB = board temperature for the package perimeter (°C)
RθJB = junction-to-board thermal resistance (°C/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air does not factor into the calculation, the
junction temperature is predictable if the application board is similar to the thermal test
condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance
plus a case-to-ambient thermal resistance:
Equation 3
RθJA = RθJC + RθCA
where:
RθJA = junction-to-ambient thermal resistance (°C/W)
RθJC = junction-to-case thermal resistance (°C/W)
RθCA = case to ambient thermal resistance (°C/W)
RθJC is device related and is not affected by other factors. The thermal environment can be
controlled to change the case-to-ambient thermal resistance, RθCA. For example, change
the air flow around the device, add a heat sink, change the mounting arrangement on the
printed circuit board, or change the thermal dissipation on the printed circuit board
surrounding the device. This description is most useful for packages with heat sinks where
90% of the heat flow is through the case to heat sink to ambient. For most packages, a
better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board
thermal resistance and the junction-to-case thermal resistance. The junction-to-case
thermal resistance describes when using a heat sink or where a substantial amount of heat
is dissipated from the top of the package. The junction-to-board thermal resistance
describes the thermal performance when most of the heat is conducted to the printed circuit
board. This model can be used to generate simple estimations and for computational fluid
dynamics (CFD) thermal models. More accurate compact Flotherm models can be
generated upon request.
To determine the junction temperature of the device in the application on a prototype board,
use the thermal characterization parameter (ΨJT) to determine the junction temperature by
measuring the temperature at the top center of the package case using the following
equation:
Equation 4
TJ = TT + (ΨJT x PD)
where:
TT = thermocouple temperature on top of the package (°C)
ΨJT = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured in compliance with the JESD51-2
specification using a 40-gauge type T thermocouple epoxied to the top center of the
package case. Position the thermocouple so that the thermocouple junction rests on the
package. Place a small amount of epoxy on the thermocouple junction and approximately 1
mm of wire extending from the junction. Place the thermocouple wire flat against the
package case to avoid measurement errors caused by the cooling effects of the
thermocouple wire.
When board temperature is perfectly defined below the device, it is possible to use the
thermal characterization parameter (ΨJPB) to determine the junction temperature by
measuring the temperature at the bottom center of the package case (exposed pad) using
the following equation:
Equation 5
TJ = TB + (ΨJPB x PD)
where:
TT = thermocouple temperature on bottom of the package (°C)
ΨJT = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)
6 Ordering information
Y = Tray
X = Tape and Reel (pin 1 top right)
0 = 1st version
1 = 2nd version
C = HSM medium
E = HSM full
H = HSM medium, ASIL-D
I = HSM full, ASIL-D
E5 = eTQFP144
E7 = eLQFP176
C3 = FPBGA302
C5 = FPBGA386
84 = 6 MB
90 = 8 MB
92 = 10 MB
H = SPC58xHx family
Note: Please contact your ST sales office to ask for the availability of a particular commercial
product.
Features (for instance, flash, RAM or peripherals) not included in the commercial product
cannot be used.
ST cannot be called to take any liability for features used outside the commercial product.
Partition
SPC58xH92 SPC58xH90 SPC58xH84
Start address End address
(10M) (8M) (6M)
RWR RWW
16 16 16 0 1 0x00FC0000 0x00FC3FFF
16 16 16 0 1 0x00FC4000 0x00FC7FFF
16 16 16 0 1 0x00FC8000 0x00FCBFFF
16 16 16 0 1 0x00FCC000 0x00FCFFFF
32 32 32 0 1 0x00FD0000 0x00FD7FFF
32 32 32 0 1 0x00FD8000 0x00FDFFFF
64 64 64 0 1 0x00FE0000 0x00FEFFFF
64 64 64 0 1 0x00FF0000 0x00FFFFFF
128 128 128 0 1 0x01000000 0x0101FFFF
128 128 128 0 1 0x01020000 0x0103FFFF
256 256 256 0 1 0x01040000 0x0107FFFF
256 256 256 0 1 0x01080000 0x010BFFFF
256 256 256 0 1 0x010C0000 0x010FFFFF
256 256 256 0 1 0x01100000 0x0113FFFF
256 256 256 0 1 0x01140000 0x0117FFFF
256 256 256 0 1 0x01180000 0x011BFFFF
256 256 256 0 4 0x011C0000 0x011FFFFF
256 256 256 0 4 0x01200000 0x0123FFFF
256 256 256 0 4 0x01240000 0x0127FFFF
256 256 256 0 4 0x01280000 0x012BFFFF
256 256 — 0 4 0x012C0000 0x012FFFFF
256 256 — 0 4 0x01300000 0x0133FFFF
256 — — 0 4 0x01340000 0x0137FFFF
256 — — 0 4 0x01380000 0x013BFFFF
256 256 256 1 5 0x013C0000 0x013FFFFF
256 256 256 1 5 0x01400000 0x0143FFFF
256 256 256 1 5 0x01440000 0x0147FFFF
256 256 256 1 5 0x01480000 0x014BFFFF
Partition
SPC58xH92 SPC58xH90 SPC58xH84
Start address End address
(10M) (8M) (6M)
RWR RWW
Partition
SPC58xH92 SPC58xH90 SPC58xH84
Start address End address
(10M) (8M) (6M)
RWR RWW
16 16 16 0 1 0x00FC0000 0x00FC3FFF
16 16 16 0 1 0x00FC4000 0x00FC7FFF
16 16 16 0 1 0x00FC8000 0x00FCBFFF
16 16 16 0 1 0x00FCC000 0x00FCFFFF
32 32 32 0 1 0x00FD0000 0x00FD7FFF
32 32 32 0 1 0x00FD8000 0x00FDFFFF
64 64 64 0 1 0x00FE0000 0x00FEFFFF
Partition
SPC58xH92 SPC58xH90 SPC58xH84
Start address End address
(10M) (8M) (6M)
RWR RWW
64 64 64 0 1 0x00FF0000 0x00FFFFFF
128 128 128 0 1 0x01000000 0x0101FFFF
128 128 128 0 1 0x01020000 0x0103FFFF
256 256 256 0 1 0x01040000 0x0107FFFF
256 256 256 0 1 0x01080000 0x010BFFFF
256 256 256 0 1 0x010C0000 0x010FFFFF
256 256 256 0 1 0x01100000 0x0113FFFF
256 256 256 0 1 0x01140000 0x0117FFFF
256 256 256 0 1 0x01180000 0x011BFFFF
256 256 256 0 4 0x011C0000 0x011FFFFF
256 256 256 0 4 0x01200000 0x0123FFFF
256 256 256 0 4 0x01240000 0x0127FFFF
256 256 256 0 4 0x01280000 0x012BFFFF
256 256 256 0 4 0x012C0000 0x012FFFFF
256 256 256 0 4 0x01300000 0x0133FFFF
256 256 256 0 4 0x01340000 0x0137FFFF
256 256 256 0 4 0x01380000 0x013BFFFF
256 256 256 1 5 0x013C0000 0x013FFFFF
256 256 256 1 5 0x01400000 0x0143FFFF
256 256 256 1 5 0x01440000 0x0147FFFF
256 256 256 1 5 0x01480000 0x014BFFFF
256 256 256 1 5 0x014C0000 0x014FFFFF
256 256 256 1 5 0x01500000 0x0153FFFF
256 256 256 1 5 0x01540000 0x0157FFFF
256 256 256 1 5 0x01580000 0x015BFFFF
256 256 — 0 6 0x015C0000 0x015FFFFF
256 256 — 0 6 0x01600000 0x0163FFFF
256 256 — 0 6 0x01640000 0x0167FFFF
256 256 — 0 6 0x01680000 0x016BFFFF
256 256 — 0 6 0x016C0000 0x016FFFFF
256 256 — 0 6 0x01700000 0x0173FFFF
256 256 — 0 6 0x01740000 0x0177FFFF
256 256 — 0 6 0x01780000 0x017BFFFF
Partition
SPC58xH92 SPC58xH90 SPC58xH84
Start address End address
(10M) (8M) (6M)
RWR RWW
7 Revision history
Throughout document:
Replaced SPC58xEx by SPC58xHx
Formatting and editorial changes.
Features:
– Removed bullet “Power supply options selectable via GPIO for BGA packages:”.
– Replaced “12 MCAN” by “16 MCAN”
– Replaced “eMMC rev 4.5.1 module” by “SD/SDIO/eMMC”.
– Added “with double Chip Select” to OctalSPI module.
– Removed USB ULPI.
26-Mar-2019 3
– Replaced “10/100 Mbps/ Gbps” by “,one 10/100Mbps and the other one
10/100Mbps or 1Gbps,
– Replaced “10/100 Mbps/ Gbps” by “,one 10/100Mbps and the other one
10/100Mbps or 1Gbps,”
– Replaced “One I2C module” by “Four I2C module”.
– Added “Two PSI5 modules” to Communication interfaces bullet.
– Changed bullet “Flexible power supply options:” to “Low power supply options:”, and
removed “Single internal SMPS regulator (FPBGA302 and FPBGA386)” and added
“external low voltage supply (1.2V)” to this bullet.
– Removed bullet “One I2S module” from Communication interfaces bullet
– Replaced bullet “182 KB HSM...(144 KB code + 32 KB data)” by “224 KB
HSM...(192 KB code + 32 KB data)”
– Removed bullet “One I2S module” from Communication interfaces bullet
– Added “1 deserial...low power mode” in Communication interfaces bullet
Chapter 1: Introduction:
Section 1.3: Device feature summary:
Table 2: Features list:
– “HyperBus” removed
– Changed “Octal SPI” by “Octal SPI w/ HyperBus support”
– Other - SMPS deleted.
– Other - eMMC changed by SDMMC.
– Removed all table notes.
– Changed MCAN, I2C, OctalSPI description.
– Removed SIPI/LFAST, USB, HyperBus and SMPS features.
– Updated row headed User Flash.
– Updated row headed Security Flash.
– Updated row headed DSPI.
– Removed I2S feature.
– Added sentence “Used for fast interface including Ethernet, SDMMC, OctalSPI and
FlexRay interfaces” to Ultra strong configuration description
– Removed “Differential configuration” row.
– Updated Standby pads description.
Table 14: STRONG/FAST I/O output characteristics:
Updated values for tTR_S for condition CL = 25 pF and CL = 50 pF
Throughout document:
Formatting and editorial changes.
Table 66: eLQFP176 package mechanical data: updated table, notes and numbering.
Moved notes to new section Section 5.2.1: Package mechanical drawings and data
information.
Table 68: FPBGA302 package mechanical data: updated table, notes and numbering.
Moved notes to new section Section 5.3.1: Package mechanical drawings and data
information.
Table 69: FPBGA386 package mechanical data: updated table, notes and numbering.
Moved notes to new section Section 5.4.1: Package mechanical drawings and data
information
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Product is not to be used following exposure greater than or equal to 50 KRAD silicon Total Ionizing Dose, for military applications, or for
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