Lab 06 Nitro

CMP3020
VLSI
Lab6:
FloorPlanning
Place & Route
Agenda
1. Use Script for power planning Nitro-SoC
2. CTS Nitro-SoC
3. Reports Nitro-SoC
4. Export Nitro-SoC
1. Setup…Folder Structure
• Folder Structure
• Constraints & lib_data 🡪 are same as Lab2

• Work 🡪 empty folder to start our Nitro from
• Clean_nitro.sh 🡪 our cleanup script
• variables 🡪 Contains the main script files that we will change with our data.
• save_design.sh → file used to save design to gds format.
1. Setup…Folder Structure
• Folder Structure
• Download the new “save_design.sh” and replace the old one

• in lib_data extract (uncompress) “NangateOpenCellLibrary_PDKv1_3_v2010_12”
• Update save_design.sh with the new extracted folder path
2.1. Update scripts “import_variables”
• In variables Folder:
• import_variables.tcl 🡪 You need to modify with your source, library and
constraints paths. (if needed)
• floorplan_variables.tcl 🡪 parameters need to be set for floorplanning.
🡪 set power planning to false.
• flow_variables.tcl 🡪 variables required for the rest of the flow.
2.2 Update “floorplan_variables”
• In this step, we will allow power
planning through scripts.
• floorplan_variables.tcl
🡪 parameters need to be set for
floorplanning.
🡪 set power planning to true.
→ update all the values for pg as you
did in UI in the previous lab.
→ use the info in the next slide to
choose widths/ spacing
→ make steps multiple of spacing
2.2 Update “floorplan_variables”
● In lib_data/NangateOpenCellLibrary.tech.lef
you will find the specification of each metal layer,

we need three informations
1. WIDTH
2. DIRECTION
3. SPACING
Try to use each metal in the preferred direction.

2.3 Update “flow_variables”
• In this step, we will do CTS
through scripts.
• flow_variables.tcl
Change the following
• ck_buf_cell_list → CLKBUF_*
• cts_max_skew → 0.1n
• MGC_MaxRouteLayer → metal8
2.3 Update “flow_variables”
• also enable power
Optimization
• flow_variables.tcl
Change the following
• powerEffort → low
• powerCorner → corner_0_0
• leakageCorner → corner_0_0
2.4 Update “timing constraints”
• Update clock constraint to 1 ns
• create three path groups as done in oasys
group_path -name I2R -from [all_inputs]

group_path -name I2O -from [all_inputs] -to [all_outputs]
group_path -name R2O -to [all_outputs]
3. Nitro: Run …Floorplan & Placement
• Add your synthesized verilog and constraints files in place
• Update scripts in variables folder
• Clean and setup work environments
source clean_nitro.sh
cd work
3. Nitro: Run …Floorplan & Placement
• Go to work Directory, Open Nitro
nitro -log LOGs/nitro.log -journal LOGs/nitro.jou

• Run setup
setup_nrf
• Run Import Script
source flow_scripts/0_import.tcl
3. Nitro: Run …GUI…Check & Save
• Open GUI
start
• Check_design
check_design (press F2 to open results in separate window)
Modify problematic strips in power grid

• Save design
write_db -file db/import.db

3. Nitro: Run …Optimize Placement
• Open GUI
source flow_scripts/1_place.tcl > LOGs/place.log
• Run design check
check_design (Press F2 to view errors)

• Save database
write_db -file db/place.db
• View placement report

report_placement
3. Nitro: Run …Optimize Clock
• Open GUI
source flow_scripts/2_clock.tcl > LOGs/clock.log

• View routed clock tree
• Save report
write_db -file db/clock.db
3. Nitro: Run …Optimize Clock
3. Nitro: Run …Optimize Routing
• Open GUI
source flow_scripts/3_route.tcl > LOGs/route.log

• Save database
write_db -file db/route.db
• View timing report

report_timing
3. Nitro: Run …Optimize Routing
•
3. Nitro: View Reports
• Check setup worst case
report_timing -max_delay
• Check hold worst case
report_timing -min_delay
• Check placement/area
report_placement
• Check power
report_power
3. Nitro: Save..
• Save Design
write_db -file db/route.db

• Add filler Cells
source flow_scripts/4_export.tcl
• Finalize and Save results

source ../save_design.sh
3. Nitro: Output
dbs & db → contains saved snapshots of the design, in case you want to start from intermediate state
*.v & *.sdf → used with modelsim to perform post-routing simulation with timing delay
reports → contains timing & physical reports after each stage
*.gds → contains the final layout to be used for DRC/LVS/PEX/…etc using calibre
output → contains the verilog/lef/def representing the circuit, in case it is used as a macro with another circuit
3. Nitro … Tips
You can check/uncheck those 4 icons to choose the

info/error/warnings/critical errors displayed
Never ignore an error or critical error

3. Nitro … Tips
● Sometimes Nitro run out of space and shutdown, that’s why we
use the saved designs. to continue the flow open the design from
the “db” folder, the one you saved by hand.
● if you forget to save it you can use the versions in “dbs” folder but
you have to import “libs.db” first, then the instance you want, then
you have to read constraints.
● only one design can be loaded at a time, any problem will

probably close nitro and reopen it
● if you modified the .tcl files during run, you will need to modify the
ones in the “flow_script” folder and in the “work” folder.
3. Nitro … Tips
• All steps made through UI are written in the transcript, you might
consider saving it
• Repeating the commands doesn’t always guarantee generating same
results, Saving design is essential.
• Port Editor has a bug and sometimes doesn’t show all Ports
• Always use check_design to make sure you didn’t mess up something
• Always read error and warnings, they are reported for a reason ☺
• Some errors and warnings can be ignored safely
• Always direct the ouput of scripts to a file to help you in later tracing
4. Modelsim: Post-routing simulation
• Create project, and add file to it

• Add multiplier.route.v and NangateOpenCellLibrary.v to project
• Add sdf file to project
• Compile Files
• run simulation using sdf file
vsim <toplevelModuleName> -t ps -sdfmax <path2sdfFile>
vsim integrationMult -t ps -sdfmax /somepath/multiplier.sdf

4. Calibre: open layout
• from a new terminal run calibre
calibredrv -m <generatedGDSfile.gds>
calibredrv -m integrationMult.gds
Cell-Based ASIC Design Flow
RTL Verify
VHDL/Verilog Function
Synthesis using Oasys-RTL Simulation using ModelSim
DFT/BIST Gate-Level Verify

& ATPG Netlist Function
Test vectors Simulation using ModelSim
Layout Netlist & sdf

Physical
DRC & LVS Verify
Layout
Verification Timing
Map/Place/Route
FP, P&R using Nitro SoC Simulation using ModelSim

Tape out (IC Mask Data)
5. Requirement
1- run the flow as instructed in the slides.

2- simulate generated design with modelsim using sdf file.
3- In flow_variables.tcl change max routing layer to metal6,
modify the power routing according and repeat the flow.
4- simulate generated design with modelsim using sdf file.
5- compare both designs in terms of area,utilization,
power,worst slack after place,clock,routing,export stages
Thank You
4. Next Time and Additions
• Nitro-SoC
• Prioritize Clock and use Clock Tree Synthesize
• Get Statistics out of Nitro
• Export GDSII File to perform physical verification.
• Calibre
• Extras If We have time
• Nitro-Soc
• Manual Floor Planning
• Adding Ready Made components and using Def files
• Oasys-RTL:
• Design Space Exploration
• Scan Chains
• Several libraries optimization
Export GDSII
1. Configure the tool to read library GDS
(preferably only the gds you need not the whole library)
a. report_stream_lib
This command will display the used cells and whether the source is just LEF file or GDS.
b. config_stream_lib -common { path2file/AND2_X1.gds path2file/INV_X1.gds }
This command will read in the gds files needed
c. report_stream_lib
Export GDSII
2. Add Layer Mapping
a. report_stream_layer_map
This command will display the mapping of the layers, at the beginning you will find the
whole table empty
b. source pathto/LayerMapping.tcl
This command will map metals and vias to Layer numbers that GDSII can understand.
c. report_stream_layer_map
Now the tables have some
numbers
Export GDSII
2. Write GDSII file
a. write_stream -file pathto/output.gds
now your design is exported as a GDS in the folder you specified into
“pathto” with the name “output.gds” please do change the names for your
convenience

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CMP3020

• Constraints & lib_data 🡪 are same as Lab2

• Download the new “save_design.sh” and replace the old one

you will find the specification of each metal layer,

Try to use each metal in the preferred direction.

group_path -name I2R -from [all_inputs]

• Update scripts in variables folder

• Clean and setup work environments

nitro -log LOGs/nitro.log -journal LOGs/nitro.jou

check_design (press F2 to open results in separate window)

Modify problematic strips in power grid

write_db -file db/import.db

check_design (Press F2 to view errors)

• View placement report

check_design (Press F2 to view errors)

check_design (Press F2 to view errors)

• View timing report

write_db -file db/route.db

• Finalize and Save results

You can check/uncheck those 4 icons to choose the

Never ignore an error or critical error

● only one design can be loaded at a time, any problem will

• Create project, and add file to it

vsim <toplevelModuleName> -t ps -sdfmax <path2sdfFile>

vsim integrationMult -t ps -sdfmax /somepath/multiplier.sdf

• from a new terminal run calibre

Synthesis using Oasys-RTL Simulation using ModelSim

DFT/BIST Gate-Level Verify

Test vectors Simulation using ModelSim

Layout Netlist & sdf

FP, P&R using Nitro SoC Simulation using ModelSim

1- run the flow as instructed in the slides.

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