CAO Unit-2 Entire Notes
CAO Unit-2 Entire Notes
CAO Unit-2 Entire Notes
UNIT
Outline
Figure: Subtraction
of Numbers in
Twos Complement
Representation (M
- S)
Figure: Block Diagram of Hardware for
Addition and Subtraction
Integer multiplication
• Compared with addition and subtraction,
multiplication is a complex operation, whether
performed in hardware or software.
• unsigned integers
Observation during multiplication
UNIT III
Computer Data Representation
Basic computer data types.
The data types found in the registers of digital computers may be classified as being
one of the following categories:
(1) numbers used in arithmetic computations
(2) letters of the alphabet used in data processing
(3) Other discrete symbols used for specific purposes.
All types of data, except binary numbers, are represented in computer registers in
binary-coded form.
This is because registers are made up of flip-flops and flip-flops are two-state devices
that can store only 1's and 0's.
Number System:
Radix
Uses R distinct symbols for each digit.
Example AR = an-1 an-2 ... a1 a0 .a-1…a-m.
Radix point (.) separates the integer portion and the fractional portion.
Example:
R = 10 Decimal number system, R = 2 Binary
R = 8 Octal, R = 16 Hexadecimal
1. Decimal
The decimal number system in everyday use employs the radix 10 system.
The 10 symbols are 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9.
Example
The string of digits 724.5 is interpreted to represent the quantity
7 x 102 + 2 x 101 + 4 x 10° + 5 x 10-1
that is, 7 hundreds, plus 2 tens, plus 4 units, plus 5 tenths.
Every decimal number can be similarly interpreted to find the quantity it
represents.
2. Binary
The binary number system uses the radix 2.
The two digit symbols used are 0 and 1. The string of digits 101101 is
interpreted to represent the quantity
1 x 25 + 0 x 24 + 1 x 23 + 1 x 22 + 0 x 21 + 1 x 2° = 45
To distinguish between different radix numbers, the digits will be enclosed in
parentheses and the radix of the number inserted as a subscript.
For example,
to show the equality between decimal and binary forty-five we will write
(101101)2 = (45)10.
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3. Octal
Octal number system uses the (radix 8).
The eight symbols of the octal system are 0, 1, 2, 3, 4, 5, 6, and 7.
For example, octal 736.4 is converted to decimal as follows:
(736.4)8 = 7 x 82 + 3 x 81 + 6 x 8° + 4 x 8-1
= 7 x 64 + 3 x 8 + 6 x 1 + 4/8 = (478.5)10
4. Hexadecimal
Hexadecimal number system uses the (radix 16).
The 16 symbols of the hexadecimal system are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C,
D, E, and F.
Hexadecimal digits, the symbols A, B, C, D, E, and F correspond to the decimal
numbers 10, 11, 12, 13, 14, and 15, respectively.
The equivalent decimal number of hexadecimal F3 is obtained from the
following calculation:
(F3)16 = F x 16 + 3 = 15 x 16 + 3 = (243)10
(r —1)'s Complement
9's complement
Given a number N in base r having n digits, the (r - 1)'s complement of N is
defined as (rn - 1) - N. For decimal numbers r = 10 and r - 1 = 9, so the 9's
complement of N is (10" - 1) - N.
Now, 10n represents a number that consists of a single 1 followed by n 0's.
10n- 1 is a number represented by n 9's.
For example, with n = 4 we have 104 = 10000 and 104 - 1 = 9999.
It follows that the 9's complement of a decimal number is obtained by
subtracting each digit from 9.
For example, the 9's complement of 546700 is 999999 - 546700 =453299 and
the 9's complement of 12389 is 99999 - 12389 = 87610.
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1's complement
For binary numbers, r = 2 and r - 1 = 1, so the 1's complement of N is (2" - 1) - N.
Again, 2n is represented by a binary number that consists of a 1 followed by n
0's.
2n - 1 is a binary number represented by n 1's.
For example, with n = 4, we have 24 = (10000)2 and 24 - 1 = (1111)2.
Thus the 1's complement of a binary number is obtained by subtracting each
digit from 1.
However, the subtraction of a binary digit from 1 causes the bit to change from
0 to 1 or from 1 to 0.
Therefore, the 1's complement of a binary number is formed by changing 1's
into 0's and 0's into 1's.
For example, the 1's complement of 1011001 is 0100110 and the 1's
complement of 0001111 is 1110000.
(r's) Complement
The r's complement of an n-digit number N in base r is defined as r" - N for N≠0 and 0
for N = 0.
Comparing with the (r - 1)'s complement, we note that the r's complement is obtained
by adding 1 to the (r -1)'s complement since r" - N = [(r" - 1) - N] + 1.
10's complement
Thus the 10's complement of the decimal 2389 is 7610 + 1 = 7611 and is
obtained by adding 1 to the 9's complement value.
2's complement
The 2's complement of binary 101100 is 010011 + 1 = 010100 and is obtained
by adding 1 to the 1's complement value.
2's complement notation solves the problem of the relationship between
positive and negative numbers, and achieves accurate results in subtractions.
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For example, the subtraction 72532 - 13250 = 59282. The 10's complement of 13250 is
86750.
M = 72532
10's complement of N = + 86750
Sum = 159282
Discard end carry 105 = - 100000
Answer = 59282
Now consider an example with M < N. The subtraction 13250 – 72532 produces
negative 59282. Using the procedure with complements, we have
M = 13250
10's complement of N = + 27468
Sum = 159282
Subtraction with complements is done with binary numbers in a similar manner using
the same procedure outlined above.
Y = 1000011
2's complement of X +
= 0101100
Sum =
1101111
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In the other two representations, the negative number is represented in either the 1's
or 2's complement of its positive value.
As an example, consider the signed number 14 stored in an 8-bit register.
1. In signed-magnitude representation 1 0001110
2. In signed-1's complement representation 1 1110001
3. In signed-2's complement representation 1 1110010
The signed-magnitude representation of -14 is obtained from +14 by complementing
only the sign bit.
The signed-1's complement representation of -14 is obtained by complementing all the
bits of +14, including the sign bit.
The signed-2's complement representation is obtained by taking the 2's complement of
the positive number, including its sign bit.
Arithmetic Addition
1. Compare their signs
2. If two signs are the same, ADD the two magnitudes - Look out for an overflow
3. If not the same , compare the relative magnitudes of the numbers and then SUBTRACT
the smaller from the larger --> need a subtractor to add
4. Determine the sign of the result
+6 0000011 -6 11111010
0
+13 0000110 +13 00001101
1
+19 0001001 +7 00000111
1
+6 0000011 -6 11111010
0
-13 1111001 -13 11110011
1
-7 1111100 -19 11101101
1
In each of the four cases, the operation performed is always addition, including the
sign bits.
Any carry out of the sign bit position is discarded, and negative results are
automatically in 2's complement form.
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Arithmetic Subtraction
Arithmetic Subtraction in 2’s complement.
Take the 2's complement of the subtrahend (including the sign bit) and add it to the
minuend (including the sign bit).
A carry out of the sign bit position is discarded.
This procedure stems from the fact that a subtraction operation can be changed to an
addition operation if the sign of the subtrahend is changed.
This is demonstrated by the following relationship:
(±A) - (+B) = (±A) + ( - B)
(±A) - ( -B ) = (±A) + (+B)
But changing a positive number to a negative number is easily done by taking its 2's
complement.
The reverse is also true because the complement of a negative number in complement
form produces the equivalent positive number.
Consider the subtraction of (- 6) - (-13) = +7.
In binary with eight bits this is written as 11111010 - 11110011.
The subtraction is changed to addition by taking the 2's complement of the subtrahend
( - 1 3 ) to give (+13).
In binary this is 11111010 + 00001101 = 100000111.
Removing the end carry, we obtain the correct answer 00000111 (+7).
Overflow
When two numbers of n digits each are added and the sum occupies n + 1 digits, we
say that an overflow occurred.
An overflow is a problem in digital computers because the width of registers is finite.
A result that contains n + 1 bits cannot be accommodated in a register with a standard
length of n bits.
For this reason, many computers detect the occurrence of an overflow, and when it
occurs, a corresponding flip-flop is set which can then be checked by the user.
An overflow cannot occur after an addition if one number is positive and the other is
negative, since adding a positive number to a negative number produces a result that is
smaller than the larger of the two original numbers.
An overflow may occur if the two numbers added are either positive or both negative.
Consider the following example.
Two signed binary numbers, +70 and +80, are stored in two 8-bit registers.
The range of numbers that each register can accommodate is from binary +127 to
binary -128.
Since the sum of the two numbers is +150, it exceeds the capacity of the 8-bit register.
This is true if the numbers are either positive or both negative.
The two additions in binary are shown below together with the last two carries.
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carries: 0 1 carries: 1 0
+70 0 1000110 -70 1 0111010
+80 0 1010000 -80 1 0110000
+150 1 0010110 -150 1 0110000
Note that the 8-bit result that should have been positive has a negative sign bit and the
8-bit result that should have been negative has a positive sign bit.
If, however, the carry out of the sign bit position is taken as the sign bit of the result,
the 9-bit answer so obtained will be correct.
Since the answer cannot be accommodated within 8 bits, we say that an overflow
occurred.
An overflow condition can be detected by observing the carry into the sign bit position
and the carry out of the sign bit position.
If these two carries are not equal, an overflow condition is produced.
This is indicated in the examples where the two carries’ are explicitly shown.
If the two carries’ are applied to an exclusive-OR gate, an overflow will be detected
when the output of the gate is equal to 1.
m x 2e = +(.1001110)2 x 2+4
Normalization
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and increment, so the 2's complement is obtained from these two microoperations.
In other paths of the flowchart, the sign of the result is the same as the sign of A. so no
change in A is required. However, when A < B, the sign of the result is the complement of
the original sign of A. It is then necessary to complement A, to obtain the correct sign.
The final result is found in register A and its sign in As. The value in AVF provides an
overflow indication. The final value of E is immaterial.
Figure 7.2 shows a block diagram of the hardware for implementing the addition and
subtraction operations.
It consists of registers A and B and sign flip-flops As and Bs.
Subtraction is done by adding A to the 2's complement of B.
The output carry is transferred to flip-flop E , where it can be checked to determine the
relative magnitudes of two numbers.
The add-overflow flip-flop AVF holds the overflow bit when A and B are added.
The A register provides other microoperations that may be needed when we specify the
sequence of steps in the algorithm.
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Minuend in A Augend in A
=0 =1 =1 =0
A s ⊕ Bs A s ⊕ Bs
EA ← A+ B’ + 1
EA ← A+ B
As ≠ Bs
As ≠ Bs As = Bs
=0 =1
E AVF ← E
A≥B
A<B
≠0 =0
A ← A’ A
A← A+1 AS ← 0
As ← As ’
END
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Booth’s algorithm
Booth algorithm gives a procedure for multiplying binary integers in signed- 2’s
complement representation.
It operates on the fact that strings of 0’s in the multiplier require no addition but just
shifting, and a string of 1’s in the multiplier from bit weight 2k to weight 2m can be
treated as 2k+1 – 2m.
For example, the binary number 001110 (+14) has a string 1’s from 23 to 21 (k=3, m=1).
The number can be represented as 2k+1 – 2m. = 24 – 21 = 16 – 2 = 14. Therefore, the
multiplication M X 14, where M is the multiplicand and 14 the multiplier, can be done as
M X 2 4 – M X 2 1.
Thus the product can be obtained by shifting the binary multiplicand M four times to the
left and subtracting M shifted left once.
Multiply
Multiplicand in BR
Multiplier in QR
AC ← 0
Qn + 1 ← 0
= 10 = 01
QnQn+1
AC ← AC + BR’ + 1 = 00 AC ← AC + BR
≠0 =0
SC
END
Figure 7.3: Booth algorithm for multiplication of signed-2's complement numbers
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Prior to the shifting, the multiplicand may be added to the partial product, subtracted
from the partial, or left unchanged according to the following rules:
1. The multiplicand is subtracted from the partial product upon encountering the
first least significant 1 in a string of 1’s in the multiplier.
2. The multiplicand is added to the partial product upon encountering the first 0 in a
string of 0’s in the multiplier.
3. The partial product does not change when multiplier bit is identical to the
previous multiplier bit.
The algorithm works for positive or negative multipliers in 2’s complement
representation.
This is because a negative multiplier ends with a string of 1’s and the last operation will
be a subtraction of the appropriate weight.
The two bits of the multiplier in Qn and Qn+1 are inspected.
If the two bits are equal to 10, it means that the first 1 in a string of 1 's has been
encountered. This requires a subtraction of the multiplicand from the partial product in
AC.
If the two bits are equal to 01, it means that the first 0 in a string of 0's has been
encountered. This requires the addition of the multiplicand to the partial product in AC.
When the two bits are equal, the partial product does not change.
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If neither of the operands is equal to zero, the process continues with the exponent
addition.
The exponent of the multiplier is in q and the adder is between exponents a and b.
It is necessary to transfer the exponents from q to a, add the two exponents, and
transfer the sum into a.
Multiplicand in BR
Multiplier in QR
=0
BR
≠0
=0
QR
AC ← 0 ≠0
a←q
a←a+b
a ← a - bias
Multiply mantissa
=0
shl AQ
A1
a←a-1
=1
END
(product is in AC)
Since both exponents are biased by the addition of a constant, the exponent sum will
have double this bias.
The correct biased exponent for the product is obtained by subtracting the bias number
from the sum.
The multiplication of the mantissas is done as in the fixed-point case with the product
residing in A and Q.
Overflow cannot occur during multiplication, so there is no need to check for it.
The product may have an underflow, so the most significant bit in A is checked. If it is a
1, the product is already normalized.
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4. Multiply the (-9) with (-13) using Booth’s algorithm. Give each
step. (Sum’14)
A numerical example of booth algorithm is shown for n=5. It shows the step-by-step
multiplication of (-9) X (-13) = +117.
9: 01001 13: 01101
1’s complement of 9: 10110 1’s complement of 13: 10010
+ 1 + 1
2’s complement of 9: 10111 (-9) 2’s complement of 13: 10011 (-13)
AC QR(-13) Qn+1 M(BR)(-9) SC Comments
00000 10011 0 10111 5 Initial value
01001 10011 0 10111 Subtraction: AC=AC+BR’+1
4
00100 11001 1 10111 Arithmetic Shift Right
00010 01100 1 10111 3 Arithmetic Shift Right
11001 01100 1 10111 Subtraction: AC=AC+BR’+1
2
11100 10110 0 10111 Arithmetic Shift Right
11110 01011 0 10111 1 Arithmetic Shift Right
00111 01011 0 10111 Subtraction: AC=AC+BR’+1
0
00011 10101 1 10111 Arithmetic Shift Right
Answer: -9 X -13 =117 => 001110101
5. Multiply the (7) with (3) using Booth’s algorithm. Give each
step.
7: 0111 3: 0011
6. Multiply the (15) with (13) using Booth’s algorithm. Give each
step.
15: 01111 13: 01101
15X13=195
AC QR(15) Qn+1 M(BR)(13) SC Comments
00000 01111 0 01101 5 Initial value
10011 01111 0 01101 Subtraction: AC=AC+BR’+1
4
11001 10111 1 01101 Arithmetic Shift Right
11100 11011 1 01101 3 Arithmetic Shift Right
11110 01101 1 01101 2 Arithmetic Shift Right
11111 00110 1 01101 1 Arithmetic Shift Right
01100 00110 1 01101 Addition: AC=AC+BR
0
00110 00011 1 01101 Arithmetic Shift Right
Answer: 15X13=195 => 0011000011
7. Multiply the (+15) with (-13) using Booth’s algorithm. Give each
step.
15: 01111 13: 01101
1’s complement of 13: 10010
+ 1
2’s complement of 13: 10011 (-13)
To verify 0011000010
+ 1
+195=> 0011000011
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BCD adder
BCD representation is a class of binary encodings of decimal numbers where each
decimal digit is represented by a fixed number of bits.
BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit in
BCD form.
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Floating point representation
Principles:
• The floating-point representation can implement operations for
high range values. The numerical evaluations are carried out using
floating-point values.
• The floating-point representation breaks the number into two
parts, the left-hand side is a signed, fixed-point number known as a
mantissa and the right-hand side of the number is known as the
exponent.
• For decimal numbers, we get around this limitation by using
scientific notation. Thus, 976,000,000,000,000 can be represented
as 9.76 * 1014 , and 0.0000000000000976 can be represented as
9.76 * 10-14
• This same approach can be taken with binary numbers. We can
represent a number in the form
±M * B ± E
• This number can be stored in a binary word
with three fields:
■ Sign: plus or minus
■ Significand S or Mantissa M
■ Exponent E
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INSTRUCTION FORMATS
• An instruction format defines the layout of the
bits of an instruction, in terms of its constituent
fields.
• An instruction format must include an opcode
and, implicitly or explicitly, zero or more
operands.
• Each explicit operand is referenced using one of
the addressing modes.
• The format must, implicitly or explicitly, indicate
the addressing mode for each operand.
Instruction Length
• The most basic design issue to be faced is the
instruction format length.
• This decision is affected by memory size,
memory organization, bus structure,
processor complexity, and processor speed.
• This decision determines the richness and
flexibility of the machine as seen by the
assembly-language programmer.
• The most obvious trade-off here is between the
desire for a powerful instruction set and a need
to save space.
• Programmers want more opcodes, more
operands, more addressing modes, and greater
address range.
• More opcodes and more operands make life
easier for the programmer, because shorter
programs can be written to accomplish given
tasks.
• Similarly, more addressing modes give the
programmer greater flexibility in implementing
certain functions, such as table manipulations
and multiple- way branching.
• With the increase in main memory size and
the increasing use of virtual memory,
programmers want to be able to address
larger memory ranges.
• All of these things (opcodes, operands,
addressing modes, address range) require bits
and push in the direction of longer instruction
lengths.
• But longer instruction length may be wasteful.
• A 64-bit instruction occupies twice the space
of a 32-bit instruction.
• Either the instruction length should be equal to
the memory-transfer length (in a bus system,
databus length) or one should be a multiple of
the other.
• Memory transfer rate: This rate has not kept up
with increases in processor speed.
• The processor can execute instructions faster
than it can fetch them, then memory required
also high.
• One solution to this problem is to use cache
memory.
• Another is to use shorter instructions.
• Thus, 16-bit instructions can be fetched at twice
the rate of 32-bit instructions, but probably can
be executed less than twice as rapidly.
Allocation of Bits:
• For a given instruction length, there is clearly a trade-
off between the number of opcodes and the power of
the addressing capability. For an instruction format of a
given length, this reduces the number of bits available
for addressing.
• Use variable-length opcodes to solve this issue.
• In this approach, there is a minimum opcode length
but, for some opcodes, additional operations may be
specified by using additional bits in the instruction. For
a fixed-length instruction, this leaves fewer bits for
addressing. Thus, this feature is used for those
instructions that require fewer operands and/or less
powerful addressing.
Interrelated factors
• Number of addressing modes
• Number of operands
• Register versus memory
• Number of register sets
• Address range
• Address granularity
REGISTER ORGANIZATION
• Registers are the smaller and
the fastest accessible memory units in the central
processing unit (CPU).
• According to memory hierarchy, the registers in the
processor, function a level above the main
memory and cache memory.
• The registers used by the central unit are also called
as processor registers.
• Register organization is the arrangement of the registers in
the processor.
• The processor designers decide the organization of the
registers in a processor.
• A register can hold the instruction, address location, or
operands. Sometimes, the instruction has register as a part
of itself.
• Different processors may have different
register organization.
• Depending on the roles played by the registers
they can be categorized into two types, user-
visible register and control and status register.
Definition and purpose
• User-visible registers: Enable the machine- or
assembly language programmer to minimize
main memory references by optimizing use of
registers.
• Control and status registers: Used by the
control unit to control the operation of the
processor and by privileged, operating system
programs to control the execution of
programs.
User-Visible Registers
• A user-visible register is one that may be
referenced by means of the machine language
that the processor executes.
• These registers are visible to the assembly or
machine language programmers and they use
them effectively to minimize the memory
references in the instructions.
• These registers can only be referenced using
the machine or assembly language.
General-purpose registers
• The general-purpose registers detain both
the addresses or the data.
• The general purpose register also accepts
the intermediate results in the course of program
execution.
• The programmers can restrict some of the
general-purpose registers to specific functions.
• Like, some registers are specifically used for stack
operations or for floating-point operations.
• The general-purpose register can also be
employed for the addressing functions.
Data Register
• The term itself describes that these registers
are employed to hold the data. But the
programmers can’t use these registers
for calculating operand address.
Address Register
• Now, the address registers contain the address of
an operand or it can also act as a general-
purpose register.
• An address register may be dedicated to a
certain addressing mode.
(a) Segment Pointer Register: A memory divided in
segments, requires a segment register to hold the
base address of the segment. There can be
multiple segment registers. As one segment register
can be employed to hold the base address of the
segment occupied by the operating system. The
other segment register can hold the base address of
the segment allotted to the processor.
(b) Index Register: The index register is
employed for indexed addressing and it is initial
value is 0. Generally, it used for traversing the
memory locations. After each reference, the
index register is incremented or decremented
by 1, depending upon the nature of the
operation. Sometime the index register may
be auto indexed.
(c) Stack Pointer Register: The stack register has
the address that points the stack top. This
allows implicit addressing; that is, push, pop,
and other stack instructions need not contain an
explicit stack operand.
Condition Code
• Condition codes are the flag bits which are
the part of the control register. The condition
codes are set by the processor as a result of an
operation and they are implicitly read through
the machine instruction.
• The programmers are not allowed to alter the
conditional codes. Generally, the condition
codes are tested during conditional branch
operation.
Design issues
• Use completely general- purpose registers or
to specialize their use.
• With the use of specialized registers, it can
generally be implicit in the opcode which type
of register a certain operand specifier refers
to. The operand specifier must only identify
one of a set of specialized registers rather
than one out of all the registers, thus saving
bits. On the other hand, this specialization
limits the programmer’s flexibility.
• Number of registers: either general purpose
or data plus address, to be provided. Again,
this affects instruction set design because
more registers require more operand specifier
bits.
• Between 8 and 32 registers appears optimum.
• Register length: Registers that must hold
addresses obviously must be at least long
enough to hold the largest address. Data
registers should be able to hold values of most
data types.
Control and Status Registers
• The control and status register holds
the address or data that is important
to control the processor’s operation.
• The most important thing is that these
registers are not visible to the users.
• All the control and status registers
are essential for the execution of an
instruction.
Types
1. Program Counter
• The program counter is a processor register that holds the address
of the instruction that has to be executed next. It is a processor
which updates the program counter with the address of the next
instruction to be fetched for execution.
2. Instruction Register
• Instruction register has the instruction that is currently fetched. It
helps in analysing the opcode and operand present in the
instruction.