Features

• Single Voltage Operation

– 5V Read
– 5V Reprogramming
• Fast Read Access Time - 70 ns
• Internal Program Control and Timer
• 8K bytes Boot Block With Lockout
• Fast Erase Cycle Time - 10 seconds
• Byte By Byte Programming - 10 µs/Byte
• Hardware Data Protection
•
•
DATA Polling For End Of Program Detection
Low Power Dissipation
512K (64K x 8)
– 30 mA Active Current
– 100 µA CMOS Standby Current 5-volt Only
• Typical 10,000 Write Cycles
Flash Memory
Description
The AT49F512 is a 5-volt-only in-system programmable and erasable Flash Memory.
Its 512K of memory is organized as 65,536 words by 8 bits. Manufactured with AT49F512
Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 70
ns with a power dissipation of just 165 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 100 µA.
To allow for simple in-system reprogrammability, the AT49F512 does not require high
input voltages for programming. Five-volt-only commands determine the read and
programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49F512 is performed by erasing the
entire 512K of memory and then programming on a byte by byte basis. The typical
byte programming time is a fast 10 µs. The end of a program cycle can be optionally
(continued)
Pin Configurations DIP Top View
Pin Name Function
NC 1 32 VCC
NC 2 31 WE
A0 - A15 Addresses A15 3 30 NC
A12 4 29 A14
CE Chip Enable A7 5 28 A13
A6 6 27 A8
OE Output Enable A5 7 26 A9

WE Write Enable
A4
A3
8
9
25
24
A11
OE
512K (64K x 8)
A2 10 23 A10
I/O0 - I/O7 Data Inputs/Outputs A1
A0
11
12
22
21
CE
I/O7 5-volt Only
I/O0 13 20 I/O6
NC No Connect

VSOP Top View (8 x 14 mm) or

I/O1
I/O2
14
15
19
18
I/O5
I/O4 CMOS Flash
GND 16 17 I/O3
TSOP Top View (8 x 20 mm)
Type 1
Memory
PLCC Top View
VCC
A12
A15

A11 1 32 OE
WE
NC
NC

NC

A9 2 31 A10
A8 3 30 CE
4
3
2
1
32
31
30

A13 4 29 I/O7 A7 5 29 A14

A14 5 28 I/O6 A6 6 28 A13
NC 6 27 I/O5 A5 7 27 A8
WE 7 26 I/O4 A4 8 26 A9
VCC 8 25 I/O3 A3 9 25 A11
NC 9 24 GND A2 10 24 OE
NC 10 23 I/O2 A1 11 23 A10
A15 11 22 I/O1 A0 12 22 CE
A12 12 21 I/O0 I/O0 13 21 I/O7
14
15
16
17
18
19
20

A7 13 20 A0
Rev. 1027C–09/98
A6 14 19 A1
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6

A5 15 18 A2
A4 16 17 A3

1
detected by the DATA polling feature. Once the end of a The optional 8K bytes boot block section includes a repro-
byte program cycle has been detected, a new access for a gramming write lock out feature to provide data integrity.
read or program can begin. The typical number of program The boot sector is designed to contain user secure code,
and erase cycles is in excess of 10,000 cycles. and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.

Block Diagram

FFFFH
2000H
1FFFH
0000H

Device Operation
READ: The AT49F512 is accessed like an EPROM. When latched on the rising edge of WE or CE, whichever occurs
CE and OE are low and WE is high, the data stored at the first. Programming is completed after the specified tBP cycle
memory location determined by the address pins is time. The DATA polling feature may also be used to indicate
asserted on the outputs. The outputs are put in the high the end of a program cycle.
impedance state whenever CE or OE is high. This dual-line BOOT BLOCK PROGRAMMING LOCKOUT: The device
control gives designers flexibility in preventing bus conten- has one designated block that has a programming lockout
tion. feature. This feature prevents programming of data in the
ERASURE: Before a byte can be reprogrammed, the 64K designated block once the feature has been enabled. The
bytes memory array (or 56K bytes if the boot block featured size of the block is 8K bytes. This block, referred to as the
is used) must be erased. The erased state of the memory boot block, can contain secure code that is used to bring up
bits is a logical “1”. The entire device can be erased at one the system. Enabling the lockout feature will allow the boot
time by using a 6-byte software code. The chip erase code code to stay in the device while data in the rest of the
consists of 6-byte load commands to specific address loca- device is updated. This feature does not have to be acti-
tions with a specific data pattern (please refer to the Chip vated; the boot block’s usage as a write protected region is
Erase Cycle Waveforms). optional to the user. The address range of the boot block is
After the chip erase has been initiated, the device will inter- 0000H to 1FFFH.
nally time the erase operation so that no external clocks Once the feature is enabled, the data in the boot block can
are required. The maximum time needed to erase the no longer be erased or programmed. Data in the main
whole chip is tEC. If the boot block lockout feature has been memory block can still be changed through the regular pro-
enabled, the data in the boot sector will not be erased. gramming method. To activate the lockout feature, a series
BYTE PROGRAMMING: Once the memory array is of six program commands to specific addresses with spe-
erased, the device is programmed (to a logical “0”) on a cific data must be performed. Please refer to the Command
byte-by-byte basis. Please note that a data “0” cannot be Definitions table.
programmed back to a “1”; only erase operations can con- BOOT BLOCK LOCKOUT DETECTION: A software
vert “0”s to “1”s. Programming is accomplished via the method is available to determine if programming of the boot
internal device command register and is a 4 bus cycle block section is locked out. When the device is in the soft-
operation (please refer to the Command Definitions table). ware product identification mode (see Software Product
The device will automatically generate the required internal Identification Entry and Exit sections) a read from address
program pulses. location 00002H will show if programming the boot block is
The program cycle has addresses latched on the falling locked out. If the data on I/O0 is low, the boot block can be
edge of WE or CE, whichever occurs last, and the data programmed; if the data on I/O0 is high, the program lock-

2 AT49F512
 AT49F512

out feature has been activated and the block cannot be outputs and the next cycle may begin. DATA polling may
programmed. The software product identification code begin at any time during the program cycle.
should be used to return to standard operation. TOGGLE BIT: In addition to DATA polling the AT49F512
PRODUCT IDENTIFICATION: The product identification provides another method for determining the end of a pro-
mode identifies the device and manufacturer as Atmel. It gram or erase cycle. During a program or erase operation,
may be accessed by hardware or software operation. The successive attempts to read data from the device will result
hardware operation mode can be used by an external pro- in I/O6 toggling between one and zero. Once the program
grammer to identify the correct programming algorithm for cycle has completed, I/O6 will stop toggling and valid data
the Atmel product. will be read. Examining the toggle bit may begin at any time
For details, see Operating Modes (for hardware operation) during a program cycle.
or Software Product Identification. The manufacturer and HARDWARE DATA PROTECTION: Hardware features
device code is the same for both modes. protect against inadvertent programs to the AT49F512 in
DATA POLLING: The AT49F512 features DATA polling to the following ways: (a) VCC sense: if VCC is below 3.8V (typ-
indicate the end of a program cycle. During a program ical), the program function is inhibited. (b) Program inhibit:
cycle an attempted read of the last byte loaded will result in holding any one of OE low, CE high or WE high inhibits
the complement of the loaded data on I/O7. Once the pro- program cycles. (c) Noise filter: Pulses of less than 15 ns
gram cycle has been completed, true data is valid on all (typical) on the WE or CE inputs will not initiate a program
cycle.
Command Definition (in Hex)
Command Bus 1st Bus 2nd Bus 3rd Bus 4th Bus 5th Bus 6th Bus
Sequence Cycles Cycle Cycle Cycle Cycle Cycle Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read 1 Addr DOUT
Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
Byte Program 4 5555 AA 2AAA 55 5555 A0 Addr DIN
Boot Block
6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
Lockout(1)
Product ID
3 5555 AA 2AAA 55 5555 90
Entry
Product ID
3 5555 AA 2AAA 55 5555 F0
Exit(2)
Product ID
1 XXXX F0
Exit(2)
Notes: 1. The 8K byte boot sector has the address range 0000H to 1FFFH.
2. Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
All Input Voltages other conditions beyond those indicated in the
(including NC pins) operational sections of this specification is not
with Respect to Ground ...................................-0.6V to +6.25V implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
All Output Voltages reliability.
with Respect to Ground .............................-0.6V to VCC + 0.6V

Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V

3
DC and AC Operating Range
AT49F512-70 AT49F512-90

Operating Com. 0°C - 70°C 0°C - 70°C

Temperature (Case) Ind. -40°C - 85°C -40°C - 85°C
VCC Power Supply 5V ± 10% 5V ± 10%

Operating Modes
Mode CE OE WE Ai I/O
Read VIL VIL VIH Ai DOUT
Program(2) VIL VIH VIL Ai DIN
(1)
Standby/Write Inhibit VIH X X X High Z
Program Inhibit X X VIH
Program Inhibit X VIL X
Output Disable X VIH X High Z
Product Identification
A1 - A15 = VIL, A9 = VH, A0 = VIL(3) Manufacturer Code(4)
Hardware VIL VIL VIH
A1 - A15 = VIL, A9 = VH, A0 = VIH(3) Device Code(4)
A0 = VIL, A1 - A15 = VIL Manufacturer Code(4)
Software(5)
A0 = VIH, A1 - A15 = VIL Device Code(4)
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 03H
5. See details under Software Product Identification Entry/Exit.

DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC 10 µA
ILO Output Leakage Current VI/O = 0V to VCC 10 µA
Com. 100 µA
ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC
Ind. 300 µA
ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3 mA
Com. 30 mA
ICC(1) VCC Active Current f = 5 MHz; IOUT = 0 mA
Ind. 40 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 2.1 mA 0.45 V
VOH1 Output High Voltage IOH = -400 µA 2.4 V
VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V
Note: 1. In the erase mode, ICC is 90 mA.

4 AT49F512
 AT49F512

AC Read Characteristics
AT49F512-70 AT49F512-90
Symbol Parameter Min Max Min Max Units
tACC Address to Output Delay 70 90 ns
(1)
tCE CE to Output Delay 70 90 ns
(2)
tOE OE to Output Delay 35 0 40 ns
tDF(3)(4) CE or OE to Output Float 0 25 0 25 ns
Output Hold from OE, CE or
tOH 0 0 ns
Address, whichever occurred first

AC Read Waveforms(1)(2)(3)(4)

Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE, after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and Output Test Load

Measurement Level

tR, tF < 5 ns

Pin Capacitance
f = 1 MHz, T= 25°C(1)
Typ Max Units Conditions
CIN 4 6 pF VIN = 0V
COUT 8 12 pF VOUT = 0V
Note: 1. This parameter is characterized and is not 100% tested.

5
AC Word Load Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Set-up Time 0 ns
tAH Address Hold Time 50 ns
tCS Chip Select Set-up Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE) 90 ns
tDS Data Set-up Time 50 ns
tDH, tOEH Data, OE Hold Time 0 ns
tWPH Write Pulse Width High 90 ns

AC Byte Load Waveforms

WE Controlled

CE Controlled

6 AT49F512
 AT49F512

Program Cycle Characteristics

Symbol Parameter Min Typ Max Units
tBP Byte Programming Time 10 50 µs
tAS Address Set-up Time 0 ns
tAH Address Hold Time 50 ns
tDS Data Set-up Time 50 ns
tDH Data Hold Time 0 ns
tWP Write Pulse Width 90 ns
tWPH Write Pulse Width High 90 ns
tEC Erase Cycle Time 10 seconds

Program Cycle Waveforms

PROGRAM CYCLE

OE

CE

t t t
WP WPH BP

WE
t t t
AS AH DH

A0-A15 5555 2AAA 5555 ADDRESS

t
DS

DATA AA 55 A0 INPUT
DATA

Chip Erase Cycle Waveforms

OE

CE

t t
WP WPH
WE
t t t
AS AH DH

A0-A15 5555 2AAA 5555 5555 2AAA 5555

t t
DS EC

DATA AA 55 80 AA 55 10

BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5

Note: OE must be high only when WE and CE are both low.

7
Data Polling Characteristics(1)
Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

(2)
tOE OE to Output Delay ns

tWR Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.

Data Polling Waveforms

WE

CE

tOEH
OE
tDH tWR
tOE HIGH Z
I/O7

A0-A15 An An An An An

Toggle Bit Characteristics(1)

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay(2) ns

tOEHP OE High Pulse 150 ns

tWR Write Recovery Time 0 ns

Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.

Toggle Bit Waveforms(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s)
2. Begining and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.

8 AT49F512
 AT49F512

Software Product Boot Block

Identification Entry(1) Lockout Enable Algorithm(1)
LOAD DATA AA LOAD DATA AA
TO TO
ADDRESS 5555 ADDRESS 5555

LOAD DATA 55 LOAD DATA 55

TO TO
ADDRESS 2AAA ADDRESS 2AAA

LOAD DATA 90 LOAD DATA 80

TO TO
ADDRESS 5555 ADDRESS 5555

ENTER PRODUCT LOAD DATA AA

IDENTIFICATION TO
MODE(2)(3)(5) ADDRESS 5555

Software Product LOAD DATA 55

Identifcation Exit(1) TO
ADDRESS 2AAA
LOAD DATA AA LOAD DATA F0
TO OR TO
ADDRESS 5555 ANY ADDRESS
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA 55 EXIT PRODUCT
TO IDENTIFICATION
ADDRESS 2AAA MODE(4)
PAUSE 1 second(2)

LOAD DATA F0
TO Notes: 1. Data Format: I/O7 - I/O0 (Hex);
ADDRESS 5555 Address Format: A14 - A0 (Hex).
2. Boot block lockout feature enabled.

EXIT PRODUCT
IDENTIFICATION
MODE(4)

Notes: 1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).
2. A1 - A15 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if pow-
ered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 03H

9
Ordering Information(1)
tACC ICC (mA)
(ns) Active Standby Ordering Code Package Operation Range
70 30 0.1 AT49F512-70JC 32J Commercial
AT49F512-70PC 32P6 (0° to 70°C)
AT49F512-70TC 32T
AT49F512-70VC 32V
40 0.3 AT49F512-70JI 32J Industrial
AT49F512-70PI 32P6 (-40° to 85°C)
AT49F512-70TI 32T
AT49F512-70VI 32V
90 30 0.1 AT49F512-90JC 32J Commercial
AT49F512-90PC 32P6 (0° to 70°C)
AT49F512-90TC 32T
AT49F512-90VC 32V
40 0.3 AT49F512-90JI 32J Industrial
AT49F512-90PI 32P6 (-40° to 85°C)
AT49F512-90TI 32T
AT49F512-90VI 32V
Note: 1. The AT49F512 has as optional boot block feature. The part number shown in the Ordering Information table is for devices
with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring the boot block to be in the higher
address range should contact Atmel.

Package Type
32J 32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
32P6 32-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T 32-Lead, Thin Small Outline Package (TSOP) (8 x 20 mm)
32V 32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm)

10 AT49F512
 AT49F512

Packaging Information
32J, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC) 32P6, 32-Lead, 0.600” Wide, Plastic Dual Inline
Dimensions in Inches and (Millimeters) Package (PDIP)
JEDEC STANDARD MS-016 AE Dimensions in Inches and (Millimeters)

1.67(42.4)
.045(1.14) X 45° PIN NO. 1 .025(.635) X 30° - 45° 1.64(41.7) PIN
.012(.305) 1
IDENTIFY
.008(.203)

.530(13.5) .566(14.4)
.553(14.0)
.490(12.4) .530(13.5)
.032(.813) .547(13.9)
.595(15.1) .021(.533)
.026(.660)
.585(14.9) .013(.330)
.090(2.29)
1.500(38.10) REF MAX
.050(1.27) TYP .030(.762) .220(5.59)
.300(7.62) REF .005(.127)
.015(3.81) MAX
.430(10.9) MIN
.095(2.41)
.390(9.90) .060(1.52) SEATING
AT CONTACT .140(3.56) PLANE
POINTS .065(1.65)
.120(3.05) .161(4.09) .015(.381)
.125(3.18)
.022(.559)
.065(1.65) .014(.356)
.110(2.79) .041(1.04)
.022(.559) X 45° MAX (3X)
.090(2.29)
.630(16.0)
.453(11.5) .590(15.0)
.447(11.4) 0 REF
15
.495(12.6) .012(.305)
.485(12.3) .008(.203)
.690(17.5)
.610(15.5)

32T, 32-Lead, Plastic Thin Small Outline Package 32V, 32-Lead, Plastic Thin Small Outline Package
(TSOP) (VSOP)
Dimensions in Millimeters and (Inches) Dimensions in Millimeters (Inches)

INDEX INDEX
MARK MARK

18.5(.728) 20.2(.795) 12.5(.492) 14.2(.559)

18.3(.720) 19.8(.780) 12.3(.484) 13.8(.543)

0.50(.020)
0.50(.020) 0.25(.010)
0.25(.010) BSC 7.50(.295)
BSC 0.15(.006)
7.50(.295) 0.15(.006) REF
REF
8.10(.319)
8.20(.323) 7.90(.311) 1.20(.047) MAX
7.80(.307) 1.20(.047) MAX

0.15(.006)
0.15(.006) 0.05(.002)
0.05(.002) 0 0.20(.008)
0 5 REF
0.20(.008) 0.10(.004)
5 REF
0.10(.004)
0.70(.028)
0.70(.028) 0.50(.020)
0.50(.020)

11