481

CYM1471
CYM1481

1024K x 8 SRAM Module

2048K x 8 SRAM Module
Features words (1471) or 2048K words (1481) by 8 bits. These modules
are constructed from eight (1471) or sixteen (1481) 128K x 8
• High-density 8-/16-megabit SRAM modules SRAMs in plastic surface-mount packages on an epoxy lami-
• High-speed CMOS SRAMs nate board with pins. On-board decoding selects one of the
SRAMs from the high-order address lines, keeping the remain-
— Access time of 70 ns
ing devices in standby mode for minimum power consumption.
• Low active power
An active LOW write enable signal (WE) controls the writ-
— 605 mW (max.), 2M x 8 ing/reading operation of the memory. When MS and WE inputs
• Double-sided SMD technology are both LOW, data on the eight data input/output pins is writ-
• TTL-compatible inputs and outputs ten into the memory location specified on the address pins.
• Small footprint SIP Reading the device is accomplished by selecting the device
and enabling the outputs MS and OE active LOW while WE
— PCB layout area of 0.72 sq. in. remains inactive or HIGH. Under these conditions, the content
• 2V data retention (L version) of the location addressed by the information on the address
pins is present on the eight data input/output pins.
Functional Description
The input/output pins remain in a high-impedance state unless
The CYM1471 and CYM1481 are high-performance 8-mega- the module is selected, outputs are enabled, and write enable
bit and 16-megabit static RAM modules organized as 1024K (WE) is HIGH.

Logic Block Diagram Pin Configuration SIP

Top View
A19 1
A0–A 16
17 VCC 2
128K x 8 128K x 8 128K x 8 128K x 8 WE 3
SRAM SRAM SRAM SRAM I/O2 4
I/O3 5
OE I/O0 6
A1 7
WE A2 8
A 17–A 20 CYM1471 A3 9
A4 10
4
128K x 8 128K x 8 128K x 8 128K x 8 GND 11
1 of 8 SRAM SRAM SRAM SRAM I/O5 12
DECODER A10 13
A11 14
A5 15
MS
A13 16
A20 (1481) A14 17
18
128K x 8 128K x 8 128K x 8 128K x 8 MS (1471) MS 19
SRAM SRAM SRAM SRAM A15 20
A16 21
A12 22
A18 23
A6 24
I/O1 25
GND 26
A0 27
128K x 8 128K x 8 128K x 8 128K x 8
A7 28
SRAM SRAM SRAM SRAM
1 of 8 A8 29
DECODER A9 30
I/O7 31
I/O4 32
I/O6 33
A17 34
I/O0–I/O 7 VCC 35
8 OE
1471-1 36
1471-2

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 1990 - Revised January 2, 1997
 CYM1471
CYM1481
/

Selection Guide
CYM1471 CYM1481
Maximum Access Time (ns) 70 85 100 120 70 85 100 120
Maximum Operating Current (mA) 95 95 95 95 110 110 110 110
Maximum Standby Current (mA) 32 32 32 32 64 64 64 64

Maximum Ratings
(Above which the useful life may be impaired.) DC Input Voltage ............................................–0.3V to +7.0V
Storage Temperature ................................. –55°C to +125°C Output Current into Outputs (LOW)............................. 20 mA
Ambient Temperature with
Power Applied ................................................... 0°C to +70°C Operating Range
Supply Voltage to Ground Potential ............... –0.3V to +7.0V Ambient
Range Temperature VCC
DC Voltage Applied to Outputs
in High Z State ............................................... –0.3V to +7.0V Commercial 0°C to +70°C 5V ± 10%

Electrical Characteristics Over the Operating Range

1471 1481
Parameter Description Test Conditions Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 2.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V
VIL Input LOW Voltage –0.3 0.8 –0.3 0.8 V
IIX Input Load Current GND < V I < V CC –20 +20 –20 +20 µA
IOZ Output Leakage Current GND < VO < VCC, Output Disabled –20 +20 –20 +20 µA
ICC VCC Operating Supply VCC = Max., MS < VIL, IOUT = 0 mA 95 110 mA
Current
ISB1 Automatic MS Max. VCC, MS > VIH, 32 64 mA
Power-Down Current Min. Duty Cycle = 100%
ISB2 Automatic MS Max. VCC, MS > VCC – Standard 16 32 mA
Power-Down Current 0.2V, VIN > VCC – 0.2V, or
L Version 250 500 µA
VIN < 0.2V
–100, –120
L Version 800 1600 µA
–85

Capacitance[1]
CYM1471 CYM1481
Parameter Description Test Conditions Max. Max. Unit
CINA Input Capacitance (A0–16, OE, WE) TA = 25°C, f = 1 MHz, 75 125 pF
VCC = 5.0V
CINB Input Capacitance (A17–20, MS) 25 25 pF
COUT Output Capacitance 95 165 pF
Note:
1. Tested on a sample basis.

2
 CYM1471
CYM1481

AC Test Loads and Waveforms

R1 2530 Ω R1 2530 Ω ALL INPUT PULSES

5V 5V 3.0V
90% 90%
OUTPUT OUTPUT
R2 R2 10% 10%
100 pF 2830Ω 5 pF 2830Ω GND

INCLUDING INCLUDING < 10 ns < 10 ns

JIG AND JIG AND
SCOPE SCOPE
(a) 1471-5 (b) 1471-3 1471-4

Equivalent to: THÉVENIN EQUIVALENT

1340Ω
OUTPUT 2.64V

Switching Characteristics Over the Operating Range[2]

1471-70 1471–85 1471–100 1471–120
1481-70 1481–85 1481–100 1481–120
Parameter Description Min Max Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 70 85 100 120 ns
tAA Address to Data Valid 70 85 100 120 ns
tOHA Data Hold from Address Change 5 10 10 10 ns
tAMS MS LOW to Data Valid 70 85 100 120 ns
tDOE OE LOW to Data Valid 40 45 50 60 ns
tLZOE OE LOW to Low Z 5 5 5 5 ns
[3]
tHZOE OE HIGH to High Z 30 30 35 45 ns
[4]
tLZMS MS LOW to Low Z 5 10 10 10 ns
tHZMS MS HIGH to High Z[3, 4] 30 30 35 45 ns
[5]
WRITE CYCLE
tWC Write Cycle Time 70 85 100 120 ns
tSMS MS LOW to Write End 65 75 90 100 ns
tAW Address Set-Up to Write End 65 75 90 100 ns
tHA Address Hold from Write End 5 7 7 7 ns
tSA Address Set-Up to Write Start 0 5 5 5 ns
tPWE WE Pulse Width 65 65 75 85 ns
tSD Data Set-Up to Write End 30 35 40 45 ns
tHD Data Hold from Write End 0 5 5 5 ns
[3]
tHZWE WE LOW to High Z 30 30 35 40 ns
tLZWE WE HIGH to Low Z 5 5 5 5 ns
Notes:
2. Test conditions assume signal transition time of 10 µs or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, output loading of 1 TTL load, and
100-pF load capacitance.
3. t HZOE, tHZMS, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
4. At any given temperature and voltage condition, tHZMS is less than t LZMS for any given device. These parameters are guaranteed and not 100% tested.
5. The internal write time of the memory is defined by the overlap of MS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

3
 CYM1471
CYM1481

Data Retention Characteristics (L Version Only)

1471–100 1481–100
1471-70 1471–85 1471–120 1481-70 1481–85 1481–120
Parameter Description Test Conditions Min. Max Min. Max Min Max Min Max Min Max Min Max Unit
VDR VCC for Retention 2 2 2 2 2 2 V
Data
ICCDR Data Retention VDR = 3.0V, 400 400 125 800 800 250 µA
Current MS > VCC – 0.2V,
VIN > VCC – 0.2V
tCDR[6] Chip Deselect to 0 0 0 0 0 0 ns
or VIN < 0.2V
Data
Retention Time
tR Operation Recov- 5 5 5 5 5 5 ns
ery Time

Data Retention Waveform

DATA RETENTION MODE

VCC
4.5V VDR > 2V 4.5V

tCDR tR
VDR
VIH VIH
CS
1471-6

Switching Waveforms

Read Cycle No. 1[7, 8]

tRC

ADDRESS

tAA
tOHA

DATAOUT PREVIOUS DATA VALID DATA VALID

1471-7

Notes:
6. Guaranteed, not tested.
7. Device is continuously selected. OE, MS = VIL.
8. Address valid prior to or coincident with MS transition LOW

4
 CYM1471
CYM1481

Switching Waveforms (continued)

Read Cycle No. 2 [8, 9]

tRC
MS

tAMS
OE

tHZOE
tDOE
tHZMS
tLZOE
HIGH
HIGH IMPEDANCE IMPEDANCE
DATA OUT DATA VALID
tLZMS
1471-8

Write Cycle No. 1[5, 10]

tWC

ADDRESS

tSMS
MS

tAW tHA
tSA tPWE

WE

tSD tHD

DATA IN DATA VALID

tHZWE tLZWE
HIGH IMPEDANCE
DATA I/O DATA UNDEFINED

1471-9

Notes:
9. WE is HIGH for read cycle.
10. Data I/O is high impedance if OE = VIH.

5
 CYM1471
CYM1481

Switching Waveforms (continued)

Write Cycle No. 2 [5, 10, 11]

tWC

ADDRESS

tSA tSMS

MS

tAW tHA
tPWE
WE

tSD tHD

DATA IN DATA VALID

tHZWE
HIGH IMPEDANCE
DATA I/O DATA UNDEFINED

1471-10

Note:
11. If MS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

6
 CYM1471
CYM1481

Truth Table
MS WE OE Input/Outputs Mode
H X X High Z Deselect/Power-Down
L H L Data Out Read
L L X Data In Write
L H H High Z Deselect

Ordering Information
Speed Package Package Operating
(ns) Ordering Code Type Type Range
70 CYM1471PS-70C PS08 36-Pin SIP Module Commercial
CYM1471LPS-70C
85 CYM1471PS–85C PS08 36-Pin SIP Module Commercial
CYM1471LPS–85C
100 CYM1471PS–100C PS08 36-Pin SIP Module Commercial
CYM1471LPS–100C
120 CYM1471PS–120C PS08 36-Pin SIP Module Commercial
CYM1471LPS–120C

Speed Package Package Operating

(ns) Ordering Code Type Type Range
70 CYM1481PS-70C PS08 36-Pin SIP Module Commercial
CYM1481LPS-70C
85 CYM1481PS–85C PS06 36-Pin SIP Module Commercial
CYM1481LPS–85C
100 CYM1481PS–100C PS06 36-Pin SIP Module Commercial
CYM1481LPS–100C
120 CYM1481PS–120C PS06 36-Pin SIP Module Commercial
CYM1481LPS–120C

Document #: 38–M–00041–C

7
 CYM1471
CYM1481

Package Diagrams

36-Pin SIP Module PS06

3.755 .190 MAX.

3.765

.745
.835
.755 .040 TYP.
.855

.125–.175
PIN 1
.100 TYP .050 TYP. .020 TYP.

3.500(36PINS)

36-Pin SIP Module PS08

3.755 .120 MAX.

3.765

.835 .745
.755 .040 TYP.
.855

.125–.175
PIN 1 .050 TYP. .020 TYP.
.100 TYP

3.500(36PINS)

© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.