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Cy7c164 Cy7c166 Datasheet Cypress Semiconductor

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CY7C164
CY7C166

16K x 4 Static RAM


Features three-state drivers. The CY7C166 has an active LOW Output
Enable (OE) feature. Both devices have an automatic power-
• High speed down feature, reducing the power consumption by 65% when
— 15 ns deselected.
• Output enable (OE) feature (CY7C166) Writing to the device is accomplished when the Chip Enable
• CMOS for optimum speed/power (CE) and Write Enable (WE) inputs are both LOW (and the
Output Enable (OE) is LOW for the CY7C166). Data on the
• Low active power four input/output pins (I/O0 through I/O3) is written into the
— 633 mW memory location specified on the address pins (A0 through
• Low standby power A13).
— 110 mW Reading the device is accomplished by taking Chip Enable
• TTL-compatible inputs and outputs (CE) LOW (and OE LOW for CY7C166), while Write Enable
(WE) remains HIGH. Under these conditions the contents of
• Automatic power-down when deselected the memory location specified on the address pins will appear
Functional Description on the four data I/O pins.
The CY7C164 and CY7C166 are high-performance CMOS The I/O pins stay in a high-impedance state when Chip Enable
static RAMs organized as 16,384 by 4 bits. Easy memory ex- (CE) is HIGH (or Output Enable (OE) is HIGH for CY7C166).
pansion is provided by an active LOW Chip Enable (CE) and A die coat is used to insure alpha immunity.

Logic Block Diagram Pin Configurations


DIP SOJ
Top View Top View
A5 1 22 VCC A5 1 24 VCC
A6 2 21 A4 A6 2 23 A4
A7 3 20 A3 A7 3 22 A3
A8 4 19 A2 A8 4 21 A2
A9 5 18 A1 A9 5 20 A1
A10 6 7C164 17 A0 A10 6 7C164 19 A0
A11 7 16 I/O3 A11 7 18 NC
A12 8 15 I/O2 A12 8 17 I/O3
A13 9 14 I/O1 A13 9 16 I/O2
CE 10 13 I/O0 CE 10 15 I/O1
GND 11 12 WE NC 11 14 I/O0
INPUT BUFFER GND 12 13 WE
C164–3
C164–2
ROW DECODER

A1 I/O3
SENSE AMPS

A2 DIP/SOJ
A3 I/O2 Top View
A4 256 x 64 x 4
A5 ARRAY A5 1 24 VCC
A6 I/O1
A6 2 23 A4
A7
A7 3 22 A3
A8 I/O0
A8 4 21 A2
A9 5 20 A1
POWER A10 6 7C166 19 A0
COLUMN DOWN A11
CE 7 18 NC
DECODER A12 8 17 I/O3
A13 9 16 I/O2
WE
A10
A11
A12
A13

I/O1
A0
A9

CE 10 15
(OE) 11 14 I/O0
OE
(7C166 ONLY) GND 12 13 WE

C164–4 C166–1
]

Selection Guide
7C164-15 7C164-20 7C164-25 7C164-35
7C166-15 7C166-20 7C166-25 7C166-35
Maximum Access Time (ns) 15 20 25 35
Maximum Operating Current (mA) 115 115 105 105
Maximum Standby Current (mA) 20 20 20 20

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05025 Rev. ** Revised August 24, 2001
CY7C164
CY7C166

Maximum Ratings
(Above which the useful life may be impaired. For user guide- Output Current into Outputs (LOW)............................. 20 mA
lines, not tested.) Static Discharge Voltage .......................................... >2001V
Storage Temperature ................................. –65°C to +150°C (per MIL-STD-883, Method 3015)
Ambient Temperature with Latch-Up Current.................................................... >200 mA
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V Operating Range
DC Voltage Applied to Outputs Ambient
in High Z State[1] ............................................ –0.5V to +7.0V Range Temperature VCC
DC Input Voltage [1]
........................................ –0.5V to +7.0V Commercial 0°C to +70°C 5V ± 10%

Electrical Characteristics Over the Operating Range


7C164-15 7C164-20 7C164-25, 35
7C166-15 7C166-20 7C166-25, 35
Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Unit
VOH Output HIGH VCC = Min., 2.4 2.4 2.4 V
Voltage IOH = –4.0 mA
VOL Output LOW VCC = Min., 0.4 0.4 0.4 V
Voltage IOL = 8.0 mA
VIH Input HIGH Voltage 2.2 VCC 2.2 VCC 2.2 VCC V
VIL Input LOW –0.5 0.8 –0.5 0.8 –0.5 0.8 V
Voltage[1]
IIX Input Load Current GND < VI < VCC –5 +5 –5 +5 –5 +5 µA
IOZ Output Leakage GND < VO < VCC, –5 +5 –5 +5 –5 +5 µA
Current Output Disabled
IOS Output Short VCC = Max., –350 –350 –350 mA
Circuit Current[2] VOUT = GND
ICC VCC Operating VCC = Max., 115 115 105 mA
Supply Current IOUT = 0 mA
ISB1 Automatic CE Max. VCC, CE > VIH, 40 40 20 mA
Power-Down Current[3] Min. Duty Cycle = 100%
ISB2 Automatic CE Max. VCC, 20 20 20 mA
Power-Down Current[3] CE > VCC – 0.3V,
VIN > VCC – 0.3V
or VIN < 0.3V

Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz, 10 pF
VCC = 5.0V
COUT Output Capacitance 10 pF
Notes:
1. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns.
2. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.
4. Tested initially and after any design or process changes that may affect these parameters.

Document #: 38-05025 Rev. ** Page 2 of 9


CY7C164
CY7C166

AC Test Loads and Waveforms

R1 481Ω R1 481Ω
5V 5V
ALL INPUT PULSES
OUTPUT OUTPUT 3.0V
90% 90%
R2 R2 10% 10%
30 pF 5 pF GND
255Ω 255 Ω
< 5 ns < 5 ns
INCLUDING INCLUDING
JIG AND JIG AND C164–5 C164–6
SCOPE (a) SCOPE (b)

Equivalent to: THÉVENIN EQUIVALENT


167Ω
OUTPUT 1.73V

Switching Characteristics Over the Operating Range[5]


7C164-15 7C164-20 7C164-25 7C164-35
7C166-15 7C166-20 7C166-25 7C166-35
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 15 20 25 35 ns
tAA Address to Data Valid 15 20 25 35 ns
tOHA Output Hold from Address Change 3 5 5 5 ns
tACE CE LOW to Data Valid 15 20 25 35 ns
tDOE OE LOW to Data Valid 7C166 10 10 12 15 ns
tLZOE OE LOW to Low Z 7C166 3 3 3 3 ns
tHZOE OE HIGH to High Z 7C166 8 8 10 12 ns
[6]
tLZCE CE LOW to Low Z 3 5 5 5 ns
tHZCE CE HIGH to High Z[6, 7] 8 8 10 15 ns
tPU CE LOW to Power-Up 0 0 0 0 ns
tPD CE HIGH to Power-Down 15 20 20 20 ns
[8]
WRITE CYCLE
tWC Write Cycle Time 15 20 20 25 ns
tSCE CE LOW to Write End 12 15 20 25 ns
tAW Address Set-Up to Write End 12 15 20 25 ns
tHA Address Hold from Write End 0 0 0 0 ns
tSA Address Set-Up to Write Start 0 0 0 0 ns
tPWE WE Pulse Width 12 15 15 20 ns
tSD Data Set-Up to Write End 10 10 10 15 ns
tHD Data Hold from Write End 0 0 0 0 ns
[6]
tLZWE WE HIGH to Low Z 5 5 5 5 ns
tHZWE WE LOW to High Z[6, 7] 7 7 7 10 ns
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. These parameters are guaranteed by design and not 100% tested.
7. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

Document #: 38-05025 Rev. ** Page 3 of 9


CY7C164
CY7C166

Switching Waveforms

Read Cycle No.1 [9, 10]

tRC

ADDRESS
tAA
tOHA
DATA OUT PREVIOUS DATA VALID DATA VALID

C164–7

Read Cycle No. 2 [9, 11]

tRC
CE

tACE
OE
7C166
tDOE tHZOE
tHZCE
tLZOE HIGH
HIGH IMPEDANCE IMPEDANCE
DATA OUT DATA VALID
tLZCE
tPD
tPU
V CC ICC
SUPPLY 50% 50%
CURRENT ISB

C164–8

Write Cycle No. 1 (WE Controlled) [8, 12]


tWC

ADDRESS

tSCE

CE

tAW tHA
tSA tPWE

WE
tSD tHD

DATA IN DATAINVALID

tHZWE tLZWE
HIGH IMPEDANCE
DATA I/O DATA UNDEFINED

C164–9

Notes:
9. WE is HIGH for read cycle.
10. Device is continuously selected, CE = VIL. (CY7C166: OE = VIL also).
11. Address valid prior to or coincident with CE transition LOW.
12. CY7C166 only: Data I/O will be high-impedance if OE = VIH.

Document #: 38-05025 Rev. ** Page 4 of 9


CY7C164
CY7C166

Switching Waveforms (continued)

Write Cycle No. 2 (CE Controlled) [8, 12, 13]


tWC

ADDRESS

tSA tSCE
CE

tAW tHA
tPWE

WE

tSD tHD

DATA IN DATAIN VALID

HIGH IMPEDANCE
DATA I/O
C164–10

Note:
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

Document #: 38-05025 Rev. ** Page 5 of 9


CY7C164
CY7C166

Typical DC and AC Characteristics

NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENT


vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vs. OUTPUT VOLTAGE

OUTPUT SOURCE CURRENT (mA)


1.4 1.2 120
SB

SB
1.2 1.0 100
I CC I CC
NORMALIZED I,CC

NORMALIZED I,CC
I

I
1.0
0.8 80
0.8
V CC = 5.0V
0.6 60 TA = 25°C
0.6
0.4 V CC = 5.0V 40
0.4
V IN = 5.0V
0.2 I SB 0.2 I SB 20

0.0 0.0 0
4.0 4.5 5.0 5.5 6.0 –55 25 125 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V)

NORMALIZED ACCESS TIME NORMALIZED ACCESS TIME OUTPUT SINK CURRENT


vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vs. OUTPUT VOLTAGE

OUTPUT SINK CURRENT (mA)


1.4 1.6 140
120
1.3
NORMALIZED tAA

1.4
NORMALIZED t AA

100
1.2 VCC = 5.0V
1.2 80 TA =25°C
1.1
TA = 25°C 60
1.0
1.0 VCC =5.0V
40
0.8
0.9 20

0.8 0.6 0
4.0 4.5 5.0 5.5 6.0 –55 25 125 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V)

TYPICAL POWER-ON CURRENT TYPICAL ACCESS TIME CHANGE


vs. SUPPLY VOLTAGE vs. OUTPUT LOADING NORMALIZED I CC vs. CYCLE TIME
3.0 30.0 1.25
VCC = 5.0V
2.5 25.0 TA = 25°C
NORMALIZED I CC
NORMALIZED I PO

VIN = 0.5V
DELTA tAA (ns)

2.0 20.0 1.00

1.5 15.0

1.0 10.0 0.75


VCC = 4.5V
TA = 25°C
0.5 5.0

0.0 0.0 0.50


0.0 1.0 2.0 3.0 4.0 5.0 0 200 400 600 800 1000 10 20 30 40
SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz)

Document #: 38-05025 Rev. ** Page 6 of 9


CY7C164
CY7C166

CY7C164 Truth Table Address Designators


CE WE Input/Output Mode Address Address CY 7C164 Pin CY7C166 Pin
Name Function Number Number
H X High Z Deselect/Power-Down
A5 X3 1 1
L H Data Out Read
A6 X4 2 2
L L Data In Write
A7 X5 3 3
A8 X6 4 4
CY7C166 Truth Table
A9 X7 5 5
CE WE OE Input/Output Mode
A10 Y5 6 6
H X X High Z Deselect/Power-Down
A11 Y4 7 7
L H L Data Out Read
A12 Y0 8 8
L L H Data In Write
A13 Y1 9 9
L H H High Z Write
A0 Y2 17 19
A1 Y3 18 20
A2 X0 19 21
A3 X1 20 22
A4 X2 21 23

Ordering Information
Speed Package Operating
(ns) Ordering Code Name Package Type Range
15 CY7C164-15PC P9 22-Lead (300-Mil) Molded DIP Commercial
CY7C164-15VC V13 24-Lead Molded SOJ
20 CY7C164-20PC P9 22-Lead (300-Mil) Molded DIP Commercial
CY7C164-20VC V13 24-Lead Molded SOJ
25 CY7C164-25PC P9 22-Lead (300-Mil) Molded DIP Commercial
CY7C164-25VC V13 24-Lead Molded SOJ
35 CY7C164-35PC P9 22-Lead (300-Mil) Molded DIP Commercial
CY7C164-35VC V13 24-Lead Molded SOJ

Speed Package Operating


(ns) Ordering Code Name Package Type Range
15 CY7C166-15PC P13 24-Lead (300-Mil) Molded DIP Commercial
CY7C166-15VC V13 24-Lead Molded SOJ
20 CY7C166-20PC P13 24-Lead (300-Mil) Molded DIP Commercial
CY7C166-20VC V13 24-Lead Molded SOJ
25 CY7C166-25PC P13 24-Lead (300-Mil) Molded DIP Commercial
CY7C166-25VC V13 24-Lead Molded SOJ
35 CY7C166-35PC P13 24-Lead (300-Mil) Molded DIP Commercial
CY7C166-35VC V13 24-Lead Molded SOJ

Document #: 38-05025 Rev. ** Page 7 of 9


CY7C164
CY7C166

Package Diagrams
22-Lead (300-Mil) Molded DIP P9

51-85012-A

24-Lead (300-Mil) Molded DIP P13/P13A

51-85013-A

24-Lead (300-Mil) Molded SOJ V13

51-85030-A

Document #: 38-05025 Rev. ** Page 8 of 9


© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C164
CY7C166

Document Title: CY7C164, CY7C166 16K x 4 Static RAM


Document Number: 38-05025
Issue Orig. of
REV. ECN NO. Date Change Description of Change
** 106811 09/10/01 SZV Change from Spec number: 38-00032 to 38-05025

Document #: 38-05025 Rev. ** Page 9 of 9

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