CY62256

256K (32K x 8) Static RAM

Features Functional Description[1]

• Temperature Ranges The CY62256 is a high-performance CMOS static RAM
— Commercial: 0°C to 70°C organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
— Industrial: –40°C to 85°C output enable (OE) and three-state drivers. This device has an
— Automotive: –40°C to 125°C automatic power-down feature, reducing the power
• High speed: 55 ns and 70 ns consumption by 99.9% when deselected.
• Voltage range: 4.5V–5.5V operation An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
• Low active power (70 ns, LL version, Com’l and Ind’l)
inputs are both LOW, data on the eight data input/output pins
— 275 mW (max.) (I/O0 through I/O7) is written into the memory location
• Low standby power (70 ns, LL version, Com’l and Ind’l) addressed by the address present on the address pins (A0
— 28 µW (max.) through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
• Easy memory expansion with CE and OE features while WE remains inactive or HIGH. Under these conditions,
• TTL-compatible inputs and outputs the contents of the location addressed by the information on
• Automatic power-down when deselected address pins are present on the eight data input/output pins.
• CMOS for optimum speed/power The input/output pins remain in a high-impedance state unless
• Package available in a standard 450-mil-wide (300-mil the chip is selected, outputs are enabled, and write enable
body width) 28-lead narrow SOIC, 28-lead TSOP-1, (WE) is HIGH.
28-lead reverse TSOP-1, and 600-mil 28-lead PDIP
packages
Logic Block Diagram

I/O0
INPUTBUFFER
I/O1
A10
ROW DECODER

A9
A8 I/O2
SENSE AMPS

A7
A6 512 x 512 I/O3
A5
ARRAY
A4 I/O4
A3
A2 I/O5

CE I/O6
POWER
WE COLUMN DOWN
DECODER
I/O7
OE
A14
A13
A12
A11

A0
A1

Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05248 Rev. *C Revised June 25, 2004
 CY62256
Product Portfolio
Power Dissipation
Operating, ICC Standby, ISB2
VCC Range (V) (mA) (µA)
Speed
Product Min. Typ.[2] Max. (ns) Typ.[2] Max. Typ.[2] Max.
CY62256 Commercial 4.5 5.0 5.5 70 28 55 1 5
CY62256L Com’l / Ind’l 55/70 25 50 2 50
CY62256LL Commercial 70 25 50 0.1 5
CY62256LL Industrial 55/70 25 50 0.1 10
CY62256LL Automotive 55 25 50 0.1 15

Pin Configurations

OE 22 21 A0
A1 23 20 CE
Narrow SOIC DIP A2 24 19 I/O7
A3 25 18 I/O6
Top View Top View A4 26 17 I/O5
WE 27 16 I/O4
A5 1 28 VCC A5 1 28 VCC VCC 28 TSOP I 15 I/O3
A5 1 Top View 14 GND
A6 2 27 WE A6 2 27 WE A6 13 I/O2
A7 3 26 A7 26 A7
2
(not to scale) I/O1
A4 3 A4 3 12
A8 4 11 I/O0
A8 4 25 A3 A8 4 25 A3 10 A14
A9 5
A9 5 24 A2 A9 5 24 A2 A10 6 9 A13
A10 23 A1 A10 23 A11 7 8 A12
6 6 A1
A11 7 22 OE A11 7 22 OE A11 7 8 A12
A12 8 21 A0 A12 8 21 A0 A10 6 9 A13
20 A9 10 A14
A13 9 CE A13 9 20 CE 5
A8 4 11 I/O0
A14 10 19 I/O7 A14 10 19 I/O7 A7 3 TSOP I 12 I/O1
I/O0 11 18 I/O6 I/O0 11 18 I/O6 A6 2 Reverse Pinout 13 I/O2
I/O1 12 17 I/O5 I/O1 12 17 I/O5 A5 1 Top View 14 GND
VCC 28 15 I/O3
I/O2 13 16 I/O4 I/O2 13 16 I/O4 27
(not to scale) 16 I/O4
WE
GND 14 15 I/O3 GND 15 I/O3 A4 26 17 I/O5
14 A3 18
25 I/O6
A2 24 19 I/O7
A1 23 20 CE
OE 22 21 A0

Pin Definitions

Pin Number Type Description

1-10, 21, 23-26 Input A0-A14. Address Inputs
11-13, 15-19, Input/Output I/O0-I/O7. Data lines. Used as input or output lines depending on operation
27 Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted
20 Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip
22 Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as
input data pins
14 Ground GND. Ground for the device
28 Power Supply Vcc. Power supply for the device
Notes:
2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(TA = 25°C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.

Document #: 38-05248 Rev. *C Page 2 of 12

 CY62256
Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Operating Range
Power Applied..............................................-55°C to +125°C
Range Ambient Temperature (TA)[4] VCC
Supply Voltage to Ground Potential
Commercial 0°C to +70°C 5V ± 10%
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V
Industrial –40°C to +85°C 5V ± 10%
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.5V Automotive –40°C to +125°C 5V ± 10%
[3]
DC Input Voltage .................................–0.5V to VCC + 0.5V

Electrical Characteristics Over the Operating Range

CY62256−55 CY62256−70
Parameter Description Test Conditions Min. Typ.[2] Max. Min. Typ.[2] Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = −1.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC 2.2 VCC V
+0.5V +0.5V
VIL Input LOW Voltage –0.5 0.8 –0.5 0.8 V
IIX Input Leakage Current GND < VI < VCC –0.5 +0.5 –0.5 +0.5 µA
IOZ Output Leakage Current GND < VO < VCC, Output Disabled –0.5 +0.5 –0.5 +0.5 µA
ICC VCC Operating Supply VCC = Max., IOUT = 0 mA, 28 55 28 55 mA
Current f = fMAX = 1/tRC
L 25 50 25 50 mA
LL 25 50 25 50 mA
ISB1 Automatic CE Max. VCC, CE > VIH, 0.5 2 0.5 2 mA
Power-down Current— VIN > VIH or VIN < VIL, f = L 0.4 0.6 0.4 0.6 mA
TTL Inputs fMAX
LL 0.3 0.5 0.3 0.5 mA
ISB2 Automatic CE Max. VCC, CE > VCC − 0.3V 1 5 1 5 mA
Power-down Current— VIN > VCC − 0.3V, or VIN < L 2 50 2 50 µA
CMOS Inputs 0.3V, f = 0
LL 0.1 5 0.1 5 µA
LL - Ind’l 0.1 10 0.1 10 µA
LL - 0.1 15 µA
Auto

Capacitance[5]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz, 6 pF
COUT Output Capacitance VCC = 5.0V 8 pF
Notes:
3. VIL (min.) = −2.0V for pulse durations of less than 20 ns.
4. TA is the “Instant-On” case temperature.
5. Tested initially and after any design or process changes that may affect these parameters.

Document #: 38-05248 Rev. *C Page 3 of 12

 CY62256

Thermal Resistance
Description Test Conditions Symbol DIP SOIC TSOP RTSOP Unit
Thermal Resistance Still Air, soldered on a 4.25 x 1.125 ΘJA 75.61 76.56 93.89 93.89 °C/W
(Junction to Ambient)[5] inch, 4-layer printed circuit board
Thermal Resistance ΘJC 43.12 36.07 24.64 24.64 °C/W
(Junction to Case)[5]

AC Test Loads and Waveforms

R1 1800 Ω R1 1800 Ω
5V 5V
ALL INPUT PULSES
OUTPUT OUTPUT 3.0V 90%
90%
10% 10%
100 pF R2 5 pF R2 GND
990Ω 990Ω
< 5 ns < 5 ns
INCLUDING INCLUDING
JIG AND JIG AND
SCOPE (a) SCOPE (b)
Equivalent to: THÉVENIN EQUIVALENT
639Ω
OUTPUT 1.77V
Data Retention Characteristics
Parameter Description Conditions[6] Min. Typ.[2] Max. Unit
VDR VCC for Data Retention 2.0 V
ICCDR Data Retention Current L VCC = 3.0V, CE > VCC − 0.3V, 2 50 µA
LL VIN > VCC − 0.3V, or VIN < 0.3V 0.1 5 µA
LL - Ind’l 0.1 10 µA
LL - Auto 0.1 10 µA
tCDR[5] Chip Deselect to Data Retention Time 0 ns
tR[5] Operation Recovery Time tRC ns

Data Retention Waveform

DATA RETENTION MODE
VCC 3.0V VDR > 2V 3.0V
tCDR tR

CE

Notes:
6. No input may exceed VCC + 0.5V.

Document #: 38-05248 Rev. *C Page 4 of 12

 CY62256
Switching Characteristics Over the Operating Range[7]
CY62256−55 CY62256−70
Parameter Description Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time 55 70 ns
tAA Address to Data Valid 55 70 ns
tOHA Data Hold from Address Change 5 5 ns
tACE CE LOW to Data Valid 55 70 ns
tDOE OE LOW to Data Valid 25 35 ns
tLZOE OE LOW to Low-Z[8] 5 5 ns
tHZOE OE HIGH to High-Z[8, 9] 20 25 ns
tLZCE CE LOW to Low-Z[8] 5 5 ns
tHZCE CE HIGH to High-Z[8, 9] 20 25 ns
tPU CE LOW to Power-up 0 0 ns
tPD CE HIGH to Power-down 55 70 ns
Write Cycle[10, 11]
tWC Write Cycle Time 55 70 ns
tSCE CE LOW to Write End 45 60 ns
tAW Address Set-up to Write End 45 60 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-up to Write Start 0 0 ns
tPWE WE Pulse Width 40 50 ns
tSD Data Set-up to Write End 25 30 ns
tHD Data Hold from Write End 0 0 ns
tHZWE WE LOW to High-Z[8, 9] 20 25 ns
tLZWE WE HIGH to Low-Z[8] 5 5 ns

Switching Waveforms
Read Cycle No. 1 [12, 13]
tRC

ADDRESS

tAA
tOHA

DATA OUT PREVIOUS DATA VALID DATA VALID

Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate
a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for Read cycle.

Document #: 38-05248 Rev. *C Page 5 of 12

 CY62256
Switching Waveforms (continued)
Read Cycle No. 2 [13, 14]
tRC
CE

tACE
OE

tDOE tHZOE
tHZCE
tLZOE HIGH
HIGH IMPEDANCE IMPEDANCE
DATA OUT DATA VALID
tLZCE
tPD
tPU
VCC ICC
SUPPLY 50% 50%
CURRENT ISB

[10, 15, 16]

Write Cycle No. 1 (WE Controlled)
tWC

ADDRESS

CE

tAW tHA
tSA tPWE
WE

OE
tSD tHD

DATA I/O NOTE 17 DATAIN VALID

tHZOE

[10, 15, 16]

Write Cycle No. 2 (CE Controlled)
tWC

ADDRESS

CE tSCE
tSA
tAW tHA

WE
tSD tHD

DATA I/O DATAIN VALID

Notes:
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.

Document #: 38-05248 Rev. *C Page 6 of 12

 CY62256
Switching Waveforms (continued)
[11, 16]
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC

ADDRESS

CE

tAW tHA
tSA
WE

tSD tHD

DATA I/O NOTE 17 DATAIN VALID

tHZWE tLZWE

Document #: 38-05248 Rev. *C Page 7 of 12

 CY62256
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT STANDBY CURRENT
vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vs. AMBIENT TEMPERATURE
1.4 1.4 3.0
ICC
SB

1.2 1.2 2.5

ICC
NORMALIZED I,CC

1.0 2.0

NORMALIZED I CC
1.0
I

ISB

ISB2 µA
0.8 0.8 1.5

0.6 VIN =5.0V 0.6 1.0

TA =25°C
0.4 0.4 VCC =5.0V 0.5
VIN =5.0V
VCC =5.0V
0.2 0.2 0.0 VIN =5.0V
ISB
0.0 0.0 -0.5
4.0 4.5 5.0 5.5 6.0 −55 25 125 −55 25 105
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)

NORMALIZED ACCESS TIME NORMALIZED ACCESS TIME OUTPUT SINK CURRENT

vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE vs. OUTPUT VOLTAGE

OUTPUT SINK CURRENT (mA)

1.4 1.6 140
120
1.3 1.4
AA
NORMALIZED t AA

100
NORMALIZED t

1.2
1.2 80
1.1
TA =25°C 60 VCC =5.0V
1.0
1.0 VCC =5.0V TA =25°C
40
0.8
0.9 20

0.8 0.6 0
4.0 4.5 5.0 5.5 6.0 −55 25 125 0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
OUTPUT SOURCE CURRENT (mA)

120

100

80
VCC =5.0V
60 TA =25°C

40

20
0
0.0 1.0 2.0 3.0 4.0
OUTPUT VOLTAGE (V)

Document #: 38-05248 Rev. *C Page 8 of 12

 CY62256
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT TYPICAL ACCESS TIME CHANGE
vs. SUPPLY VOLTAGE vs. OUTPUT LOADING NORMALIZED I CC vs.CYCLE TIME
3.0 30.0 1.25

2.5 25.0 VCC =5.0V

DELTA tAA (ns)

NORMALIZED ICC
PO

TA =25°C
NORMALIZED I

2.0 20.0 1.00 VIN =0.5V

1.5 15.0

1.0 10.0 VCC =4.5V 0.75

TA =25°C
0.5 5.0

0.0 0.0 0.50

0.0 1.0 2.0 3.0 4.0 5.0 0 200 400 600 800 1000 10 20 30 40
SUPPLY VOLTAGE (V) CAPACITANCE (pF) CYCLE FREQUENCY (MHz)

Truth Table
CE WE OE Inputs/Outputs Mode Power
H X X High-Z Deselect/Power-down Standby (ISB)
L H L Data Out Read Active (ICC)
L L X Data In Write Active (ICC)
L H H High-Z Output Disabled Active (ICC)

Ordering Information
Speed Package Operating
(ns) Ordering Code Name Package Type Range
55 CY62256LL−55SNI SN28 28-lead (300-Mil Narrow Body) Narrow SOIC Industrial
CY62256LL−55ZI Z28 28-lead Thin Small Outline Package
CY62256LL−55SNE SN28 28-lead (300-Mil Narrow Body) Narrow SOIC Automotive
CY62256LL−55ZE Z28 28-lead Thin Small Outline Package
CY62256LL−55ZRE ZR28 28-lead Reverse Thin Small Outline Package
70 CY62256−70SNC SN28 28-lead (300-Mil Narrow Body) Narrow SOIC Commercial
CY62256L−70SNC
CY62256LL−70SNC
CY62256L–70SNI Industrial
CY62256LL−70SNI
CY62256LL−70ZC Z28 28-lead Thin Small Outline Package Commercial
CY62256LL−70ZI Z28 Industrial
CY62256−70PC P15 28-lead (600-Mil) Molded DIP Commercial
CY62256L−70PC P15
CY62256LL−70PC P15
CY62256LL−70ZRI ZR28 28-lead Reverse Thin Small Outline Package Industrial

Document #: 38-05248 Rev. *C Page 9 of 12

 CY62256
Package Diagrams
28-lead (600-mil) Molded DIP P15

51-85017-A

28-lead (300-mil) SNC (Narrow Body) SN28

51-85092-*B

Document #: 38-05248 Rev. *C Page 10 of 12

 CY62256

Package Diagrams (continued)

28-lead Thin Small Outline Package Type 1 (8 x 13.4 mm) Z28

51-85071-*G

28-lead Reverse Type 1 Thin Small Outline Package (8 x 13.4 mm) ZR28

51-85074-*F

All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05248 Rev. *C Page 11 of 12

© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
 CY62256

Document Title: CY62256 256K (32K x 8) Static RAM

Document Number: 38-05248
Issue Orig. of
REV. ECN NO. Date Change Description of Change
** 113454 03/06/02 MGN Change from Spec number: 38-00455 to 38-05248
Remove obsolete parts from ordering info, standardize format
*A 115227 05/23/02 GBI Changed SN Package Diagram
*B 116506 09/04/02 GBI Added footnote 1.
Corrected package description in Ordering Information table
*C 238448 See ECN AJU Added Automotive product information

Document #: 38-05248 Rev. *C Page 12 of 12

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