Features

• Fast Read Access Time – 70 ns

• 5-volt Only Reprogramming
• Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– Internal Address and Data Latches for 64 Bytes
• Internal Program Control and Timer
• Hardware and Software Data Protection
• Fast Program Cycle Times
– Page (64 Byte) Program Time – 10 ms

•
– Chip Erase Time – 10 ms
DATA Polling for End of Program Detection
256K (32K x 8)
• Low-power Dissipation
– 50 mA Active Current
5-volt Only
– 300 µA CMOS Standby Current
• Typical Endurance > 10,000 Cycles Flash Memory
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges
AT29C256
Description
The AT29C256 is a five-volt-only in-system Flash programmable and erasable read
only memory (PEROM). Its 256K of memory is organized as 32,768 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 70 ns with power dissipation of just 275 mW. When the device is
deselected, the CMOS standby current is less than 300 µA. The device endurance is
such that any sector can typically be written to in excess of 10,000 times.

Pin Configurations TSOP Top View

Type 1
Pin Name Function
A0 - A14 Addresses
OE 22 21 A10
CE Chip Enable A11 23 20 CE
A9 24 19 I/O7
A8 25 18 I/O6
OE Output Enable A13 26 17 I/O5
A14 27 16 I/O4
WE Write Enable VCC 28 15 I/O3
WE 1 14 GND
I/O0 - I/O7 Data Inputs/Outputs A12 2 13 I/O2
A7 3 12 I/O1
NC No Connect A6 4 11 I/O0
A5 5 10 A0
DC Don’t Connect A4 6 9 A1
A3 7 8 A2

PLCC and LCC Top View

VCC
A12

A14
A13
WE
DC
A7
4
3
2
1
32
31
30

A6 5 29 A8
A5 6 28 A9
A4 7 27 A11
A3 8 26 NC
A2 9 25 OE
A1 10 24 A10
A0 11 23 CE
NC 12 22 I/O7
I/O0 13 21 I/O6
14
15
16
17
18
19
20
I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5

Note: PLCC package pins 1 and 17 are Rev. 0046P–FLASH–10/04

DON’T CONNECT.

1
 To allow for simple in-system reprogrammability, the AT29C256 does not require high
input voltages for programming. Five-volt-only commands determine the operation of
the device. Reading data out of the device is similar to reading from a static RAM.
Reprogramming the AT29C256 is performed on a page basis; 64 bytes of data are
loaded into the device and then simultaneously programmed. The contents of the entire
device may be erased by using a six-byte software code (although erasure before pro-
gramming is not needed).
During a reprogram cycle, the address locations and 64 bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation of
a program cycle, the device will automatically erase the page and then program the
latched data using an internal control timer. The end of a program cycle can be detected
by DATA polling of I/O7. Once the end of a program cycle has been detected a new
access for a read, program or chip erase can begin.

Block Diagram

Device Operation READ: The AT29C256 is accessed like a static RAM. When CE and OE are low and
WE is high, the data stored at the memory location determined by the address pins
is asserted on the outputs. The outputs are put in the high impedance state whenever
CE or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.
BYTE LOAD: A byte load is performed by applying a low pulse on the WE or CE input
with CE or WE low (respectively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of
CE or WE. Byte loads are used to enter the 64 bytes of a page to be programmed or the
software codes for data protection and chip erasure.

2 AT29C256
0046P–FLASH–10/04
 AT29C256

PROGRAM: The device is reprogrammed on a page basis. If a byte of data within a

page is to be changed, data for the entire page must be loaded into the device. Any byte
that is not loaded during the programming of its page will be indeterminate. Once the
bytes of a page are loaded into the device, they are simultaneously programmed during
the internal programming period. After the first data byte has been loaded into the
device, successive bytes are entered in the same manner. Each new byte to be pro-
grammed must have its high-to-low transition on WE (or CE) within 150 µs of the low-to-
high transition of WE (or CE) of the preceding byte. If a high-to-low transition is not
detected within 150 µs of the last low-to-high transition, the load period will end and the
internal programming period will start. A6 to A14 specify the page address. The page
address must be valid during each high-to-low transition of WE (or CE). A0 to A5 specify
the byte address within the page. The bytes may be loaded in any order; sequential
loading is not required. Once a programming operation has been initiated, and for the
duration of tWC, a read operation will effectively be a polling operation.
SOFTWARE DATA PROTECTION: A software controlled data protection feature is
available on the AT29C256. Once the software protection is enabled a software algo-
rithm must be issued to the device before a program may be performed. The software
protection feature may be enabled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable the software data protection,
a series of three program commands to specific addresses with specific data must be
performed. After the software data protection is enabled the same three program com-
mands must begin each program cycle in order for the programs to occur. All software
program commands must obey the page program timing specifications. Once set, the
software data protection feature remains active unless its disable command is issued.
Power transitions will not reset the software data protection feature, however the soft-
ware feature will guard against inadvertent program cycles during power transitions.
Once set, software data protection will remain active unless the disable command
sequence is issued.
After setting SDP, any attempt to write to the device without the three-byte command
sequence will start the internal write timers. No data will be written to the device; how-
ever, for the duration of tWC, a read operation will effectively be a polling operation.
After the software data protection’s three-byte command code is given, a byte load is
performed by applying a low pulse on the WE or CE input with CE or WE low (respec-
tively) and OE high. The address is latched on the falling edge of CE or WE, whichever
occurs last. The data is latched by the first rising edge of CE or WE. The 64 bytes of
data must be loaded into each sector by the same procedure as outlined in the program
section under device operation.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent
programs to the AT29C256 in the following ways: (a) VCC sense – if VCC is below 3.8V
(typical), the program function is inhibited; (b) V CC power on delay – once V CC has
reached the VCC sense level, the device will automatically time out 5 ms (typical) before
programming; (c) Program inhibit – holding any one of OE low, CE high or WE high
inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a program cycle.

3
0046P–FLASH–10/04
 PRODUCT IDENTIFICATION: The product identification mode identifies the device
and manufacturer and may be accessed by a hardware operation. For details, see
Operating Modes or Product Identification.
DATA POLLING: The AT29C256 features DATA polling to indicate the end of a pro-
gram cycle. During a program cycle an attempted read of the last byte loaded will result
in the complement of the loaded data on I/O7. Once the program cycle has been com-
pleted, true data is valid on all outputs and the next cycle may begin. DATA polling may
begin at any time during the program cycle.
TOGGLE BIT: In addition to DATA polling the AT29C256 provides another method for
determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid
data will be read. Examining the toggle bit may begin at any time during a program
cycle.
OPTIONAL CHIP ERASE MODE: The entire device can be erased by using a six-byte
software code. Please see Software Chip Erase application note for details.

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
All Input Voltages (including NC Pins) other conditions beyond those indicated in the
with Respect to Ground ...................................-0.6V to +6.25V operational sections of this specification is not
implied. Exposure to absolute maximum rating
All Output Voltages conditions for extended periods may affect
with Respect to Ground .............................-0.6V to VCC + 0.6V device reliability.

Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V

4 AT29C256
0046P–FLASH–10/04
 AT29C256

DC and AC Operating Range

AT29C256-70 AT29C256-90 AT29C256-12 AT29C256-15

Operating Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C
Temperature (Case) Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C -40°C - 85°C
VCC Power Supply 5V ± 5% 5V± 10% 5V± 10% 5V± 10%

Note: Not recommended for New Designs.

Operating Modes
Mode CE OE WE Ai I/O
Read VIL VIL VIH Ai DOUT
(2)
Program VIL VIH VIL Ai DIN
5V Chip Erase VIL VIH VIL Ai
(1)
Standby/Write Inhibit VIH X X X High Z
Write Inhibit X X VIH
Write Inhibit X VIL X
Output Disable X VIH X High Z
High Voltage Chip Erase VIL VH(3) VIL X High Z
Product Identification
VIL VIL VIH A1-A14 = VIL, A9 = VH, A0 = VIL Manufacturer Code(4)
Hardware
A1-A14 = VIL, A9 = VH, A0 = VIH Device Code(4)
A0 = VIL Manufacturer Code(4)
Software(5)
A0 = VIH Device Code(4)
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1F, Device Code: DC.
5. See details under Software Product Identification Entry/Exit.

DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC 10 µA
ILO Output Leakage Current VI/O = 0V to VCC 10 µA
ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC 300 µA
ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3 mA
ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 50 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 2.1 mA 0.45 V
VOH1 Output High Voltage IOH = -400 µA 2.4 V
VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

5
0046P–FLASH–10/04
AC Read Characteristics
AT29C256-70 AT29C256-90 AT29C256-12 AT29C256-15
Symbol Parameter Min Max Min Max Min Max Min Max Units
tACC Address to Output Delay 70 90 120 150 ns
(1)
tCE CE to Output Delay 70 90 120 150 ns
tOE(2) OE to Output Delay 0 40 0 40 0 50 0 70 ns
tDF(3)(4) CE or OE to Output Float 0 25 0 25 0 30 0 40 ns
Output Hold from OE, CE or Address, 0 0 0 0 ns
tOH
whichever occurred first

Note: Not recommended for New Designs.

AC Read Waveforms(1)(2)(3)(4)

Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.

6 AT29C256
0046P–FLASH–10/04
 AT29C256

Input Test Waveforms and Measurement Level

tR, tF < 5 ns

Output Test Load

Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol Typ Max Units Conditions
CIN 4 6 pF VIN = 0V
COUT 8 12 pF VOUT = 0V
Note: 1. This parameter is characterized and is not 100% tested.

7
0046P–FLASH–10/04
AC Byte Load Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Set-up Time 0 ns
tAH Address Hold Time 50 ns
tCS Chip Select Set-up Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE) 90 ns
tDS Data Set-up Time 35 ns
tDH,tOEH Data, OE Hold Time 0 ns
tWPH Write Pulse Width High 100 ns

AC Byte Load Waveforms

WE Controlled

CE Controlled

8 AT29C256
0046P–FLASH–10/04
 AT29C256
Program Cycle Characteristics
Symbol Parameter Min Max Units
tWC Write Cycle Time 10 ms
tAS Address Set-up Time 0 ns
tAH Address Hold Time 50 ns
tDS Data Set-up Time 35 ns
tDH Data Hold Time 0 ns
tWP Write Pulse Width 90 ns
tBLC Byte Load Cycle Time 150 µs
tWPH Write Pulse Width High 100 ns

Program Cycle Waveforms(1)(2)(3)

Notes: 1. A6 through A14 must specify the page address during each high-to-low transition of WE (or CE).
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the page being programmed will be indeterminate.

9
0046P–FLASH–10/04
Software Data Protection Software Data Protection
Enable Algorithm(1) Disable Algorithm(1)
LOAD DATA AA LOAD DATA AA
TO TO
ADDRESS 5555 ADDRESS 5555

LOAD DATA 55 LOAD DATA 55

TO TO
ADDRESS 2AAA ADDRESS 2AAA

LOAD DATA A0 LOAD DATA 80

TO TO
ADDRESS 5555 WRITES ENABLED(2) ADDRESS 5555

LOAD DATA LOAD DATA AA

TO ENTER DATA TO
PAGE (64 BYTES)(4) PROTECT STATE ADDRESS 5555

Notes: 1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex). LOAD DATA 55
2. Data Protect state will be re-activated at end of pro- TO
gram cycle. ADDRESS 2AAA
3. Data Protect state will be deactivated at end of pro-
gram period.
4. 64 bytes of data MUST BE loaded. LOAD DATA 20
TO
ADDRESS 5555 EXIT DATA
PROTECT STATE(3)

LOAD DATA
TO
PAGE (64 BYTES)(4)

Software Protected Program Cycle Waveform(1)(2)(3)

Notes: 1. A6 through A14 must specify the page address during each high-to-low transition of WE (or CE) after the software code has
been entered.
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the page being programmed will be indeterminate.

10 AT29C256
0046P–FLASH–10/04
 AT29C256

Data Polling Characteristics(1)

Symbol Parameter Min Typ Max Units
tDH Data Hold Time 0 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay(2) ns
tWR Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.

Data Polling Waveforms

Toggle Bit Characteristics(1)

Symbol Parameter Min Typ Max Units
tDH Data Hold Time 0 ns
tOEH OE Hold Time 10 ns
(2)
tOE OE to Output Delay ns
tOEHP OE High Pulse 150 ns
tWR Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.

Toggle Bit Waveforms(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.

2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.

11
0046P–FLASH–10/04
Software Product Identification Entry(1) Software Product Identification Exit(1)
LOAD DATA AA LOAD DATA AA
TO TO
ADDRESS 5555 ADDRESS 5555

LOAD DATA 55 LOAD DATA 55

TO TO
ADDRESS 2AAA ADDRESS 2AAA

LOAD DATA 90 LOAD DATA F0

TO TO
ADDRESS 5555 ADDRESS 5555

PAUSE 10 mS ENTER PRODUCT PAUSE 10 mS EXIT PRODUCT

IDENTIFICATION IDENTIFICATION
MODE(2)(3)(5) MODE(4)

Notes: 1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).
2. A1 - A14 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code is 1F. The Device Code is DC.

12 AT29C256
0046P–FLASH–10/04
 AT29C256

NORMALIZED SUPPLY CURRENT

vs. TEMPERATURE
1.4
N
O 1.3
R
M
A 1.2
L
I 1.1
Z
E
D 1.0

I
0.9
C
C
0.8
-55 -25 5 35 65 95 125
TEMPERATURE (C)

NORMALIZED SUPPLY CURRENT

vs. ADDRESS FREQUENCY
1.1
N
O
R
M 1.0
A
L
I
0.9
Z
E VCC = 5V
D T = 25C
0.8
I
C
C
0.7
0 1 2 3 4 5 6 7
FREQUENCY (MHz)

NORMALIZED SUPPLY CURRENT

vs. SUPPLY VOLTAGE
1.4
N
O
R
M 1.2
A
L
I
1.0
Z
E
D
0.8
I
C
C
0.6
4.50 4.75 5.00 5.25 5.50
SUPPLY VOLTAGE (V)

13
0046P–FLASH–10/04
Ordering Information
tACC ICC (mA)
(ns) Active Standby Ordering Code Package Operation Range
70 50 0.3 AT29C256-70JC 32J Commercial
AT29C256-70TC 28T (0° to 70°C)
AT29C256-70JI 32J Industrial
AT29C256-70TI 28T (-40° to 85°C)
90 50 0.3 AT29C256-90JC 32J Commercial
AT29C256-90TC 28T (0° to 70°C)
AT29C256-90JI 32J Industrial
AT29C256-90TI 28T (-40° to 85°C)
120 50 0.3 AT29C256-12JC 32J Commercial
AT29C256-12TC 28T (0° to 70°C)
AT29C256-12JI 32J Industrial
AT29C256-12TI 28T (-40° to 85°C)
150 50 0.3 AT29C256-15JC 32J Commercial
AT29C256-15TC 28T (0° to 70°C)
AT29C256-15JI 32J Industrial
AT29C256-15TI 28T (-40° to 85°C)

Note: Not recommended for New Designs.

Package Type
32J 32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
28T 28-lead, Plastic Thin Small Outline Package (TSOP)

14 AT29C256
0046P–FLASH–10/04
 AT29C256

Packaging Information

32J – PLCC

PIN NO. 1 1.14(0.045) X 45˚

1.14(0.045) X 45˚
IDENTIFIER 0.318(0.0125)
0.191(0.0075)

E1 E B1 E2
B

e
A2
D1
A1
D
A

0.51(0.020)MAX
45˚ MAX (3X) COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

D2 A 3.175 – 3.556
A1 1.524 – 2.413
A2 0.381 – –
D 12.319 – 12.573
D1 11.354 – 11.506 Note 2
D2 9.906 – 10.922
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. E 14.859 – 15.113
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 E1 13.894 – 14.046 Note 2
and E1 include mold mismatch and are measured at the extreme E2 12.471 – 13.487
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum. B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
10/04/01

TITLE DRAWING NO. REV.

2325 Orchard Parkway
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) 32J B
R San Jose, CA 95131

15
0046P–FLASH–10/04
28T – TSOP

PIN 1
0º ~ 5º
c

Pin 1 Identifier Area

D1 D

e b L1

E A2 A SEATING PLANE GAGE PLANE

COMMON DIMENSIONS
A1 (Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 1.20
A1 0.05 – 0.15
A2 0.90 1.00 1.05
Notes: 1. This package conforms to JEDEC reference MO-183. D 13.20 13.40 13.60
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. D1 11.70 11.80 11.90 Note 2
3. Lead coplanarity is 0.10 mm maximum. E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.55 BASIC

12/06/02
TITLE DRAWING NO. REV.
2325 Orchard Parkway
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline 28T C
R San Jose, CA 95131 Package, Type I (TSOP)

16 AT29C256
0046P–FLASH–10/04
 Atmel Corporation Atmel Operations
2325 Orchard Parkway Memory RF/Automotive
San Jose, CA 95131, USA 2325 Orchard Parkway Theresienstrasse 2
Tel: 1(408) 441-0311 San Jose, CA 95131, USA Postfach 3535
Fax: 1(408) 487-2600 Tel: 1(408) 441-0311 74025 Heilbronn, Germany
Fax: 1(408) 436-4314 Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
Regional Headquarters Microcontrollers
Europe 2325 Orchard Parkway 1150 East Cheyenne Mtn. Blvd.
Atmel Sarl San Jose, CA 95131, USA Colorado Springs, CO 80906, USA
Route des Arsenaux 41 Tel: 1(408) 441-0311 Tel: 1(719) 576-3300
Case Postale 80 Fax: 1(408) 436-4314 Fax: 1(719) 540-1759
CH-1705 Fribourg
Switzerland La Chantrerie Biometrics/Imaging/Hi-Rel MPU/
Tel: (41) 26-426-5555 BP 70602 High Speed Converters/RF Datacom
Fax: (41) 26-426-5500 44306 Nantes Cedex 3, France Avenue de Rochepleine
Tel: (33) 2-40-18-18-18 BP 123
Asia Fax: (33) 2-40-18-19-60 38521 Saint-Egreve Cedex, France
Room 1219 Tel: (33) 4-76-58-30-00
Chinachem Golden Plaza ASIC/ASSP/Smart Cards Fax: (33) 4-76-58-34-80
77 Mody Road Tsimshatsui Zone Industrielle
East Kowloon 13106 Rousset Cedex, France
Hong Kong Tel: (33) 4-42-53-60-00
Tel: (852) 2721-9778 Fax: (33) 4-42-53-60-01
Fax: (852) 2722-1369
1150 East Cheyenne Mtn. Blvd.
Japan Colorado Springs, CO 80906, USA
9F, Tonetsu Shinkawa Bldg. Tel: 1(719) 576-3300
1-24-8 Shinkawa Fax: 1(719) 540-1759
Chuo-ku, Tokyo 104-0033
Japan Scottish Enterprise Technology Park
Tel: (81) 3-3523-3551 Maxwell Building
Fax: (81) 3-3523-7581 East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743

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0046P–FLASH–10/04 xM