SRI CHANDRASEKHARENDRA SARASWATHI VISWA

MAHAVIDYALAYA
(University U/S 3 of UGC Act 1956)
Accredited with “A” Grade by NAAC
ENATHUR, KANCHIPURAM - 631561

DEPARTMENT : EIE/MECHATRONICS
YEAR/SEM : SECOND/FOURTH
SUBJECT : DIGITAL ELECTRONICS
SUBJECT CODE : BMTF184T60
UNIT : I TO V

Prepared by

S. S. SARAVANA KUMAR,

Assistant Professor
Department of Electronics and Instrumentation Engineering
Sri Chandrasekharendra Saraswathi Viswa Mahavidyalaya
Enathur, Kanchipuram - 631561
 SEM IV L T P C
BRANCH : Mechatronics 3 0 - 3
DIGITAL ELECTRONICS
CODE : CATEGORY: PCC
(For Students admitted from 2018 onwards)

PREREQUISITE: Basic Electronics

COURSE OBJECTIVES
The course should enable the students to:
1. StudyvariousnumbersystemsandtosimplifythemathematicalexpressionsusingBoolean
functions – simpleproblems.
2. Study implementation of combinationalcircuits.
3. Study the design of various synchronous and asynchronouscircuits.
4. LearnabouttheStatereductiontechniques&varioushazardspresentinthecircuit
5. ExposethestudentstovariousmemorydevicesandtoDesigntheDigitalcircuitsusingHDL
programming.

UNITI NUMBERSYSTEMS&BOOLEANALGEBRA (9Hours)

Number Systems & Boolean Algebra: Introduction to Number Systems & Conversions - Boolean
algebra – Logic Gates & operations – Boolean Laws - Minimization of Boolean expressions - Boolean
expressions and Logic Diagrams -Universal building blocks - Negative logic.
Logic Simplifications: Truth tables and maps - Sum of products (SOP) and Product of Sum (POS) -
Simplification of logic functions using Karanaugh map - Minimization and Quine- McCluskey method
of minimization.

UNITII COMBINATIONALCIRCUITS (9Hours)

Arithmetic Circuits: Half Adder, Full Adder, Half Subtractor & Full Subtractor, Number
complements. Multiplexer & Demultiplexer, Decoder and Encoder
Code converters: BCD to Excess3, Gray, Seven Segment Display Conversions – Parity Generator and
Checkers.

UNITIII SYNCHRONOUSSEQUENTIALCIRCUITS (9Hours)

Basic latch circuits - Flip-flops, Truth table and excitation table- Analysis of Clocked Sequential
circuits- Shift Registers.
Counters: Synchronous counter design using JK, T, D flip flops, Up-down counter, BCD counter and
Ring counters.

UNITIV ASYNCHRONOUSSEQUENTIALLOGIC (9Hours)

AnalysisandDesignofAsynchronousSequentialCircuits-ReductionofStateandFlowTables- Multiple
Inputs- Race free State Assignment-Hazards
UNIT V LOGIC FAMILIES AND PROGRAMMABLE LOGIC DEVICES (9 Hours)

HDL Programming: Introduction to HDL Programming, HDL for Combinational Circuits, HDL for
sequential logic circuits.
Programmable Logic Devices: Programmable Logic Array (PLA) -Programmable Array Logic
(PAL) - PROM.

COURSE OUTCOME
The students should be able to:

CO1. Understand the basic number system and Boolean algebra.

CO2.UnderstandthebasicsofcombinationalandSequentialcircuits. CO3. Know
about Flip flops and theirdesigning.
CO4. Analyze about State reduction techniques and various hazards present in the circuit.
CO5. Understanding the concepts of VHDL programming for designing Digital circuits.

TEXT BOOKS
1. W.H. Gothmann, “Digital Electronics - An Introduction, Theory and Practice”, Prentice Hall of
India.2nd Edition,2000.
2. M.MorrisMano,“DigitalDesign”,4thEdition,PrenticeHallofIndiaPvt.Ltd.,2008/ Pearson
Education (Singapore) Pvt. Ltd., New Delhi,2003..
3. Frank Vahid “VHDL for Digital Design-With RTL design, VHDL & Verilog”- John Wiley
& Sons,2010.
4. Jain—Modern Digital Electronics, 2/e,TMH

REFERENCE BOOKS
1. A.AnandKumar,“SwitchingTheoryandLogicDesign”–PHI,2ndEdition
2. HeiserMan,“HandbookofDigitalICapplications”,PrenticeHall.2002.
3. T.L. Floyd & Jain, “Digital Fundamentals”, Pearson, 10 Edition,2010.
4. John F.Wakerly, “Digital Design”, Fourth Edition, Pearson/PHI,2008
5. Charles H.Roth. “Fundamentals of Logic Design”, 6th Edition, Thomson Learning, 2013
Edition,2000.

Mapping of COs with Pos

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1   
CO2   
CO3   
CO4      
CO5     

UNIT- I
 NUMBER SYSTEMS ANDCODES
AIM & OBJECTIVE
To understand the
variousnumbersystemsandtosimplifythemathematicalexpressionsusingBooleanfunctions.
PRE MCQ:
1. The parameter through which 16 distinct values can be represented is known as ________
a) Bit
b) Byte
c) Word
d) Nibble
Answer: c

2. Truth table is used to express

a) Boolean expression
b) Boolean map
c) Boolean matrix
d) Boolean addition
Answer: a

3. An important drawback of binary system is ________

a) It requires very large string of 1’s and 0’s to represent a decimal number
b) It requires sparingly small string of 1’s and 0’s to represent a decimal number
c) It requires large string of 1’s and small string of 0’s to represent a decimal number
d) It requires small string of 1’s and large string of 0’s to represent a decimal number
Answer: a

4. The largest two digit hexadecimal number is ________

a) (FE)16
b) (FD)16
c) (FF)16
d) (EF)16
Answer: C

5. The quantity of double word is ________

a) 16 bits
b) 32 bits
c) 4 bits
d) 8 bits
Answer: b
6. (170)10 is equivalent to ____________
 a. (FD)16
b. (DF)16
c. (AA)16
d. (AF)16
Answer: c
7. Octal to binary conversion: (24)8 =?
a) (111101)2
b) (010100)2
c) (111100)2
d) (101010)2
Answer: b
8. Convert binary to octal: (110110001010)2 =?
a) (5512)8
b) (6612)8
c) (4532)8
d) (6745)8
Answer: b
9. Perform binary addition: 101101 + 011011 = ?
a) 011010
b) 1010100
c) 101110
d) 1001000
Answer: d
10. Binary subtraction of 100101 – 011110 is?
a) 000111
b) 111000
c) 010101
d) 101010
Answer: a

THEORY:
1.1 INTRODUCTION:
 Electronic systems usually deal with information. Representation of information is called a
signal. Signal in electronics is generally in form of voltage or current. Value of a signal is
proportional to some physical quantity and it gives information about it. For example,
temperature represented in terms of voltagesignal.

 There are two types of signals which are different in terms of their characteristics with respect
to time andvalue.
1. AnalogSignals
2. DigitalSignals

 Asignalwhosevalueisdefinedatallinstancesoftimeiscalledcontinuoustimesignal.Ontheother
handsignalwhosevaluesaredefinedonlyatdiscreteinstancesoftimeiscalleddiscretetimesignal.
Most of the signals that occur in nature are analog in form. A discrete time signal can be
obtained from continuous time signal by process called sampling. This has been illustrated in
Fig.1.1.

Fig. 1.1: (a) Continuous time signal x(t) sampled at every T interval, (b) Resulting discrete time signal x(n)

 Similarlyifasignalcantakeanyvalueinagivenrangebetweensomeminimumandmaximumvalue
thenthesignaliscalledcontinuousvaluesignal.Ontheotherhandifasignaltakesonlycertainfixed
valuesinagivenrangethenitiscalleddiscretevaluesignal.Theprocessofconvertingacontinuous
value signal to a discrete value signal is called quantization. This is illustrated in Fig.1.2.

Fig. 1.2: Continuous value signal (solid line) and discrete value signal (dotted line)
Analog signal: Signals that are continuous in time and continuous in value are called analog signal.

Digital signal: Signals that are discrete in time and discrete in values are called digital signals. Digital
signalsaregenerallyprocessedbydigitalsystemslikecomputersandhencetheirvaluesarerepresented in terms of binary as shown in
Fig.1.2.

 Analogsignalbeingcontinuousintimewillhaveinfinitevaluesinanygivenperiodoftime.Practically a
digital system like computer cannot handle infinite values due to limited physical resources and
processing power. This is the reason why a continuous time signal has to be sampled and converted
to discrete timesignal.

 Again analog signals are continuous in value and hence can take any value in a given range. Now
ideally number of values in any given range will be infinite which cannot be represented by finite
numberofbitsonacomputer.Forexample,asshowninFig.1.2,withthreebitsusedforrepresenting values
only eight different values can be represented. Thus a continuous value signal has to be quantized
and converted to discrete valuesignal.

1.1.1 Levels ofIntegration

 Digital electronic circuits have become increasingly popular and successful due to integrated circuit
(IC) technology. Advancement in IC technology has made it possible to construct large number of
devices (eg. transistor, diode, resistors, capacitors, etc) on a very small chip. Classification of IC
technology based on number of components per chip is asfollows.

1. Small-scale integration (SSI), containing fewer than 100components

2. Medium-scale integration (MSI), containing 100 to 1000components
3. Large-scale integration (LSI), containing 1000 to 10,000components
4. Very large-scale integration (VLSI), containing more than 10,000components

1.1.2 Comparison of Analog and DigitalSystems

Analog Systems Digital Systems

1 Analog systems operate on Digitalsystemsoperateondiscretetime
continuous time and continuous and discrete value signals generally
value signals. represented in binary.
2 Analog systems are difficult to Digital systems are easy to design as
design. most of the components are in form of
Integrated circuits (IC).
3 Analog systems are mostly custom Digital systems have high degree of
made and lack flexibility. flexibility.
4 Less efficient in storage of More efficient in storage of information.
information.
 5 Analog signal processed by these Digital signal are more noise-immune
systems are affected by noise very compared to analog signals.
easily.
6 Relatively costly compared to Low cost due to mass production of
digital system components.
7 Analog systems are more sensitive Digital systems are less sensitive to
to parameter variation. parameter variation
8 No conversion of input signals are Input signals are converted from analog
required before processing to digital form before it is processed
9 As no conversion of input signal is Due to process of sampling and
required there is no loss of quantization there is loss of
information. information.
10 Analog systems are more efficient Digital systems may offer limitations for
for real time processing real time processing

1.2 Introduction to DigitalSystem:

 A digital system uses a building blocks approach. Many small operational units are interconnected
to make up the overallsystem.
 Themostbasiclogicalunitsystemisgatecircuit.Thereareseveraldifferenttypesofgateswitheach perform
differently from other logicgates.
 Digital signal consist of only two values, ‘0’ and ‘1’. These two values have logical meaning i.e. ‘1’
represents the existence of particular condition and ‘0’ represents the absence ofcondition.

 There are two types of tables are used in digitalsystem:

1. TruthTable:
Truth table plots inputs and outputs in terms of 1s and 0s.

2. FunctionTable:
Function table plots inputs and outputs in term of HIGH and LOW voltage levels.

 The design of digital system may be roughly divided into threestages;

1. SystemDesign:
It involves breaking the overall system into subsystem and specifying the characteristics of each
subsystem.Forexample,thesystemdesignofadigitalcomputersinvolvesspecifyingthenumber and type of memory,
ALU and i/p – o/pdevices.

2. Logic Design:
It involves how to interconnect basic logic building blocks to perform specific function. For example, to make a flip
flop different logic gates are needs to be connected in specific manner.
 3. CircuitDesign:
It involves specifying the interconnection of specific components like resistors, transistors, diodes, CMOS etc. to
create a logic gates.

1.2.1 Advantages of DigitalSystems

1. Digital systems are easier todesign
2. Information storage iseasy
3. Accuracy and precision aregreater
4. Digital systems are moreversatile
5. Digital circuits are less affected bynoise
6. More digital circuitry can be fabricated on ICchips

1.2.2 Logic Levels and Different types ofLogics

 Digital system use the binary number system. Therefore, two-state devices are used to represent the
two binary digits 1s & 0s by two different voltage levels, called HIGH andLOW.
 Normally, the binary 0 and 1 are represented by the logic voltage levels 0 V and +5V.
 Usually any voltage between 0 V to 0.8 V represents the logic 0 and any voltage between 2 V to 5 V
represents the logic 1. This voltage levels can be varies according to the different logicalsystems.
 There are three types of logics available in digitalsystems.
1. PositiveLogic
2. NegativeLogic
3. MixedLogic

1. PositiveLogic:
In positive logic high voltage level is represent as logic 1 and low voltage level is represent as logic 0.
High (1)

LeadingEdge TrailingEdge

Low (0)

Fig. 1.3: Illustration of positive logic

2. NegativeLogic:
In positive logic high voltage level is represent as logic 0 and low voltage level is represent as logic 1.

High (0)

LeadingEdge TrailingEdge

Low (1)
Fig. 1.4: Illustration of negative logic
3. MixedLogic:
This scheme uses positive logic in some portions (e.g inputs) of the system while applying negative logic (e.g. outputs)
in other portion of the system.

 SupposesomefunctionX=AB’+A’Bforthisfunctiontherepresentationofallthelogicsareas
follow;

A
B
X
’

A
’
B

Fig. 1.5: Representation of function X = AB’ + A’B

 Truth table of the given function for all the logics is shown asfollow;

Table 1.1: Truth table of Positive logic, Negative logic, Mixed logic for X = AB’ + A’B

PositiveLogic NegativeLogic MixedLogic

1.3 NUMBERSYSTEMS:
1.3.1 Introduction to NumberSystem:

 Definition &Importance

 Number system is the basis for counting various items. On hearing the word ‘number’, we
immediately think of the familiar decimal number system with 10 digits 0 to 9. But modern
computers communicate and operate with binary numbers which use only 2 digits 0 & 1. Also
differenttypesofnumbersystemslikeoctalandhexadecimalarealsousedwidely.Dependingupon the type
of number system, we use different digits to represent variousnumbers.
 Few Common Aspects to All NumberingSystems

(i) Base or Radix

Thenumberofsymbolsusedfortherepresentationofnumbersinanumbersystemisknownas its Base or Radix and is
generally denoted byr.

(ii) Digit
Each symbol in the number system is called a Digit.

(iii) The largest value of a digit is always one less than thebase
For ex, in decimal system, the largest digit is 9 (since base is 10)

(iv) Each digit position (i.e. place) represents a different multiple ofbase
Thismeansthatthenumbershavepositionalimportance.Hencethenumbersystemsareknown as Positional Weighted
Number System. It means that the value attached to a symbol depends on its location with respect to the
decimalpoint.

 For example decimal number 123.4 (base 10) can actually be representedas;
(123.4)10 = 1x102 + 2x101 + 3x100 +4x10-1

 In general, a number of any radix can be expressedas,

Nr = … + D3 x r3 + D2 x r2 + D1 x r1 + D0 x r0 + D-1 x r -1 + D-2 x r -2 + D-3 x r -3 +...

Where;
r is the base and Di is any valid digit in the number system of base r.

 The digits on the left side of the decimal point form the integer part of a number and those on the
right side form the fractionalpart.
 Theleftmostdigitinanynumberrepresentation,whichhasthegreatestpositionalweightoutofall the digits
present in that number is called the most significant digit(MSD).
 The right most digit in any number representation, which has the least positional weight out of all
the digits present in that number is called the least significant digit(LSD).

 Various NumberingSystems

 Different number systems are used in various applications. The commonly used number systems
along with their base, 1st digit, last digit and available digits are as shownbelow:
 Table 1.2: Illustration of various number system

Sr. Number Base First Last All

No System digit digit digits
1 Binary 2 0 1 0,1
2 Octal 8 0 7 0,1,2,3,4,5,6,7
3 Decimal 10 0 9 0,1,2,3,4,5,6,7,8,9
4 Hexadecimal 16 0 F 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
Note: In hexadecimal number system, meaning of A
A≈10, B≈11, C≈12, D≈13, E≈14 & F≈15.

1. DECIMAL NUMBERSYSTEM

 Decimal number system is the most familiar no. system used in day
day-to-day
day life. The decimal system
consists of 10 unique symbols. Hence the base or radix is 10.. It is a positional weighted system. In
thissystem,anynumber(integer,fractionormixed)ofanymagnitu
thissystem,anynumber(integer,fractionormixed)ofanymagnitudecanberepresentedbytheuse
decanberepresentedbytheuse of these
ten symbolsonly.

 Thedigitsontheleftsideofthedecimalpointformtheintegerpartofadecimalnumberwhilethose
onrightsidefromthefractionalpart.Thedigitsontherightofthedecimalpointhaveweightswhich are
negative powers of 10 and the digits to the left of the decimal point have weights which are positive
powers of 10. The sum of all the digits multiplied by their weights gives the total number
beingrepresented.

 In general, the value of any mixed decimalnumber

dn dn-1 dn-2 . . . d1 d0 . d-1 d-2 d-3 . . . d-k
is given by

(dn x 10n) + (dn-1 x 10n-1) + . . . + (d1 x 101) + (d0 x 100) + (d-1 x 10-1) + . . + (d-k x 10-k)

 Consider a decimal no. 9256.26. We represent itas:

9256.26 = 9 x 1000 + 2 x 100 + 5 x 10 + 6 x 1 + 2 x (1/10) + 6 x (1/100)

= 9 x 103 + 2 x 102 + 5 x 101 + 6 x 100 + 2 x 10-1 + 6 x 10-2

MSD . ... 103 102 101 100 10-1 10-2 10-3 .................. LSD

RADIX POINT
Fig 1.6: Decimal position values as power of 10
2. BINARY NUMBERSYSTEM

 Thebinarynumbersystemisapositionalweightedsystem.The
positionalweightedsystem.Thebaseorradixofthisnumbersystem
ofthisnumbersystem is 2.
Hence, it has two independent symbols. The base itself cannot be a symbol. The symbols used are 0
& 1. A binary digit is called a bit
bit.. A binary number consists of a sequence of bits, each of which
w is
either a 0 or a 1. The binary point separates the integer and fraction part. The weight of each bit
position is one power of 2 greater than the weight of the position to its immediate right. The place
values left on the binary point in binary are 664, 32, 16, 8, 4, 2 and1.

 In general, the value of any mixed binarynumber

bn bn-1 bn-2 . . . b1 b0 . b-1 b-2 b-3 . . . b-k

is given by
(bn x 2n) + (bn-1 x 2n-1) + . . . + (b1 x 21) + (b0 x 20) + (b-1 x 2-1) + . . + (b-k x 2-k)

MSB . ... 23 22 21 20 2-1 2-2 2-3 .................. LSB

RADIX POINT
Fig. 1.7: Binary position values as power of 2

 Counting inBinary

 Counting in binary is very similar to decimal counting. Start counting with 0, the next count is 1.
Movingahead,weput1inthecolumntotheleftandcontinuethe
Movingahead,weput1inthecolumntotheleftandcontinuethecounting.Thus,11isthemaximum
themaximum we can
count using two bits. Similarly, we can continue counting with 5, 6, ...bits.

Table 1.3: Counting in Binary

Decimal Binary Decimal Binary

Number Number Number Number
0 00000 11 01011
1 00001 12 01100
2 00010 13 01101
3 00011 14 01110
4 00100 15 01111
5 00101 16 10000
6 00110 17 10001
7 00111 18 10010
8 01000 19 10011
9 01001 20 10100
10 01010 21 10101
 Applications

 The binary number system is used in digital computers because the switching circuits used in these
computers use two-state
state devices such as transistors, diodes, etc. These devices have to exist in one of
the two possible states: ON of OFF, OPEN or CLOSED. So, these two states can be represented by
the symbols 0 and 1,respectively.

3. OCTAL NUMBERSYSTEM

 The octal number system was extensively used by early minicomputers. It is also a positional
weighted system. Its base or radix is 88. It has 8 independent symbols 0 to7.
 Sinceitsbase8=23,every3-bitgroupofbinarycanberepresentedbyanoctal
bitgroupofbinarycanberepresentedbyanoctaldigit.Anoctalnumber
digit.Anoctalnumber is, thus
1/3 rd. the length of the corresponding binarynumber.

MSD . ... 83 82 81 80 8-1 8-2 8-3 .................. LSD

RADIX POINT
Fig 1.8: Octal position values as power of 8

Table 1.4: Counting in Octal

Decimal Octal Decimal Octal

Number Number Number Number
0 0 11 13
1 1 12 14
2 2 13 15
3 3 14 16
4 4 15 17
5 5 16 20
6 6 17 21
7 7 18 22
8 10 19 23
9 11 20 24
10 12 21 25

 Usefulness of the OctalSystem

 In computer work, binary numbers up to 64 bits are not uncommon. These binary numbers do not
always represent a numerical quantity; they often represent some type of code. While dealingwith
 large binary numbers, it is convenient and more efficient for us to write the numbers in octal rather
thanbinary.Theeasewithwhichconversionscanbemadebetweenoctalandbinarymakestheoctal
sewithwhichconversionscanbemadebetweenoctalandbinarymakestheoctal system more attractive as a
shorthand means of expressing large binarynumbers.

4. HEXADECIMAL NUMBERSYSTEM

 Binarynumbersaretoolong.Thesenumbersarefineformachinesbuttaretoolengthytobehandled
byhumanbeings.So,thereisaneedtorepresentthebinarynumbersconcisely.Onenumbersystem
yhumanbeings.So,thereisaneedtorepresentthebinarynumbersconcisely.Onenumbersystem developed
with this objective is the hexadecimal number system (or Hex). Although it is somewhat difficult to
interpret than the octal number system, it has become the most po
popular
pular means of direct data entry
and retrieval in digitalsystems.

 The hexadecimal number system is positional weighted system. The base or radix is 16 that means,
ithas16independentsymbols.Thesymbolsusedare .sinceitsbaseis16=24,every 4 bit binary
ithas16independentsymbols.Thesymbolsusedare0to9andAtoF.sinceitsbaseis16=2
digit combination can be represented by one hexadecimal digit. So, a hexadecimal number is ¼ th the
length of the corresponding binarynumber.

 A 4-bit group is called a nibble.. Since computer words come in 8, 16, 32 bits and so on, they can be
easily represented in hexadecimal. The hexadecimal number system is particularly used for human
communications with computers. It is used in both large and smallcomputers.

MSD . ... 163 162 161 160 16-1 16-2 16-3 . . .LSD

RADIX POINT
Fig. 1.9: Hexadecimal position values as power of 16

Table 1.5: Counting in Hexadecimal

Decimal Number Hexadecimal Decimal Hexadecimal

Number Number Number
0 0 21 15
1 1 22 16
2 2 23 17
3 3 24 18
4 4 25 19
5 5 26 1A
6 6 27 1B
7 7 28 1C
8 8 29 1D
9 9 30 1E
 10 A 31 1F
11 B 32 20
12 C 33 21
13 D 34 22
14 E 35 23
15 F 36 24
16 10 37 25
17 11 38 26
18 12 39 27
19 13 40 28
20 14 41 29

1.3.2 Number BaseConversions:

 Definition andImportance

 The human beings use decimal number system while computer uses binary number system.
Therefore, it is essential to convert decimal number into its equivalent binary while feeding number
into computer and to convert binary number into its decimal equivalent while displaying result of
operation to the humanbeings.

 However, dealing with a large quantity of binary numbers of many bits is inconvenient for human
beings.Therefore,octalandhexadecimalnumbersareusedasashorthandmeansofexpressinglarge binary
numbers. Hence inter conversion among different number systems isrequired.

 Conversions between Decimal, Binary, Octal andHexadecimal

 The below table shows the decimal, binary, octal and hexadecimalnumbers.

Table 1.6: Conversions between Decimal, Binary, Octal and Hexadecimal

Decimal Binary Octal Hexadecima

l
0 0000 0 0
1 0001 1 1
2 0010 2 2
3 0011 3 3
4 0100 4 4
5 0101 5 5
6 0110 6 6
7 0111 7 7
8 1000 10 8
 9 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F

1. Binary to DecimalConversion

 Binary numbers can be converted to their decimal equivalents by the positional weights method. In
this method, each binary digit of the number is multiplied by its position weight and the product
terms are added to obtain the decimalnumber.

Ex 1: Convert (10101)2 to decimal

Solution:
Positional weights are: 24 23 22 21 20
1 0 1 0 1 = (1 x 24) + (0 x 23) + (1 x 22) + (0 x 21) + (1 x 20)
= 16 + 0 + 4 + 0 + 1
= 21
Hence, (10101)2 = (21)10

Ex 2: Convert (11011.101)2 to decimal

Solution:
Positional weights are: 24 23 22 21 20 . 2-1 2-2 2-3
1 1 0 1.1 0 1 = (1 x 24) + (1 x 23) + (0 x 22) + (1 x 21) + (1 x 20) + (1 x 2-1) + (0 x 2-2) +
(1 x 2-3)
= 16 + 8 + 0 + 2 + 1 + 0.5 + 0 + 0.125
= 27.625
Hence, (11011.101)2 = (27.625)10

2. Octal to DecimalConversion

 To convert an octal number to a decimal number, multiply each digit in the octal number by the
weight of its position and add all the productterms.
Ex 3: Convert (4057.06)8 to decimal

Solution:
Positional weights are: 83 82 81 80 . 8-1 8-2
4057.068 = (4 x 83) + (0 x 82) + (5 x 81) + (7 x 80) + (0 x 8-1) + (6 x 8-2)
= 2048 + 0 + 40 + 7 + 0 + 0.0937
= 2095.0937
Hence, (4057.06)8 = (2095.0937)10

3. Hexadecimal to Decimal Conversion

 Multiplyeachdigitinthehexnumberbyitspositionweightandaddallthoseproductterms.Inthis way, we
get the decimal equivalent of the hexadecimalnumber.

Ex 4: Convert (5C7)16 to decimal

Solution:
Positional weights are: 162 161 160
5C716 = (5 x 162) + (12 x 161) + (7 x 160)
= 1280 + 192 + 7
= 147910
Hence, (5C7)16 = (1479)10

Ex 5: Convert A0F9.0EB16 to decimal

Solution:
Positional weights are: 163 162 161 160.16-1 16-2 16-3
A0F9.0EB16 = (10 x 163) + (0 x 162) + (15 x 161) + (9 x 160) + (0 x 16-1) + (14 x 16-2)
+ (11 x 16-3)
= 40960 + 0 + 240 + 9 + 0 + 0.0546 + 0.0026
= 41209.057210
Hence, (A0F9.0EB)16 = (41209.0572)10

4. Decimal to Binary Conversion

 The conversion of decimal number to binary is carried out in 2 steps. In step 1, we have to convert
integer part and in step 2, we have to convert fractionalpart.
 For integer part conversion, we use successive division-by-2 method. In this method we repeatedly
divide the integer part of the decimal number by 2 until the quotient is zero. The remainder of each
division becomes the numeral in the new radix. The remainders are taken in the reverse order to
form a new radix number. This means that the first remainder is the LSD and the last remainder is
the MSD in the new radix number. Thus the integers read from bottom to top give the equivalent
binaryfraction.

 Similarly, for fractional part, we use successive multiplication-by-2 method. In this method, the
number to be converted is multiplied by the radix of new number, producing a product that has an
integer part and a fractional part. The integer part (carry) of the product becomes a numeral in the
new radix number. The fractional part is again multiplied by the radix and this process is repeated
until fractional part reaches 0 or until the new radix number is carried out to significant digits. The
integer part (carry) of each product is read from top to bottom to represent the new radixnumber.

Ex 6: Convert 5210 to binary

 Here the number is integer number so we need to divide the given decimal number by 2 and read the
remainders from bottom to top to get the equivalent binarynumber.

2 52 Remainder
2 26 0
2 13 0
2 6 1
2 3 0
2 1 1
0 1

Hence, (52)10 = (110100)

Ex 7: Convert (163.875)10 to binary

Solution:
Step 1: Separate the integer and fractional parts of the decimal number. Now for integer part, we carry successive division-by-2
method as follows:

2 163 Remainder 1
1
2 81
0
2 40 0
2 20
2 10
 2 5 0
2 2 1
2 1 0
0 1

So, 16310 = (10100011)2

Step 2: Now the fraction part is 0.87510. Carrying out successive multiplication-by-2 as follows: 0.875 x 2=1.75

1
0.75 x 2=1.5 1
0.5 x 2=1.0 1

So, 0.87510 = 0.1112

Hence. (163.875)10 = (10100011.111)2

5. Decimal to OctalConversion

 DecimaltoOctalconversion canbedoneinsimilarwayasdecimaltobinaryconversion.Theinteger and

fractional parts are to be separated and the same procedure is carried out. But the division and
multiplicationarecarriedoutby8asthebaseofoctalnumberis8.Followingthesamesteps,wecan get the
equivalent octal number of the given decimalnumber.

Ex 8: Convert 378.9310 to octal

Solution:
Step1: Conversion of integer part by successive division-by-8 method.

8 378 Remainder
8 47 2
8 5 7
0 5

So, (378)10 = (572)8

Step 2: Conversion of fractional part by successive multiplication-by-8 method.

0.93 x 8 = 7.44 7
0.44 x 8 = 3.52 3
0.52 x 8 = 4.16 4
0.16 x 8 = 1.28 1
So, 0.9310 = 0.73418

Hence, (378.93)10 = (572.7341)8

6. Decimal to Hexadecimal Conversion

 Decimal to hexadecimal conversion is carried out by 2 steps. In the first step, the integer part of the
decimalnumberisdividedby16successivelyandtheremainderisnoted.Theremaindersreadfrom bottom to
top gives the equivalent hexadecimal integer. In the second step, the successive
multiplicationoffractionalpartby16isdoneandtheintegersarenoteddown.Readingtheintegers from
bottom to top gives the hexadecimalfraction.

Ex 9: Convert (3509.75)10 to hexadecimal

Solution:
Step1: Conversion of integer part by successive division-by-16 method

16 3509 Remainder
5
16 219
11 =B
16 13 13 =D
0
So, (3509)10 =(DB5)16

Step 2: Conversion of fractional part by successive multiplication-by-16 method.

0.75 x 16 =12.0 12 =C

So, (0.75) 10 = (0.C)16

Hence, (3509.75)10 =(DB5.C)16

7. Octal to BinaryConversion

 Toconvertagivenoctalnumbertobinary,justreplaceeachoctaldigitbyits3-bitbinaryequivalent.

Ex 9: Convert 367.528 to binary.

Solution:
Given octal number is 3 6 7 . 5 2

Convert each octal digit to binary 011 110 111 . 101 010

Hence, (367.52)8 = (11110111.101010)2

8. Hexadecimal to Binary Conversion

 To convert a given hexadecimal number to binary, just replace each hexadecimal digit by its 4-bit
binaryequivalent.
Ex 10: Convert 4BAC16 to binary.

Solution:
Given hexadecimal number is 4 B A C

Convert each digit to 4-bit binary 0100 1011 1010 1100

Hence, (4BAC)16 = (100101110101100)2

Ex 11: Convert 3A9.B0D16 to binary.

Solution:
Given hexadecimalnumberis 3 A 9 . B 0 D

Convert each digit to 4-bit binary 0011 1010 1001 . 1011 0000 110

Hence, (3A9.B0D)16 = (1110101001.101100001101)2

9. Binary to OctalConversion

 Toconvertabinarynumbertoanoctalnumber,startingfromthebinarypointmakegroupsof3bits each, on
either side of the binary point and replace each 3-bit binary group by the equivalent octal digit.
Ex 12: Convert 110101.1010102 to octal.

Solution:
Group of 3 bits are 110 101 . 101 010

Convert each group to octal 6 5 . 5 2

Hence, (110101.101010)2 = (65.52)8

Ex 13: Convert 10101111001.01112 to octal.

Solution:
Group of 3bitsare 10 101 111 001 . 011 1
 = 010 101 111 001 . 011 100

Convert each groupto octal 2 5 7 1 . 3 4

Hence, (10101111001.0111)2 = (2571.34)8

10. Binary to HexadecimalConversion

 Toconvertabinarynumbertoanoctalnumber,startingfromthebinarypointmakegroupsof4bits each, on
either side of the binary point and replace each 4-bit binary group by the equivalent
hexadecimaldigit.

Ex 14: Convert 1011111011.0111112 to hexadecimal.

Solution:
Group of 4 bits are 10 1111 1011 . 0111 11

0010 1111 1011 . 0111 1100

Convert each group to hex 2 F B . 7 C

Hence, (1011111011.011111)2 = (2FB.7C)16

11. Octal to Hexadecimal Conversion

 To convert an octal number to hexadecimal, the simplest way is to first convert the given octal
number to binary and then the binary number tohexadecimal.

Ex 15: Convert 1245 to hex.

Solution:
Given octal number is 1 2 4 5

Convert each octal digit to binary 001 010 100 110

Group of 4 bits are 0010 1010 0110

Convert each 4–bit group to hex 2 A 6

Hence, (1245)8 = (2A6)16

Ex 16: Convert 756.6038 to hex.

Solution:
Given octalnumberis 7 5 6 . 6 0 3

Convert each octal digitto binary 111 101 110 . 110 000 011

Group of 4bitsare 0001 1110 1110 . 1100 0001 1000

Convert each 4–bit groupto hex 1 E E . C 1 8

Hence, (756.603)8 = (1EE.C18)16

12. Hexadecimal to Octal Conversion

 To convert hexadecimal number to octal, the simplest way is to first convert the given hexadecimal
number to binary and then the binary number tooctal.
Ex 17: Convert B9F.AE16 to octal.

Solution:
Given hexnumber is B 9 F . A E

Convert each hex digit to binary 1011 1001 1111 . 1010 1110

Group of 3 bits are 101 110 011 111 . 101 011 100

Convert each 3–bit group to octal 5 6 3 7 . 5 3 4

Hence, (B9F.AE)16 = (5637.534)8

13. Any radix r number to DecimalConversion

 Wecanconvertagivennumberinradixrtodecimalbymultiplyingeachdigitbyitspositionalweights and
taking sum of all theproducts.
Ex 18: Convert 12213 to decimal.
Solution:
Here, the given number is in base 3. Its positional weights are: 33 32 31 30
1 2 2 1 = (1 x 33) + (2 x 32) + (2 x 31) + (1 x 30)
= 27 + 18 + 6 + 1= 52
Hence, (1221)3 = (52)10
Ex 19: Convert 234.025 to decimal.

Solution:
Here, the given number is in base 5. Its positional weights are: 52 51 50 . 5-1 5-2
2 3 4 . 0 2 = (2 x 52) + (3 x 51) + (4 x 50) + (0 x 5-1) + (2 x 5-2)
= 50 + 15 + 4 + 0 + 0.08
= 69.08
Hence, (234.02)5 = (69.08)10

14. Decimal to any radix rConversion

 Decimal number can be converted in any radix by 2 steps. In step1, the integer part of the decimal
number is divided successively by the radix r and the remainders are noted down. Taking the
remainders from bottom to top gives the radix r equivalent of the integer part. Similarly, the
fractional part is successively multiplied by the radix r and the integer part of the result is noted
down. Noting the carry from top to bottom gives the fractional part equivalent in radixr.

Ex 20: Convert 1989.3510 to base 12.

Solution:
Step 1: Separate the integer and fractional parts of the decimal number. Now for integer part, we carry
successive division-by-12 method as follows:
12 1989
Remainder 9
12 165 9
12 13 1
12 1 1
0
So, (1989)10 = (1199)12

Step 2: Now the fraction part is 0.3510. Carrying out successive multiplication-by-12 as follows:

0.35 x12 = 4.2 4

0.2 x12 = 2.4 2
0.4 x12 = 4.8 4

So, 0.3510 = 0.42412

Hence. (1989.35)10 = (1199.424)12

15. Find the value of unknownbase

Ex 21: Determine b if (33)10 =

(201)b Solution:
We have, (33)10 = (201)b
33 = 2 x b2 + 0 x b1 + 1 x b0
= 2b2 +
1 2b2 =32
b2 =16
b =±4
But base of any number cannot be negative. Hence value of b = 4.

Ex 22: Determine b if (193)b = (623)8

Solution:
We have, (193)b = (623)8
1 x b2 + 9 x b1 + 3 x b0 = 6 x 82 + 2 x 81 + 3 x 80
b2 + 9b + 3 = 384 + 16 + 3 b2
+ 9b + 3 = 403
b2 + 9b – 400 = 0 b
= 16, b = -25

As base is always positive, value of b=16.

16. Binary Coded Decimal(BCD)

 Itisanumericcodethatisusedtorepresentdecimalusingbinarybitsi.e.1’sand0’s.Itisdifferent
from representation of a decimal number in binary system i.e. base 2 system.
 In BCD representation each digit of a decimal number is represented by a group of four bits. These
bits are given with weights of 8-4-2-1 and hence many a times BCD code is also called 8421 code.
Code for each digit of decimal is asfollows.
Table 1.7: Conversions between Decimal to BCD code

Decimal BCD
Digit code
8421
0 0000
1 0001
2 0010
3 0011
 4 0100
5 0101
6 0110
7 0111
8 1000
9 1001

Ex 23: (58)10 = ( )BCD

Solution:
Decimal: 5 8

0101 1000
Thus (58)10 = (01011000)BCD.

 Itshouldbenotedthatbinaryrepresentationof(58) 10willbe(111010)2whichisquitedifferentfrom the

BCDrepresentation.

Ex 23: (001001011001)BCD = ()10

Solution:
BCD: 0010 01011001

2 5 9
(001001011001)BCD = (259)10

 It can be observed that BCD codes are less efficient for representation compared to binary as it
requiresmorenumberofbitsthenrequiredinbinaryrepresentation.However,itispopularbecause of its ease
of conversion
ersion to and fromdecimal.
BOOLEAN ALGEBRA
AIM:
TosimplifythemathematicalexpressionsusingBooleanfunctions

PRE MCQ
1. In boolean algebra, the OR operation is performed by which properties?
a) Associative properties
b) Commutative properties
c) Distributive properties
d) All of the Mentioned
Answer: d

2. The expression for Absorption law is given by _________

a. A + AB = A
b. A + AB = B
c. AB + AA’ = A
d. A + B = B + A
Answer: a

3. According to boolean law: A + 1 = ?

a) 1
b) A
c) 0
d) A’
Answer: a

4. The involution of A is equal to _________

a) A
b) A’
c) 1
d) 0
Answer: a

5. A(A + B) = ?
a. AB
b. 1
c. (1+AB)
d. A
Answer: d

6. DeMorgan’s theorem states that _________

 a) (AB)’ = A’ + B’
b) (A + B)’ = A’ * B
c) A’ + B’ = A’B’
d) (AB)’ = A’ + B
Answer: a

7. (A + B)(A’ * B’) = ?
a. 1
b. 0
c. AB
d. AB’
Answer: b
8. Complement of the expression A’B + CD’ is _________
a) (A’ + B)(C’ + D)
b) (A + B’)(C’ + D)
c) (A’ + B)(C’ + D)
d) (A + B’)(C + D’)
Answer: d

9. Simplify Y = AB’ + (A’ + B)C.

a) AB’ + C
b) AB + AC
c) A’B + AC’
d) AB + A
Answer: a

10. The boolean function A + BC is a reduced form of ____________

a) AB + BC
b) (A + B)(A + C)
c) A’B + AB’C
d) (A + C)B
Answer: b

THEORY:

LOGICGATES:

 Logicgatesarethefundamentalbuildingblocksofdigitalsystems.Theyarethephysicaldevicesthat
performs the basic Boolean operations of AND, OR andNOT.
 Inputandoutputsoflogicgates(thatisbasicallyavoltagesignal)canoccuronlyintwolevels.These two
levels are termed as High and Low or True and False or ON and OFF or simply 1 and 0. In
 representation of higher of the two voltage levels is symbolized as 1 and lower symbolized as 0 the
gate is said to be positive logic gate. However, if higher of the two voltage levels is symbolized as 0
and lower as 1 then it is said to be negative logicgate.
 Inputoutputbehaviorofagateisgenerallyrepresentedusingtruthtable.Itisatablethatlistsoutput for all
possible combinations ofinputs.

 Therearetotalsevenlogicgatesinwhichthreearebasiclogicgates(AND,OR,NOT)andtwoare
universal logic gates (NAND, NOR).

 Various basic gates are discussed asfollows;

NOTGate:

 NOT gate has one inputs and one output. The output becomes logic 1 when input is at logic 0 and
outputbecomeslogic0whentheinputisatlogic1.Thusitinvertsorcomplementsthelogicavailable at input
and hence called and inverter or complement. It is represented by a bar over the variable
“̅”orwithasymbol“ ’ ”. Thus,forexample,X =A΄orX= Areadas“Xis equaltoNotAorAbar or A
complement”. NOT gate and its truth table are shown in fig.

Fig. : Illustration of NOT gate

ANDGate:
 AND gate means all or nothinglogic
 AND gate has two or more inputs and one output. The output becomes logic 1 only when each one
ofitsinputisatlogic1.Forallotherinputcombinationsitgivesoutputlogic0.Itisrepresentedbya symbol •.
 Thus, for example, X = A · B (also written simply as X = AB) is read as “X is equal to A AND B”.
Two input AND gate and its truth table is shown in fig.1.11.

ORGate:

 OR gate means any or alllogic

 OR gate has two or more inputs and one output. The output becomes logic 1 when at least
(minimum) one of the inputs is at logic 1. It is represented by a symbol +. Thus, for example, X = A
+ B is read as “X is equal to A OR B”. Two input AND gate and its truth table is shown in fig.1.12.

Exclusive OR Gate(EX-OR):

 It also means Inequality detector because it gives output high when both inputs aredifferent.
 Exclusive OR gate give output equal to 1 when the two inputs are exclusively different. This is the
reasonwhyitisalsoknownasinequalitygate.Theschematicsymbolandtruthtableofthegateis
shown in fig. 1.13. It is represented by a symbol  . Thus, for example, X  A B is read as “X is
 equal to A XOR B.” The logic expression this gate in terms of AND, OR and NOT operation is
X  A  B  AB  AB .
Exclusive NOR Gate(EX-NOR):

 It also means equality detector because it gives output high when both inputs aresame.
 Exclusive NOR gate is XOR gate followed by inverter. Thus it is complement of XOR gate. This
is the reason why it is also known as equality gate. The logic symbol, logic expression, schematic
symbol, truth table of the gate is shown in fig.
 X = AB +A’B’

Fig. : Illustration of EX-NOR gate

 UniversalGates:
 NANDandNORgatesareknownasauniversalgatesbecausefromthistwogatesallothergatescan be
constructed.
NANDGate:

 NANDgaterepresentscombinationofANDgatefollowedbyNOTgate.Itrepresentscomplementof AND
operation. Schematic symbol of NAND gate and its truth table are shown in fig. 1.15. Thelogic
 Expression is given as X = 𝐴. 𝐵 or X = (A·B)’
 Fig. : Illustration of NAND gate

 NAND gate as Universalgate

1. Implementing NOTgate
 All NAND input pins connect to the input signal A gives an outputA’.

2. Implementing ANDgate
 The AND is replaced by a NAND gate with its output complemented by a NAND gateinverter.

3. Implementing ORgate
 The OR gate is replaced by a NAND gate with all its inputs complemented by NAND gateinverters.
7. NOR Gate:

 NORgaterepresentscombinationofORgatefollowedbyNOTgate.ItrepresentscomplementofOR
operation.SchematicsymbolofNORgateanditstruthtableareshowninfig.4.16.Thelogic expression is
given as X  ( A  B) or X = (A+B)’.

 NOR gate as Universalgate.

1. Implementing NOTgate
 All NOR input pins connect to the input signal A gives an outputA`.

2. Implementing ANDgate
 The AND gate is replaced by a NOR gate with all its inputs complemented by NOR gateinverters.
 3. Implementing ORgate
 The OR is replaced by a NOR gate with its output complemented by a NOR gateinverter.

 Gates with More Inputs

 Any logic gates can be designed to accept three or more inputvalues.

As an example, three-input AND gate produces an output of 1 only if all input values are1.
ConstructingGates
 A transistor is a device that acts, depending on the voltage level of an input signal, either as a wire
that conducts electricity or as a resistor that blocks the flow ofelectricity
 A transistor has no moving parts, yet acts like aswitch.
 It is made of a semiconductor material, which is neither a particularly good conductor of electricity,
such as copper, nor a particularly good insulator, such asrubber.
 A transistor is shown in fig.1.18.

Fig. 1.18: Transistor

 A transistor has threeterminals

1. Asource
2. Abase
3. An emitter, typically connected to a groundwire
 If the electrical signal is grounded, it is allowed to flow through an alternative route to the ground
(literally) where it can do noharm.
 Itturnsoutthat,becausethewayatransistorworks,theeasiestgatestocreatearetheNOT,NAND, and NOR
gates shown in fig.1.19.
Fig. 1.19: Logic gates using transistor
2.1 BOOLEAN ALGEBRA:
 Inventor of Boolean algebra was George Boole (1815 -1864).

 Designing of any digital system there are three mainobjectives;

1) Build a system which operates within given specifications
2) Build a reliablesystem
3) Minimize resources

 Boolean algebra is a system of mathematicallogic.

 Any complex logic can be expressed by Booleanfunction.
 Boolean algebra is governed by certain rules andlaws.
 Boolean algebra is different from ordinary algebra & binary numbersystem.
In ordinary algebra; A + A = 2A and AA = A2, here A is numericvalue.
 In Booleanalgebra;
A + A = A and AA = A, here A has logical significance, but no numeric significance.

Table 2.1: Difference between Binary, Ordinary and Boolean system

Binary no. system Ordinary no. system Boolean algebra

1 + 1 = 10 1+1=2 1+1=1

 In Boolean algebra there is nothing like subtracting or division, no negative or fractionalnumbers.

 Boolean algebra represent logical operation only. Logical multiplication is same as AND operation
and logical addition is same as ORoperation.
 Boolean algebra has only two values 0 &1.
 In Booleanalgebra;
If A = 0 then A ≠ 1. & If A = 1 then A ≠ 0.

 Let’s introduce Boolean algebra by considering a practicalproblem:

 Suppose a system which transmitting 2 bit binary information over 2 line to anothersystem.
 So with 2 line, 4 unique code could berepresented.
 The receiving system may need to identify the presence of certain transmittedcodes.
 As an example suppose system is to identify the occurrence of the code representing the decimal
number 1 and 2. Each one of these code appear on the 2 lines, a circuit is to generate an output1.
 When any other code present the output should be0.
Table 2.2: 2 bit binary to decimal conversion

Binar Decimal
y
00 0
01 1
10 2
11 3
 The method of implementing the system is shown in followingfig.
 We want output 1 if decimal 1 & 2 otherwise 0 as definedabove.
 Below circuit generate output 1 when A = 0 & B = 1 or A = 1 & B =0.

Fig. 2.1: A logic system

2.1.1 Advantages of BooleanAlgebra

1. Minimize the no. of gates used incircuit.

2. Decrease the cost ofcircuit.
3. Minimize theresources.
4. Less fabrication area is required to design acircuit.
5. Minimize the designer’stime.
6. Reducing to a simple form. Simpler the expression more simple will behardware.
7. Reduce thecomplexity.

2.1.2 Axioms of BooleanAlgebra

 Axioms or postulate of Boolean algebra are a set of logical expression that we accept without proof
& upon which we can build a set of usefultheorems.

Axioms 1: 0 · 0 =0
Axioms 2: 0 · 1 =0
Axioms 3: 1 · 0 =0
Axioms 4: 1 · 1 =1
Axioms 5: 0 + 0 =0
Axioms 6: 0 + 1 =1
Axioms 7: 1 + 0 =1
Axioms 8: 1 · 1 = 1
Axioms 9: 1’ = 0
Axioms 10: 0’ = 1
2.1.3 Types of logiccircuit
 There are two types of logiccircuit;
1) Sequentialcircuit
2) Combinationalcircuit

2.1.3.1 Difference between combinational & sequentialcircuit

Table 2.3: Difference between combinational and sequential circuits

Combinational Circuit Sequential Circuit

Output is dependent only on the input at Output is dependent on present input and
the same instant of time past output.
It does not contains memory elements. It contains memory element.

Itsbehaviorisdescribedbythesetofoutput Its behavior is described by the set of next

function. state function and the set of output function.

No feedback is available. Feedback is available.

It does not contains periodic clock signal. It contains clock signals.
Faster than sequential circuit. Slower than combinational circuit.
e.g. half adder, full adder, etc. e.g. Flip flop, counter, etc.

2.2 LAWS OF BOOLEANALGEBRA:

1. ComplementationLaws:

 The term complement simply means to invert, i.e. to change 0’s to 1’s and 1’s to0’s.
Law 1: 0’ =1
Law 2: 1’ = 0
Law 3: If A = 0 then A’ = 1
Law 4: If A = 1 then A’ = 0
Law 5: A’’ = A
2. ANDLaws:
Law 1: A · 0 = 0
Law 2: A · 1 = A
Law 3: A · A = A
Law 4: A · A’ =0

3. ORLaws:

Law 1: A + 0 = A
Law 2: A + 1 = 1
Law 3: A + A = A
Law 4: A + A’ = 1

4. CommutativeLaws:

 Commutative laws allow change in position of AND or ORvariables.

Law 1: A + B = B + A
Proof:

 This law can be extended to any numbers of variables fore.g.

A + B + C = B + A + C = C + B + A = C + A +B

Law 2: A · B = B · A
Proof:

 This law can be extended to any numbers of variables fore.g.

A·B·C=B·A·C=C·B·A=C·A·B
5. AssociativeLaws:

 The associative laws allow grouping ofvariables.

Law 1: (A + B) + C = A + (B + C)
Proof:

 This law can be extended to any no. of variables fore.g.

A + (B + C + D) = (A + B + C) + D = (A + B) + (C + D)

Law 2: (A · B) · C = A · (B · C)
Proof:

 This law can be extended to any no. of variables fore.g.

A · (B · C · D) = (A · B · C) · D = (A · B) · (C · D)

6. DistributiveLaws:

 The distributive laws allow factoring or multiplying out ofexpressions.

Law 1: A (B + C) = AB + AC
 Proof:

Law 2: A + BC = (A + B) (A + C)
Proof: R.H.S. = (A + B) (A + C)
= AA + AC + BA + BC
= A + AC + BA + BC
= A+BC (B’cz 1 + C + B = 1 + B =1)
=L.H.S.

Law 3: A + A’B = A + B
Proof: L.H.S. = A +A’B
= (A + A’) (A + B)
=A+B
= R.H.S.

7. IdempotenceLaws:

 Idempotence means the samevalue.

Law 1: A · A = A
Proof:
Case 1: If A = 0  A · A = 0 · 0 = 0 = A Case
2: If A = 1  A · A = 1 · 1 = 1 = A
 Law 2: A + A = A
Proof:
Case 1: If A = 0  A + A = 0 + 0 = 0 = A Case
2: If A = 1  A + A = 1 + 1 = 1 = A

8. Complementation Law / NegationLaw:

Law 1: A · A’ = 0
Proof:
Case 1: If A = 0  A’ = 1 So, A · A’ = 0 · 1 =0
Case 2: If A = 1  A’ = 0 So, A · A’ = 1 · 0 =0

Law 2: A + A’ = 1
Proof:
Case 1: If A = 0  A’ = 1 So, A + A’ = 0 + 1 = 1 Case
2: If A = 1  A’ = 0 So, A + A’ = 1 + 0 = 1

9. Double NegationLaw:

 This law states that double negation of a variables is equal to the variableitself.
Law 1: A’’ = A
Proof:
Case 1: If A = 0  A’’ = 0’’ = 1’ = A
Case 2: If A = 1  A’’ = 1’’ = 0’ = A

 Any odd no. of inversion is equivalent to singleinversion.

 Any even no. of inversion is equivalent to no inversion atall.
10. Identity Law:
Law 1: A · 1 = A
Proof:
Case 1: If A= 1  A · 1 = 1 · 1 = 1 =A
Case 2: If A= 0  A · 0 = 0 · 0 = 0 =A

Law 2: A + 1 = 1
Proof:
Case 1: If A= 1  A + 1 = 1 + 1 = 1 =A
Case 2: If A= 0  A + 0 = 0 + 0 = 0 =A

11. Null Law:

Law 1: A · 0 = 0
Proof:
Case 1: If A= 1  A · 0 = 1 · 0 = 0 =0
Case 2: If A= 0  A · 0 = 0 · 0 = 0 =0

Law 2: A + 0 = A
Proof:
Case 1: If A= 1  A + 0 = 1 + 0 = 1 =A
Case 2: If A= 0  A + 0 = 0 + 0 = 0 =A

12. Absorption Law:

Law 1: A + AB = A
 Proof: L.H.S. = A +AB
= A (1 +B)
= A (1)
=A
R.H.S.

Law 2: A (A + B) = A Proof:
L.H.S. = A (A + B)
= A · A + AB
= A + AB
= A (1 + B)
= A (1)
=A
= L.H.S.

13. ConsensusTheorem:

Theorem 1: A · B + A’C + BC = AB + A’C

Proof: L.H.S. = AB + A’C +BC
= AB + A’C + BC (A +A’)
= AB + A’C + BCA + BCA’
= AB (1 + C) + A’C (1 + B)
= AB + A’C
= R.H.S.

 This theorem can be extendedas,

AB + A’C + BCD = AB + A’C

Theorem 2: (A + B) (A’ + C) (B + C) = (A + B) (A’ + C)

Proof: L.H.S. = (A + B) (A’ + C) (B + C)
= (AA’ + AC + A’B + BC) (B + C)
= (0 + AC + A’B + BC) (B + C)
= ACB +ACC +A’BB + A’BC + BCB + BCC
= ABC + AC + A’B + A’BC + BC + BC
= ABC + AC + A’B + A’BC + BC
= AC (1 + B) + A’B (1 + C) + BC
= AC + A’B+BC ................................... (1)

R.H.S. = (A + B) (A’ + C)
= AA’ + AC + BA’ + BC
= 0 + AC + BA’ + BC
= AC + A’B+BC ................................... (2)
 Equation (1) = Equation (2) So.
L.H.S = R.H.S.

 This theorem can be extended to any no. ofvariables.

(A + B) (A’ + C) (B + C + D) = (A + B) (A’ + C)

14. Transpositiontheorem:
Theorem: AB + A’C = (A + C) (A’ +B)
Proof: R.H.S. = (A + C) (A’ +B)
= AA’ + AB + CA’ + CB
= 0 + AB + CA’ + CB
= AB + CA’ + CB
= AB+A’C (B’cz of AB + A’C + BC = AB +A’C)
=L.H.S.

15. De Morgan’sTheorem:

Law 1: (A + B)’ = A’ · B’
Proof:

Law 2: (A· B)’ = A’ + B’

16. Duality Theorem:

 Duality theorem arises as a result of presence of two logic system i.e. positive & negative logic
system.
 This theorem helps to convert from one logic system toanother.
 From changing one logic system to another following steps aretaken:
1) 0 becomes 1, 1 becomes0.
2) AND becomes OR, OR becomesAND.
3) ‘+’ becomes ‘·’, ‘·’ becomes ‘+’.
4) Variables are not complemented in theprocess.

2.3 REDUCTION OF BOOLEAN EXPRESSIONS:

2.3.1 Demorganize the followingfunctions

Example 1: [(A + B’) (C + D’)]’

Answer: [(A + B’) (C + D’)]’

= (A + B’)’ + (C + D’)’
= A’ B’’ + C’D’’
= A’B + C’D

Example 2: [(AB)’ (CD + E’F) ((AB)’ + (CD)’)]’

Answer: [(AB)’ (CD + E’F) ((AB)’ + (CD)’)]’

= (AB)’’ + (CD + E’F)’ + ((AB)’ + (CD)’)’
 = AB + [(CD)’ (E’F)’] + [(AB)’’ (CD)’’]
= AB + (C’ + D’) (E + F’) + ABCD

Example 3: [(AB)’ + A’ + AB]’

Answer: [(AB)’ + A’ + AB]’

= AB’’ · A’’ · AB’
= ABA (A’ + B’)
= AB (A’ + B’)
= ABA’ + ABB’
=0

Example 4: [P (Q + R)]’

Answer: [P (Q + R)]’
= P’ + (Q + R)’
= P’ + Q’ R’

Example 5: [(P + Q’) (R’ + S)]’

Answer: [(P + Q’) (R’ + S)]’

= (P + Q’)’ + (R’ + S)’
= P’ Q’’ + R’’ S’
= P’Q + RS’

Example 6: [[(A + B)’ (C + D)’]’ [(E + F)’ (G + H)’]’]’

Answer: [[(A + B)’ (C + D)’]’ [(E + F)’ (G + H)’]’]’

= [(A + B)’ (C + D)’]’’ + [(E + F)’ (G + H)’]’’
= [(A + B)’ (C + D)’] + [(E + F)’ (G + H)’]
= A’B’C’D’ + E’F’G’H’

2.3.2 Reducing the followingfunctions

Example 1: A [ B + C’ (AB + AC’)’ ]

Answer: A [ B + C’ (AB + AC’)’ ]

 = A [ B + C’ (AB)’ (AC’)’ ]
= A [ B + C’ (A’ + B’) (A’ + C) ]
= A [ B + (A’ C’ + B’ C’) (A’ + C) ]
= A [ B + (A’ C’A’ + B’ C’A’) (A’ C’ C + B’ C’ C) ]
= A [ B + (A’C’ + B’ C’A’) (0 + 0) ]
= A [ B + A’C’ ( 1 + B’) ]
= A [ B +A’C’]
= AB + A’AC’
= AB + 0
= AB

Example 2: A + B [ AC + (B + C’)D ]

Answer: A + B [ AC + (B + C’)D ]
= A + B [ AC + (BD + C’D) ]
= A + ABC + BBD + BC’D
= A + ABC + BD + BC’D
= A (1 + BC) + BD (1 + C’)
= A (1) + BD (1)
= A + BD

Example 3: (A + (BC)’)’ (AB’ + ABC)

Answer: (A + (BC)’)’ (AB’ + ABC)

= (A’ (BC)’’) (AB’ + ABC)
= (A’BC) (AB’ + ABC)
= A’BCAB’ + A’BCABC
=0+0
=0

Example 4: (B + BC) (B + B’C) (B + D)

Answer: (B + BC) (B + B’C) (B + D)

= (BB + BB’C + BBC + BCB’C) (B + D)
= (B + 0 + BC + 0) (B + D)
= B (1 + C) (B + D)
= B (B + D)
 = BB + BD
= B + BD
= B (1 + D)
=B

Example 5: AB + AB’C +BC’

Answer: AB + AB’C +BC’

= A (B + B’C) + BC’
= A (B + B’) (B + C) + BC’
= A (1) (B + C) + BC’
= AB + AC +BC’
= CA + C’B +AB
= CA+C’B (B’cz of Consensus theorem1)

Example 6: AB’C + B + BD’ + ABD’ + A’C

Answer: AB’C + B + BD’ + ABD’ + A’C

= AB’C + B (1 + D’ + AD’) + A’C
= AB’C + B + A’C
= C (A’ + AB’) + B
= C (A’ + A) (A’ + B’) + B
= C (1) (A’ + B’) + B
= C (A’ + B’) + B
= A’C + CB’ + B
= A’C + (C + B) (B’ + B)
= A’C + (B + C) (1)
= A’C + B + C
= C (1 + A’) + B
=B+C

Example 7: A’B’ + A’B

Answer: A’B’ + A’B = A’ (B’ + B) = A’

Example 8: A’B’ + AB’

Answer: A’B’ + AB’
= B’ (A’ + A)
= B’

Example 9: A’B + AB

Answer: A’B + AB
= B (A’ + A)
= B (1)
=B

Example 10: A’B’ + A’B + AB’ + AB

Answer: A’B’ + A’B + AB’ + AB

= A’ (B’ + B) + A (B’ + B)
= A’ + A
=1

Example 11: [(A + B) (A’ + B)] + [(A + B) (A + B’)]

Answer: [(A + B) (A’ + B)] + [(A + B) (A + B’)]

= [AA’ + AB + BA’ + BB] + [AA + AB’ + BA + BB”]
= [0 + AB + A’B + B] + [A + AB’ + AB + 0]
= [B (A + A’ + 1)] + [A (1 + B’ + B)]
= B +A
= A +B

Example 12: [(A + B’) (A’ + B’)] + [(A’ + B’) (A’ + B’)]

Answer: [(A + B’) (A’ + B’)] + [(A’ + B’) (A’ + B’)]

= [AA’ + AB’ + B’A’ + B’B’] + [A’A’ + A’B’ + B’A’ + B’B’]
= [0 + AB’ + A’B’ + B’] + [A’ + A’B’ + B’]
= [B’ (A + A’ + 1)] + [A’ + B’(1)]
= B’ + A’ + B’
= A’ + B’
Example 13: (A + B) (A + B’) (A’ + B) (A’ + B’)

Answer: (A + B) (A + B’) (A’ + B) (A’ + B’)

= (AA + AB’ + BA + BB’) (A’A’ + A’B’ + BA’ + BB’)
= [A (1+ B’ + B)] [A’ (1 + B’ + B)]
= AA’
=0

2.4 DIFFERENT FORMS OF BOOLEANALGEBRA:

 There are two types of booleanform
1) Standardform
2) Canonicalform

2.4.1 StandardForms
 In this configuration, the terms that form the function may contain one, two, or any number of
literals.
 There are two types of standard forms: (i) sum of product (SOP) (ii) product of sum(POS).

 Sum of Product(SOP)
SOP is a Boolean expression containing AND terms, called product terms, of one or more literals each. The sum denote
the ORing of these terms.
An example of a function expressed in sum of product is:
F = Y’ + XY + X’YZ’

 Product of Sum(POS)

The OPS is a Boolean expression containing OR terms, called sum terms. Each terms may have any no. of literals. The
product denotes ANDing of these terms.
An example of a function expressed in product of sum is:
F = X (Y’ + Z) (X’ + Y + Z’ + W)

 A Boolean expression function may be expressed in a nonstandard form. For example thefunction:
F = (AB + CD) (A’B’ + C’D’)
Above function is neither sum of product nor in product sums. It can be changed to a standard form by using
distributive law as below;
F = ABC’D’ + A’B’CD
2.4.2 CanonicalForms
 Any boolean expression can be expressed in Sum of Product (SOP) form or Product of Sum (POS)
form, they are called canonicalform.

 SOP - Sum ofProduct

 A standard SOP form is one in which a no. of product terms, each one of which contains all the
variables of the function either in complemented or non-complemented form, summedtogether.
 Each of the product term is calledMINTERM.
 For minterms,
Each non-complemented variable  1 Each
complemented variable  0
 Decimal equivalent is expressed in terms of lower case‘m’.

 For example,

1. XYZ = 111 = m7
2. A’BC = 011 = m3
3. P’Q’R’ = 000 = m0
4. T’S’ = 00 =m0
5. B’C = 01 =m1

 Example 1: F1 = X’Y’Z + XY’Z’ +XYZ

= 001 + 100 + 111
= m1 + m4 + m7
= Σm(1,4,7)

 Example 2: F2 = P’Q’ +PQ

= 00 + 11
= m0 +m3
=Σm(0,3)

 Example 3: F3 = XY’ZW + XYZ’W’ +X’Y’Z’W’

= 1011 + 1100 + 0000
= m11 + m12 + m0
= Σm(0,11,12)

 POS - Product ofSum

 AstandardPOSformisoneinwhichano.ofsumterms,eachoneofwhichcontainsallthevariables of the
function either in complemented or non-complemented form, are multipliedtogether.
 Each of the product term is calledMAXTERM.
 For maxterms,
Each non-complemented variable  0 Each
complemented variable  1
 Decimal equivalent is expressed in terms of upper case‘M’.

 For example,
1. X+Y+Z = 000 = M0
2. P’+Q’+R’ = 111 = M7
3. A’+B+C’+D = 1010 = M10

 Example 1: F1 =(P’+Q)(P+Q’)
= (10)(01) = M2·M1
= ΠM(1,2)

 Example 2: F2=(X’+Y’+Z’+W)(X’+Y+Z+W’)(X+Y’+Z+W’)
= (1110)(1001)(0101)
=M14·M9·M5
=ΠM(5,9,14)

 Example 3: F3 =(A’+B+C)(A+B’+C)(A+B+C’)
= (100) (010) (001)
= M4 M2M1
=ΠM(1,2,4)

 Minterms & Maxterms for 3variables

Table 2.4: Representation of Minterms and Maxterms for 3 variables

2.4.3 Conversion between Canonicalforms
 The complement of a function expressed as the sum of minterms equals the sum of minterms
missing from originalfunction
 Thisisbecausetheoriginalfunctionisexpressedbythosemintermsthatmakethefunctionequalto 1, while
its complement is 1 for those minterms that the function is0.

 Example 1:
F(A,B,C)= Σ(1,4,5,6,7)  F’(A,B,C) = ΠM(0,2,3)

STEP 1:
Take complement of the givenfunction;
F’(A,B,C) = Σ(0,2,3) = (m0 + m2 +m3)’

STEP 2:
Put value of MINTERM in form of variables;
F’= (A’B’C’ + A’BC’ +A’BC)’
=(A+B+C)(A+B’+C)(A+B’+C’)
=M0·M2·M3
=ΠM(0,2,3)
In general, mj’ = Mj

 Example 2:
F(A,B,C,D)= ΠM(0,3,7,10,14,15)

STEP 1:
Take complement of the given function;
F’(A,B,C,D)= ΠM(1,2,4,5,6,8,9,11,12,13) = (M1 M2 M4 M5 M6 M8 M9 M11 M12 M13)’

STEP 2:
Put value of MAXTERM in form of variables;
F’= [(A+B+C+D’)(A+B+C’+D)(A+B’+C+D)(A+B’+C+D’)(A+B’+C’+D)
(A’+B+C+D)(A’+B+C+D’)(A’+B+C’+D’)(A’+B’+C+D)(A’+B’+C+D’)]’
= (A’B’C’D) + (A’B’CD’) + (A’BC’D’) + (A’BC’D) +(A’BCD’)
(AB’C’D’) + (AB’C’D) + (AB’CD) + (ABC’D’) +(ABC’D)
= m1 + m2 + m4 + m5 + m6 + m8 + m9 + m11 + m12 + m13
= Σm(1,2,4,5,6,8,9,11,12,13)

 Convert toMinterms

 Example1:
F = A + B’C
 Answer: A  B & C is missing. So multiply with (B + B’) & (C + C’).
B’C  A is missing. So multiply with (A + A’).
A = A (B + B’) (C + C’)
= (AB + AB’) (C +C’)
= ABC + AB’C + ABC’ + AB’C’

B’C = B’C (A + A’)

= AB’C + A’B’C

So, A + B’C = ABC + AB’C + ABC’ + AB’C’ + AB’C + A’B’C

= ABC + AB’C + ABC’ + AB’C’ + A’B’C
= 111 + 101 + 110 + 100 + 001
= m7 + m6 + m5 + m4 + m1
= Σm(1,4,5,6,7)

 Convert toMaxterms

 Example1:
F = A (B + C’)

Answer: A  B & C is missing. So add BB’ & CC’.

B + C’  A is missing. So add AA’.

A = A + BB’ + CC’
= (A + B) (A +B’) + CC
= (A + B + CC’) (A + B’ + CC’)
= (A + B + C) (A + B + C’) (A + B’ + C) (A + B’ + C’)

B + C’ = B + C’ + AA’ = (A + B + C’) (A’ + B + C’)

So, A (B + C’) = (A + B + C) (A + B + C’) (A + B’ + C) (A + B’ + C’)

(A + B + C’) (A’ + B + C’)
= (A + B + C) (A + B + C’) (A + B’ + C) (A + B’ + C’)
(A’ + B + C’)
= (000) (001) (010) (011) (101)
= ΠM(0,1,2,3,5)

 Example 2:F = XY +X’Y

Answer: F = XY + X’Y
= (XY + X’) (XY + Z)
= (X +X’) (Y + X’) (X + Z) (Y + Z)
= (Y + X’) (X + Z) (Y + Z)
 X’ + Y = X’ + Y + ZZ’
= (X’ + Y + Z) (X’ + Y + Z’)
= (100) (101)

X + Z = X’ + Z + YY’
= (X + Y + Z) (X + Y’ + Z)
= (000) (010)

Y + Z = Y + Z + XX’
= (X + Y + Z) (X’ + Y + Z)
= (000) (100)

So, F = XY + X’Z
= (100) (101) (000) (010)
= M 4 M5 M0
M2 F =
ΠM(0,2,4,5)

2.5 KARNAUGH MAP (K-MAP):

 A Boolean expression may have many differentforms.

 WiththeuseofK-map,thecomplexityofreducingexpressionbecomeseasyandBooleanexpression
obtained is simplified.
 K-map also be said as pictorial form of truthtable.

 K-map is alternative way of simplifying logiccircuits.

 Instead of using Boolean algebra simplification techniques, you can transfer logic values from a
Boolean statement or a truth table into a Karnaugh map(k-map)
 Tool for representing Boolean functions of up to sixvariables.
 K-maps are tables of rows and columns with entries represent 1’s or 0’s of SOPand POS
representations.

 K-mapcellsarearrangedsuchthatadjacentcellscorrespondtotruthrowsthatdifferinonlyonebit position
(logical adjacency)
 K-Map are often used to simplify logic problems with up to 6variables
 No. of Cells = 2n, where n is a number ofvariables.

 The Karnaugh map is completed by entering a ‘1’ (or ‘0’) in each of the appropriatecells.
 Within the map, adjacent cells containing 1's (or 0’s) are grouped together in twos, fours, oreights
and so on.
2.5.1 2 variablesk-map
 For 2 variable k-map, there are 22 = 4 inputcombinations.
 If A & B are two variables then;
SOP  Minterms  A’B’ (m0, 00) ; A’B (m1, 01) ; AB’ (m2, 10) ; AB (m3, 11) POS 
Maxterms  A + B (M0, 00) ; A + B’ (M1, 01) ; A’ + B (M2, 10) ;
A’ + B’ (M3, 11)

 Mapping of SOPExpression:

B B
B’ B B’ B
A 0 1 0 1
A
A’0
A’B’ A’B A’0 m0 m1
0 1 0 1
A1
AB’ AB A1
m2 m3
2 3 2 3

 1 in a cell indicates that the minterm is included in Booleanexpression.

 For e.g. if F = ∑m(0,2,3), then 1 is put in cell no. 0,2,3 as shownbelow.
B
B’ B
A 0 1

A’0 1 0
0 1

A1 1 1
2 3

Example 1: Map for a 2-input OR

gate.
Example 2: Map for a 2-input EX-OR gate.

F = A’B’ + AB

 Map following SOPexpressions:

Example 1: F =
AB B
B’ B

A 0 1

A’0
0 0
0 1

A1 0 1
2 3

Example 2: F = AB’ + A’B

+A’B’

B
B’ B

A 0 1

A’0
1 1
0 1

A1 1 0
2 3
Example 4: F = m0 +
m1 B
B’ B

A 0 1

A’0
1 1
0 1

A1 0 0
2 3

 Map following POSexpressions:

B B
B B’ B B’

A 0 1 A 0 1

A0 A+B A+B’ A0 M0 M1
0 1 0 1

A’1 A’+B A’+B’ M2 M3

A’1
2 3 2 3

 0 in a cell indicates that the maxterm is included in Booleanexpression.

 For e.g. if F = Π M(0,2,3), then 0 is put in cell no. 0,2,3 as shownbelow.

B
B’ B

A 0 1

A’0
0 1
0 1

A1 0 0
2 3
Example 1: F =
M0·M1·M2 B
B B’

A 0 1

A 0
0 0
0 1

A’ 1 0 1
2 3

Example 2: F =
ΠM(1,3) B
B B’

A 0 1

A0
1 0
0 1

1 0
A’ 1
2 3

 Reduce following SOPexpressions:

Example 1: F = m0 +
m1 B
B’ B

A 0 1

A’ 0 1 1
0 1

A 1 0 0
2 3

F = A’
Example 2: F = A’B’ +
AB’ B
B’ B
A 0 1

A’0
1 0
0 1

A1
1 0
2 3

F = B’
Example 3: F = Σ(1,3)
B
B’ B

A 0 1

A’0 0 1
0 1

A1 0 1
2 3

F=B

Example 4:
F = m2 + m3 B
B’ B

A 0 1

A’0 0 0
0 1

A1 1 1
2 3

F=A

Example 5:
F = ∑m(0,1,2,3) B
B’ B

A 0 1

A’0 1 1
0 1

A1
1 1
2 3

F=1
Example 1: F = (A+B) (A’+B)
(A+B’) B
B B’

A 0 1

A0 0 0
0 1
A’1
0 1
2 3

F = AB

Example 2: F =
M3·M1·M2 B
B B’

A 0 1

A0
1 0
0 1

A’ 1
0 0
2 3

F = A’B’

Example 4: m2 + m3
F = m2 + m3 = Π(0,1)
B
B B’

A 0 1

A0 0 0
0 1

A’1 1 1
2 3
F=A
 3 variablesk-map
Reduce following SOPexpression:

 For 3 variables, in SOP form there are 8 combinations asfollow;

A’B’C (m0, 000)

’
A’B’C (m1, 001)
A’BC’ (m2, 010)
A’BC (m3, 011)
AB’C’ (m4, 100)
A’BC’ (m5, 101)
A’B’C (m6, 110)
ABC (m7, 111)

 For the case of 3 variables, we form a map consisting of 23=8 cells as shown inFigure

EXAMPLE 1: F = A’B’C’ + ABC + A’BC’

F = A’B’C + ABC + A’BC’

EXAMPLE 2: F = Σ(1,6,7)

F = A’B’C’ + AB

EXAMPLE 3: F = A’B’C’ + ABC’ + AB’C’ + A’BC

F = B’C’ + AC’ + A’BC

EXAMPLE 4: F = Σm(0,1,2,4,5,6)

F = B’ + C’

EXAMPLE 5: F = m3 + m4 +m6 +m7

F = BC + AC’
EXAMPLE 6: F = Σm(3,7,1,6,0,2,5,4)

F=1

Reduce following POSexpression

 For 3 variables, in POS form there are 8 combinations asfollow;

A+B+C (M0, 000)

A + B + C’ (M1, 001)
A + B’ + C (M2, 010)
A + B’ + (M3, 011)
C’
A’ + B + C (M4, 100)
A’ + B + (M5, 101)
C’
A’ + B’ + (M6, 110)
C
A’ + B’ + (M7, 111)
C’

 For the case of 3 variables, we form a map consisting of 2 3=8 cells as shown inFigure
EXAMPLE 1: F = (A’+B’+C’)(A’+B+C’)

F = (A’ + C’)

EXAMPLE 2: F = ΠM(1,2,5)

F = (B + C’) (A + B + C)

EXAMPLE 3: F = M0·M3·M7

F = (A + B + C) (B’ + C’)

EXAMPLE 4: F = (A+B+C)(A+B’+C’)(A’+B+C)

F = (B + C) (A + B’ + C’)

EXAMPLE 5: F = ΠM(5,7,0,3,2,4,6,1)
 F=0

2.5.2 4 variablesk-map
Reduce following SOPexpression:

 For 4 variables, 24 = 16 combinations areavailable;

Looping:

 Looping Groups ofTwo:

 Looping Groups ofFour:
Looping Groups ofEight:
EXAMPLE 1: ∑ (0,1,2,4,5,6,8,9,12,13,14)

F = C’ + A’D’ + BD’

EXAMPLE 2: A’B’C’ + B’CD’ + A’BCD’ + AB’C’

F = B’C’ + B’D’ + A’CD’

EXAMPLE 3: ∑ (0,1,2,3,5,7,8,9,12,13)

F = A’B’ + AC’ + A’D

EXAMPLE 4: ∑ (0,1,3,4,5,6,7,13,15)

F = A’C’ + A’D + BD + A’B

EXAMPLE 5: ∑m (5,6,7,9,10,11,13,14,15)

F = BD + BC + AD + AC

Reduce following POSexpression:

 For 4 variables, 24 = 16 combinations areavailable;

EXAMPLE 1: ΠM (0,1,2,5,7,8,9,10,14,15)

F = (B + D) (B + C) (A + B’ + D’) (A’ + B’ + C’)

EXAMPLE 2: M1 M3 M4 M7 M8 M9 M11 M12 M14 M15

F = (B’ + D) (C’ + B’) (D’ + B)

Don’t CareCombinations:

EXAMPLE 1: ∑m (1,5,6,12,13,14) + d (2,4)

F = BC’ + BD’ + A’C’D

EXAMPLE 2: ΠM (4,7,10,11,12,15) · d (6,8)

F = (B’ + C + D) (B’ + C’ + D’) (A’ + B + C’)

2.5.3 5 variablesk-map
Reduce following SOPexpression:

 For 4 variables, 25 = 32 combinations areavailable;

EXAMPLE 1: ∑m (0,2,3,10,11,12,13,16,17,18,19,20,21,26,27)

F = C’D + B’C’E’ + AB’D’ + A’BCD’

 EXAMPLE 2: ∑m (0,2,4,6,9,11,13,15,17,21,25,27,29,31)

F = BE + AD’E + A’B’E’

EXAMPLE 3: ΠM (1,4,5,6,7,8,9,14,15,22,23,24,25,28,29,30,31)

F = (B’ + C + D) (C’ +D’) (A + B + C’) (A’ + B’ + D) (A + C + D + E’)

Quine-Mccluskey Method:
It also known as Tabular method. It is more systematic method of minimizing expressions of even
larger number of variables. It is suitable for hand computation as well as computation by machines i.e.,
programmable. . The procedure is based on repeated application of the combining theorem.
PA+P =P (P is set of literals) on all adjacent pairs of terms, yields the set of all PI‘s from which a
minimal sum may be selected.
Consider expression
∑m(0,1,4,5)= + C+A +A C
First, second terms & third, fourth terms can be combined

( + )+ (C+ )= +A
Reduced to (+) =
The same result can be obtained by combining m0& m4 & m1&m5 in first step & resulting terms in
the second step.
Procedure:
 Decimal Representation
  Don‘t cares
 PI chart
 EPI
 Dominating Rows & Columns
 Determination of Minimal expressions in complescases.

Branching Method:

POST MCQ:
1. _____________ expressions can be implemented using either
(1) 2-level AND-OR logic circuits or
(2) 2-level NAND logic circuits.
a) POS
b) Literals
c) SOP
d) POS
Answer: c

2. F(A, B, C, D) = Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)

a) F(A, B, C, D) = AD + B’D + C’D’

b) F(A, B, C, D) = BD + C’D + B’D’
c) F(A, B, C, D) = A’D + B’D’ + CD’
d) None of the above
Answer: b
3. F(A, B, C, D) = Σm(0, 1, 3, 5, 7, 8, 9, 11, 13, 15)
a) F(A, B, C, D) = A’B’ + C’
b) F(A, B, C, D) = B’D’ + A
c) F(A, B, C, D) = B’C + D’
d) F(A, B, C, D) = B’C’ + D
Answer: d

4. Minimize the following function using K-Map provide output Z :

F(A, B, C) = Σm(0, 1, 6, 7) + Σd(3, 5)

a) Z = A’C + AB’
b) Z = B’C’ + AB
c) Z = AB + A’B’
d) Z = BC + AB
Answer: c
5. Convert the Z= Σm (m0,m1,m5,m7) equation to POS.
a) Z= π(M2,M3,M5,M6 )
b) Z= π(M1,M3,M4,M5 )
c) Z= π(M0,M2,M1,M5 )
d) Z= π(M2,M3,M4,M6 )
Answer: d
 UNIT– II
COMBINATIONALCIRCUITS
AIM:
To study and implement the combinationalcircuits.
PRE MCQ:
1. How many combination input in 2 bit Half adder________
a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs

2. Define Demultiplexer.
a) Many input and one output
b) one input and many output
c) one input and one output
d) Many input and many output

3. How many select lines would be needed in 16 to 1 multiplexer?

a) 2
b) 4
c) 8
d) 3

4. How many NOT gates are needed for the frame of 8 to 1 multiplexer?
a) 3
b) 4
c) 2
d) 5

5. The De multiplexer is otherwise called as

a) Input selector
b) Output selector
c) Data distributor
d) Output distributor

6. How many AND gates are required for a multiplexer 4:1?

a) 2
b) 6
c) 8
d) 4

7. A code converter means of _______

a) Inverter
b) Converts one type data into another type data
c) Converts many input into one output
d) Converts to octal
THEORY:
Binary Adder and Subtractor

The operation of adding two binary numbers is one of the fundamental tasks performed by a digital
computer. The four basic addition operations are 0 + 0 = 0, 1 + 0 = 1, 0 + 1 = 1 and 1 + 1 = 10. In the
first three operations, each binary addition gives sum as one bit, i.e., either 0 or 1.

But the fourth addition operation gives a sum that consists of two binary digits. In such result of the
addition, lower significant bit is called as the sum bit, whereas the higher significant bit is called as the
carry bit. The logic circuits which are designed to perform the addition of two binary numbers are
called as binary adder circuits. In this article we are going to look at the binary addition performed by
various adder circuits.

Half Adder

A logic circuit block used for adding two one bit numbers or simply two bits is called as a half adder
circuit. This circuit has two inputs which accept the two bits and two outputs, with one producing sum
output and other produce carry output.

As we discussed above that binary addition is commonly performed by Ex-OR gate, but for the first
three rules, it performs the binary addition and when the two inputs are logic 1, it does not develop any
carry.

To accomplish the binary addition with Ex-OR gate, there is need of additional circuitry to perform the
carry operation. Hence, a half adder is formed by connecting AND gate to the input terminals of the
Ex-OR gate so as to produce the carry as shown in below figure.
In the above
bove half adder, inputs are labeled as A and B. The sum output is labeled with the summation
symbol? and the carry output or carry out is labeled with Co. Half adder is mainly used for addition of
augend and addend of first order binary numbers.

Half adder has limited number of applications, and practically not used in the application especially
multi-digit
digit addition. In such applications carry of the previous digit addition must be added along with
two bits; hence it is three bits addition.

Full Adder

A binary
ary full adder is a multiple output combinational logic network that performs the arithmetic sum
of three input bits. As we have seen that the half adder cannot respond to the three inputs and hence the
full adder is used to add three digits at a time.

It consists of three inputs, in which two are input variables represent the two significant bits to be
added, labeled as A and B, whereas the third input terminal is the carry from the previous lower
significant position and labeled as Cin. The two outputs araree a sum and a carry outputs which are
labeled as ? and Cout respectively.

Full adder can be formed by combining two half adders and an OR gate as shown in above where
output and carry-in
in of the first adder becomes the input to the second half adder that produce the total
sum output. The total carry out is produced by ORing the two half adder carry outs as shown in figure.
The full adder block diagram and truth table is shown below.

Block Diagram of Full Adder

 Truth Table

Binary Subtraction Circuits

Subtraction is a mathematical operation in which one integer number is deducted from another to
obtain the equivalent quantity. The number from which other number is to be deducted is called as
minuend and the number subtracted from the minuend is called subtrahend. Similar to the binary
addition, binary subtraction is also has four possible alternative operations.

The above figure shows the four possible rules or elementary operations of the binary subtractions. In
all the operations, each subtrahend bit is deducted from the minuend bit.

But in the second rule, minuend bit is smaller than the subtrahend bit, hence 1 is borrowed to perform
the subtraction. Similar to the adder circuits, subtraction circuits are also classified as half subtractors,
full subtractors and parallel subtractors.

Half Subtractors

A half subtractor is a multiple output combinational logic network that does the subtraction of two bits
of binary data. It has input variables and two output variables. Two inputs are corresponding to two
input bits and two output variables corresponds to the difference bit and borrow bit.
The binary subtraction is also performed by the Ex-OR gate with additional circuitry to perform the
borrow operation. Thus, a half subtractor is designed by an Ex-OR gate including AND gate with A
input complemented before fed to the gate.

The block model, truth table and logic diagram of a half subtractor shown in above figure. This circuit
is similar to the half adder with only difference in input A i.e., minuend which is complemented before
applied at the AND gate to implement the borrow output.

In case of multi-digit subtraction, subtraction between the two digits must be performed along with
borrow of the previous digit subtraction, and hence a subtractor needs to have three inputs. Therefore,
a half subtractor has limited applications and strictly it is not used in practice.

Full Subtractor

A combinational logic circuit performs a subtraction between the two binary bits by considering
borrow of the lower significant stage is called as the full subtractor. In this, subtraction of the two
digits is performed by taking into consideration whether a 1 has already borrowed by the previous
adjacent lower minuend bit or not.

It has three input terminals in which two terminals corresponds to the two bits to be subtracted
(minuend A and subtrahend B), and a borrow bit Bi corresponds to the borrow operation. There are
two outputs, one corresponds to the difference D output and other borrow output Bo as shown in figure
along with truth table.
 Block Diagram of Full Subtractor

Truth Table

By deriving the Boolean expression for the full subtractor from above truth table, we get the
expression that tells that a full subtractor can be implemented with half subtractors with OR gate as
shown in figure below.
By comparing the adder and subtractor circuits or truth tables, one can observe that the output D in the
full subtractor is exactly same as the output S of the full adder. And the only difference is that input
variable A is complemented in the full subtractor.

Therefore, it is possible to convert the full adder circuit into full subtractor by simply complementing
the input A before it is applied to the gates to produce the final borrow bit output Bo.

Parallel Binary Adders

As we discussed that a single full adder performs the addition of two one bit numbers and an input
carry. For performing the addition of binary numbers with more than one bit, more than one full adder
is required depends on the number bits. Thus, a parallel adder is used for adding all bits of the two
numbers simultaneously.

By connecting a number of full adders in parallel, n-bit parallel adder is constructed. From the below
figure, it is to be noted that there is no carry at the least significant position, hence we can use either a
half adder or made the carry input of full adder to zero at this position.

The figure below shows a parallel 4 bit binary adder which has three full adders and one half-adder.
The two binary numbers to be added are A3A2A1A0 and B3B2B1B0 which are applied to the
corresponding inputs of full adders. This parallel adder produces their sum as C4S3S2S1S0 where C4
is the final carry.
In the 4 bit adder, first block is a half
half-adder
adder that has two inputs as A0B0 and produces their sum S0
and a carry bit C1. Next block should be full adder as there are three inputs applied to it. Hence this
full adder produces their sum S1 and a carry C2. This will be followed by other two full adders and
thus the final sum is C4S3S2S1S0.
Most commonly Full adders designed in dual in
in-line
line package integrated circuits. A typical 74LS283 is
a 4 bit full adder. Arithmetic and Logic Unit of a unit computer consist of these parallel adders to
perform the addition of binary numbers.

MULTIPLEXER:

 Multiplexer is a special type of combinationalcircuit.

 The figure below shows the n x 1 multiplexer and its equivalent circuitrepresentation.
 There are ‘n’ data inputs, 1 output and ‘m’ select lines, i.e.2 m=n.
 A multiplexer is a digital circuit which selects one of the n data inputs and routes it to the
output. The selection of one of the n inputs is done by the selectinputs
 To select ‘n’ inputs, ‘m’ select lines such that2 m=n.
 Dependingonthedigitalcodeappliedattheselect inputs,oneoutof ‘n’datasourcesiselectedand
transmitted to the single output.
 Asshowninthefigure,themultiplexeractslikeadigitallycontrolledsinglepole,multiplewayswitch.
 The output gets connected to only one of the ‘n’ data inputs at given instant oftime.
 It is also called DATASELECTOR.
 Different types of multiplexers
ltiplexers are available viz. 2 to 1, 4 to 1, 8 to 1, 16 to 1 andonwards.
 Multiplexers are needed in most of electronics systems, where the digital data is available
on more than one lines, and it becomes necessary to route this data over a singleline.
 Manyy logical functions can be implemented usingMultiplexer.

2 X 1Multiplexer

It has two data inputs I0 and I1, one select input S, and one output Y.

Block Diagram

Truth table of 2 X 1 multiplexer

Select Output
Line Y
S
 0 I0
1 I1

Boolean Equation : Y = S’I0 + SI1

Circuit Diagram

I0

Y
I1

Working:
 WhenS=0,theupperANDgatewillturnONandlowerANDgatewillturnOFF,andsotheinput
WhenS=0,theupperANDgatewillturnONandlowerANDgatewillturnOFF,andsotheinputI
0 appears in theoutput.
 When S=1, the upper AND gate will turn OFF and lower AND gate will turn ON, and so the
inputI1 appears in the output.

4 X 1Multiplexer

 It has four data inputs I3, I2, I1 and I0, two select inputs S1 & S0, and one outputY.
 Here 2n=4 inputs, i.e. n=2 select lines and m = 1output

Block Diagram
Truth Table
Select Line Outpu
S1 S0 tY
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Working

 According to the truth table, when S1 S0=00, the input I0 is selected and routed to theoutput.
 When S1 S0=01,, the input I1 is selected and routed to theoutput.
 Similarly, when S1 S0=10,, then Y=I2 & when S1 S0=11, thenY=I3.
Boolean Equation

Y = S1’S0’I0 + S1’S0I1 + S1S0’I2 + S1S0I3

I0

I1
Y
I2

I3

S1 S0
Circuit Diagram

DEMULTIPLEXER:

Fig.: Illustration of demultiplexer

 It has one input common data, ‘n’ select lines and ‘m’ outputlines.
 A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input
and distributes it over severaloutputs.
 At a time only one output line is selected by the select lines and the input is transmitted to
the selected outputline.
  Relation between ‘n’ output lines and m select lines is as follows:
n = 2m

1 X 4Demultiplexer

 1 to 4 Demultiplexer has one data input F; select line inputs a,b and four outputs A, B, C &D.
&
 The select lines control the data to be routed. It helps in selecting the output on which the
data will be routed.

Switch Representation

 Based on the switch control, the input is routed to particularoutput

Switching representation of 1 X 4 demultiplexer

Table 3.4: Truth table of 1 X 4 demultiplexer

Select Line
Output Line
b a
0 0 A
0 1 B
1 0 C
1 1 D

Boolean Equation;
A= Fb′a′; B = Fb′a; C= Fba
Fba′; D =Fba
Working

 When ab=”00”, the input data F is routed to the outputA

 When ab=”01”, the input data F is routed to the outputB
 When ab=”10”, the input data F is routed to the outputC
 When ab=”11”, the input data F is routed to the outputD
 Fig. : Working of 1 X 4 demultiplexer
Circuit Diagram:

ENCODER:

 It is a combinationalcircuit.
 It has ‘n’ input lines & ‘m’ outputlines.
 An encoder produces an ‘m’ bit binary code corresponding to the digital input number of
‘n’bits.
 Many types of Encoders – Octal to Binary (8 to 3), Decimal to BCD (10 to 4)etc.
 The block diagram is as shownbelow,

PriorityEncoder

 This is special type ofencoder.

 Priorities are given to the inputlines.
 Iftwoormoreinputlinesare‘1’atthesametime,thentheinputlinewithhighestprioritywillbe
considered.
 The block diagram is shownbelow,

 The truth table of priority encoder is as givenbelow,

 There are four inputs, D0 through D3 and outputs Y1 and Y0. Out of the four inputs D3 has
 the highest priority and D0 has the lowestpriority.
 That means if D3 = 1 then Y1Y0 = 11 irrespective of the other inputs. Similarly if D3 = 0
and D2 = 1 then Y1Y0 = 10 irrespective of otherinputs

Truth Table:
Inputs Outputs
D3 D2 D1 D0 Y1 Y
0
0 0 0 0 X X
0 0 0 1 0 0
0 0 1 X 0 1
0 1 X X 1 0
1 X X X 1 1

Y1 = D3+D2 Y0 = D3 + D2’D1

Fig. : K
K-map representation of priority encoder

 Below figures shows the circuit diagram of PriorityEncoder.

Fig. 3.16: Circuit diagram of priorityencoder

Octal to Binary (8 to 3)Encoder

Table : Truth table of octal to binary encoder

Input Output
D0 D1 D2 D3 D4 D5 D6 D7 Q2 Q1 Q0
 1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
 It has 8 input lines & 3 outputlines.
 Corresponding to the eight input octal numbers we get three bit binary
binaryoutput.
output.
 In encoders only one input will have a one value at any given time

Boolean Equation:
Q0 = D1 + D3 + D5 + D7
Q1 = D2 + D3 + D6 + D7
Q2 = D4 + D5 + D6 + D7

Circuit Diagram

DECODER

 DecoderisadevicewhichdoesthereverseoperationofEncoder.Itisa
DecoderisadevicewhichdoesthereverseoperationofEncoder.Itisacombinationalcircuitthat
combinationalcircuitthat
converts binary information from ‘n’ input lines to a maximum of ‘2 n’ unique output lines.
 Decoder is identical to a demultiplexer without any datainput.
 E.g.: 2 to 4 Decoder, 3 to 8 Decoder, BCD to Seven SegmentDecoder

2 to 4 LineDecoder
  I0 & I1 are two inputs whereas y3, y2, y1 & y0 are fouroutputs.
 The truth table shows that each output is ‘1’ for only a specific combination ofinputs.

Block Diagram

Boolen Equation
y0 = I̅1I̅0;
̅ I0 ;
y1= I1
y2 = I1I̅ 0;
y3 =I1I0

Truth Table
Inputs Output
I1 I0 y0 y1 y2 y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
Working

 According to the truth table, when I1I0=00, the output Y0 is set to ‘1’, others are‘0’
 When I1I0=01,, the output Y1 is set to ‘1’, others are‘0’
 Similarly, for other input combinations, particular output is set to ‘1’ & others are‘0

Circuit Diagram:

Y3

Y2

Y1

Y0

I1
I0
3 to 8Decoder

Block Diagram

Fig. : Block diagram of 3 to 8 decoder

Truth Table:
Inputs Output
I2 I1 I0 Y0 Y Y2 Y3 Y Y Y6 Y7
1 4 5
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Working

 According to the truth table, when I2I1I0=000, the output Y0 is set to ‘1’, others are‘0’
 When I2I1I0=001,, the output Y1 is set to ‘1’, others are‘0’
 Similarly, for other input combinations, particular output is set to ‘1’ & others are‘0’

Boolean Equation:

Y0= I̅2 I̅1 I̅0 ; Y1= I̅2 I̅1 I0 ;

Y2= I̅2 I1 I0̅ ; Y3= I̅2 I1 I0

Y4= I2 I̅1 I̅0 ; Y5= I2 I̅1 I0 ;

Y6= I2 I1 I̅0 ; Y7= I2 I1 I0

Circuit Diagram:

POST MCQ:
1. If A = 0 and B =1 are the inputs of a half adder, the Carry and sum is given by __________
a) 0 and 0
b) 0 and 1
c) 1 and 0
d) 1 and 1
2. f A = 0 , B = 1 and C =1 are the inputs of a Full substractor, the Borrow and Difference is
given by __________
a) 0 and 0
b) 0 and 1
c) 1 and 0
d) 1 and 1
3. 10110 Use the weighting factors to convert the following binbinary
ary to gray ___________
a) 10010
b) 10101
c) 10001
d) 11101

4. Find the 9’s complement for the decimal number is 7892.

a) 2107
b) 2108
c) 2017
d) 2170
5. How many OR, AND & EXOR gates are needed in the full adder?
 a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1

UNIT III
SEQUENTIALCIRCUITS
AIM
To study the design of various synchronous and asynchronouscircuits.
PRE MCQ:

1. Which sequential circuits generate the feedback path due to the cross-coupled connection from
output of one gate to the input of another gate?
a. Synchronous
b. Asynchronous
c. Both
d. None of the above
2. The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
3. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
4. The logic circuits whose outputs at any instant of time depends only on the present input but
also on the past outputs are called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
5. How many types of sequential circuits are?
a) 2
b) 3
c) 4
d) 5
6. In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
d) Current state
7. What is a trigger pulse?
a) A pulse that starts a cycle of operation
 b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) A pulse that enhances a cycle of operation
8. How many types of flip-flops are?
a) 2
b) 3
c) 4
d) 5
9. A register is able to hold __________
a) Data
b) Word
c) Nibble
d) Both data and word
10. One example of the use of an S-R flip-flop is as ____________
a) Racer
b) Stable oscillator
c) Binary storage register
d) Transition pulse generator
11. When is a flip-flop said to be transparent?
a) When the Q output is opposite the input
b) When the Q output follows the input
c) When you can see through the IC packaging
d) When the Q output is complementary of the input
12. In a J-K flip-flop, if J=K the resulting flip-flop is referred to as _____________
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop
13. A counter circuit is usually constructed of ____________
a) A number of latches connected in cascade form
b) A number of NAND gates connected in cascade form
c) A number of flip-flops connected in cascade
d) A number of NOR gates connected in cascade form
14. Three decade counter would have ____________
a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters
15. BCD counter is also known as ____________
a) Parallel counter
b) Decade counter
c) Synchronous counter
d) VLSI counter
THEORY
The Basic Latch
 Basic latchis a feedback connection of two NOR gates or two NANDgates
 It can store one bit ofinformation

It can be set to 1 using the S input and reset to 0 using the R input
The Gated Latch
 Gated latch is a basic latch that includes input gating and a controlsignal
 The latch retains its existing state when the control input is equalto0
 Its state may be changed when the control signal is equal to 1. In our
discussion we referredto the control input as theclock
 We consider two types of gatedlatches:
 Gated SR latch uses the S and R inputs to set the latch to
1 or reset it to 0, respectively.
 Gated D latch uses the D input to force the latch into a state that
has thesamelogic value as the Dinput.
Gated S/R Latch
Gated D Latch

Setup and Hold Times

 Setup Timetsu

The minimum time that the input signal must be stable prior to the edge of the clock signal.

 Hold Timeth

The minimum time that the input signal must be stable after the edge of the clock signal.

Flip-Flops

 A flip-flop is a storage element based on the gated latchprinciple

 It can have its output state changed only on the edge of the controllingclocksignal

 We consider twotypes:
  Edge-triggered flip-flop is affected only by the input values present when
theactive edge of the clockoccurs

 Master-slave flip-flop is built with twogatedlatches

 Themasterstageis activeduringhalfoftheclockcycle,andtheslavestageisactive
during the otherhalf.

 The output value of the flip-flop changes on the edge of the clock that
activates the transfer into the slavestage.

Master-Slave D Flip-Flop

A Positive-Edge-Triggered D Flip-Flop
Master-Slave D Flip-Flop with Clear and Preset

T Flip-Flop
Excitation Tables
Conversions of flip-flops
Sequential Circuit Design
• Steps in the design process for sequentialcircuits
• State Diagrams andStateTables Examples

• Steps in Design of a SequentialCircuit

o 1. Specification – A description of the sequential circuit. Should include a
detailing of the inputs, the outputs, and the operation. Possibly assumes that you
have knowledge of digital systembasics.
o 2. Formulation: Generate a state diagram and/or a state table from the
statement of the prob
problem.
o 3. State Assignment: From a state table assign binary codes tothestates.
o 4. Flip-flop
flop Input Equation Generation: Select the type of flip
flip-flop
flop for the circuit
andgenerate the needed input for the required statetransitions
o 5. Output Equation Generation: Derive output logic equations for
generation ofthe output from the inputs and currentstate.
o 6. Optimization: Optimize the input and output equations. Today, CAD
systemsare typically used for this in realsystems.
o 7. Technology Mapping: Generate a logic diagram of the circuit using
ANDs,ORs, Inverters, andF/Fs.
o 8. Verification: Use a HDL to verify thedesign

Registers and Counters

• An n-bit
bit register is a cascade of n flip-flops and can store an n-bitbinarydata
binarydata

• A counter can count occurrences of events and can generate timing intervals forcontrolpurposes
A Simple Shift Register
Parallel-Access Shift Register

Counters
• Counters are a specific type of sequentialcircuit.

• Like registers, the state, or the flip-flop values themselves, serves as the“output.”

• The output value increases by one on eachclockcycle.

• After the largest value, the output “wraps around” back to0.

• Using two bits, we’d get something likethis:

 Present State Next State

A B A B

0 0 0 1
0 1 1 0

1 0 1 1

1 1 0 0

Benefits of counters

• Counters can act as simple clocks to keep track of

“time.”• You may need to record how many times

something has happened.

– How many bits have been sent orreceived?

– How many steps have been performed insomecomputation?

• All processors contain a program counter, orPC.

– Programs consist of a list of instructions that are to be executed one after another
(forthe mostpart).

– The PC keeps track of the instruction currentlybeingexecuted.

– ThePCincrementsonceoneachclockcycle,andthenextprograminstructionisthen
executed.
 A Three-Bit Up-Counter

Q1 is connected to clk, Q2 and Q3 are clocked by Q’ of the preceding stage

(hence called asynchronous or ripple counter

A Three-Bit Down-Counter
Shift registers:
In digital circuits, a shift register is a cascade of flip-flops sharing the same clock, in
which the output of each flip-flop is connected to the "data" input of the next flip-flop in the
chain, resulting in a circuit that shifts by one position the "bit array" stored in it, shifting in the
data present at its input and shifting out the last bit in the array, at each transition of the clock
input. More generally, a shift register may be multidimensional, such that its "data in" and stage
outputs are themselves bit arrays: this is implemented simply by running several shift registers of
the same bit-length inparallel.
Shift registers can have both parallel and serial inputs and outputs. These are often configured
as serial-in, parallel-out (SIPO) or as parallel-in, serial-out (PISO). There are also types that
have both serial and parallel input and types with serial and parallel output. There are also bi-
directional shift registers which allow shifting in both directions: L→R or R→L. The serial
input and last output of a shift register can also be connected to create a circular shiftregister
Shift registers are a type of logic circuits closely related to counters. They are basically forthe
storage and transfer of digitaldata.
Buffer register:
The buffer register is the simple set of registers. It is simply stores the binary word. The buffer
may be controlled buffer. Most of the buffer registers used D Flip-flops.

Figure: logic diagram of 4-bit buffer register

The figure shows a 4-bit buffer register. The binary word to be stored is applied to the data
terminals. On the application of clock pulse, the output word becomes the same as the word
applied at the terminals. i.e., the input word is loaded into the register by the application of clock
pulse.
When the positive clock edge arrives, the stored word becomes:
Q4Q3Q2Q1=X4X3X2X1
Q=X
Controlled buffer register:
If goes LOW, all the FFs are RESET and the output becomes, Q=0000.
When is HIGH, the register is ready for action. LOAD is the control input. When
LOAD is HIGH, the data bits X can reach the D inputs of FF‘s.
Q4Q3Q2Q1=X4X3X2
X1 Q=X
When load is low, the X bits cannot reach the FF‘s.
Data transmission in shift registers:

A number of ff‘s connected together such that data may be shifted into and shifted out of them is
called shift register. data may be shifted into or out of the register in serial form or in parallel
form. There are four basic types of shift registers.
1. Serial in, serial out, shift right, shiftregisters
2. Serial in, serial out, shift left, shiftregisters
3. Parallel in, serial out shiftregisters
4. Parallel in, parallel out shiftregisters
Serial IN, serial OUT, shift right, shift left register:

The logic diagram of 4-bitbit serial in serial out, right shift register with four stages. The register
can store four bits of data. Serial data is applied at the input D of the first FF. the Q output of the
first FF is connected to the D inp
input
ut of another FF. the data is outputted from the Q terminal of
the lastFF.

When serial data is transferred into a register, each new bit is clocked into the first FF at the
positive going edge of each clock pulse. The bit that was previously stored by the th first FF is
transferred to the second FF. the bit that was stored by the Second FF is transferred to the third
FF.

Serial-in, parallel-out,
out, shift register:

In this type of register, the data bits are entered into the register serially, but the data stored in
the register is shifted out in parallelform.

Once the data bits are stored, each bit appears on its respective output line and all bits are
available simultaneously, rather than on a bitbit-by-bit
bit basis with the serial output. The serial-in,
serial
parallel
el out, shift register can be used as serial
serial-in,
in, serial out, shift register if the output is taken
from the Q terminal of the last FF.
Parallel-in, serial-out, shift register:

For a parallel-in, serial out, shift register, the data bits are entered simultaneously into their
respective stages on parallel lines, rather than on a bit-by-bit basis on one line as with serial data
bits are transferred out of the register serially. On a bit-by-bit basis over a single line.
There are four data lines A,B,C,D through which the data is entered into the register in
parallel form. The signal shift/ load allows the data to be entered in parallel form into the register
and the data is shifted out serially fromterminalQ4

Parallel-in, parallel-out, shift register

In a parallel-in, parallel-out shift register, the data is entered into the register in parallel form,
and also the data is taken out of the register in parallel form. Data is applied to the D input
terminals of the FF‘s. When a clock pulse is applied, at the positive going edge of the pulse, the
D inputs are shifted into the Q outputs of the FFs. The register now stores the data. The stored
data is available instantaneously for shifting out in parallelform.
Bidirectional shift register:

A bidirectional shift register is one which the data bits can be shifted from left to right
or from right to left. A fig shows the logic diagram of a 4-bit serial-in, serial out, bidirectional
shift register. Right/left is the mode signal, when right /left is a 1, the logic circuit works as a
shift-register.the bidirectional operation is achieved by using the mode signal and two NAND
gates and one OR gate for eachstage.

A HIGH on the right/left control input enables the AND gates G1, G2, G3 and G4 and
disables the AND gates G5,G6,G7 and G8, and the state of Q output of each FF is passed
through the gate to the D input of the following FF. when a clock pulse occurs, the data bits are
then effectively shifted one place to the right. A LOW on the right/left control inputs enables the
AND gates G5, G6, G7 and G8 and disables the And gates G1, G2, G3 and G4 and the Q output
of each FF is passed to the D input of the preceding FF. when a clock pulse occurs, the data bits
are then effectively shifted one place to the left. Hence, the circuit works as a bidirectional shift
register

Figure: logic diagram of a 4-bit bidirectional shift

register Universal shift register:

A register is capable of shifting in one direction only is a unidirectional shift register. One that
can shift both directions is a bidirectional shift register. If the register has both shifts and parallel
load capabilities, it is referred to as a universal shift registers. Universal shift register is a
bidirectional register, whose input can be either in serial form or in parallel form and whose
output also can be in serial form or I parallel form.
The most general shift register has the following capabilities.

1. A clear control to clear the register to0

2. A clock input to synchronize theoperations
3. A shift-right control to enable the shift-right operation and serial input and output lines
associated with theshift-right
 4. A shift-left control to enable the shift-left operation and serial input and output lines
associated with theshift-left
5. A parallel loads control to enable a parallel transfer and the n input lines associatedwith
the paralleltransfer
6. N parallel outputlines
7. A control state that leaves the information in the register unchanged in the presenceof
theclock.

A universal shift register can be realized using multiplexers. The below fig shows the logic
diagram of a 4-bit universal shift register that has all capabilities. It consists of 4 D flip-flops and
four multiplexers. The four multiplexers have two common selection inputs s1 and s0. Input 0 in
each multiplexer is selected when S1S0=00, input 1 is selected when S1S0=01 and input 2 is
selected when S1S0=10 and input 4 is selected when S1S0=11. The selection inputs control the
mode of operation of the register according to the functions entries. When S1S0=0, the present
value of the register is applied to the D inputs of flip-flops. The condition forms a path from the
output of each flip-flop into the input of the same flip-flop. The next clock edge transfers into
each flip-flop the binary value it held previously, and no change of state occurs. When S1S0=01,
terminal 1 of the multiplexer inputs have a path to the D inputs of the flip-flop. This causes a
shift-right operation, with serial input transferred into flip-flopA4. When S1S0=10, a shift left
operation results with the other serial input going into flip-flop A1. Finally when S1S0=11, the
binary information on the parallel input lines is transferred into the register simultaneously
during the next clockcycle

Figure: logic diagram 4-bit universal shift register

 Function table for theregister

mode control
S0 S1 register operation

0 0 No change
0 1 Shift Right
1 0 Shift left
1 1 Parallel load

Counters:

Counter is a device which stores (and sometimes displays) the number of times
particular event or process has occurred, often in relationship to a clock signal. A Digital counter
is a set of flip flops whose state change in response to pulses applied at the input to the counter.
Counters may be asynchronous counters or synchronous counters. Asynchronous counters are
also called ripple counters
In electronics counters can be implemented quite easily using register
register-type
type circuits such as
the flip-flops and a wide variety of classifications exist:

 Asynchronous (ripple) counter – changing state bits are used as clocks to subsequentstate
flip-flops
 Synchronous counter – all state bits change under control of asingleclock
 Decade counter – counts through ten states perstage
 Up/down counter – counts both up and down, under command of a controlinput
 Ring counter – formed by a shift register with feedback connection in aring
 Johnson counter – a twisted ring counter
Cascadedcounter
Modulus counter.

Each is useful for different applications. Usually, counter circuits are digital in nature, and count
in natural binary Many types of counter circuits are available as digital building blocks, for
example a number of chips in the 4000 series implement different counters.
Occasionally there are advantages to using a counting sequence other than the natural binary
sequence such as the binary coded decimal counter, a linear feed
feed-back
back shift register counter, or
a gray-codecounter.
Counters are useful for digital clocks and timers, and iin
n oven timers, VCR clocks, etc.

Synchronous counters:
 Asynchronous counters are serial counters. They are slow because each FF can change state
only if all the preceding FFs have changed their state. if the clock frequency is very high, the
asynchronous counter may skip some of the states. This problem is overcome in synchronous
counters or parallel counters. Synchronous counters are counters in which all the flip flops are
triggered simultaneously by the clock pulses Synchronous counters have a common clock pulse

applied simultaneously toall flip- -Bit Synchronous BinaryCounter

Design of synchronous counters:

For a systematic design of synchronous counters. The following procedure is used.

Step 1:State Diagram: draw the state diagram showing all the possible states state diagram which
also be called nth transition diagrams, is a graphical means of depicting the sequence of states
through which the counter progresses.

Step2: number of flip-flops: based on the description of the problem, determine the required
number n of the flip-flops- the smallest value of n is such that the number of states N≤2 n--- and
the desired counting sequence.

Step3: choice of flip-flops excitation table: select the type of flip-flop to be used and write the
excitation table. An excitation table is a table that lists the present state (ps) , the next state(ns)
and required excitations.
 Step4: minimal expressions for excitations: obtain the minimal expressions for the excitations of
the FF using K-maps drawn for the excitation of the flip-flops in terms of the present states and
inputs.

Step5: logic diagram: draw a logic diagram based on the minimal expressions

Design of a synchronous 3-bit up-down counter using JK flip-flops:

Step1: determine the number of flip-flops required. A 3-bit counter requires three FFs. It has 8
states (000,001,010,011,101,110,111) and all the states are valid. Hence no don‘t cares. For
selecting up and down modes, a control or mode signal M is required. When the mode signal
M=1 and counts down when M=0. The clock signal is applied to all the FFs simultaneously.

Step2: draw the state diagrams: the state diagram of the 3-bit up-down counter is drawn as

Step3: select the type of flip flop and draw the excitation table: JK flip-flops are selected and the
excitation table of a 3-bit up-down counter using JK flip-flops is drawn as shown in fig.

PS mode NS required excitations

Q3 Q2 Q1 M Q3 Q2 Q1 J3 K3 J2 K2 J1 K1
0 0 0 0 1 1 1 1 x 1 x 1 x
0 0 0 1 0 0 1 0 x 0 x 1 x
0 0 1 0 0 0 0 0 x 0 x x 1
0 0 1 1 0 1 0 0 x 1 x x 1
0 1 0 0 0 0 1 0 x x 1 1 x
0 1 0 1 0 1 1 0 x x 0 1 x
0 1 1 0 0 1 0 0 x x 0 x 1
0 1 1 1 1 0 0 1 x x 1 x 1
1 0 0 0 0 1 1 x 1 1 x 1 x
1 0 0 1 1 0 1 x 0 0 x 1 x
1 0 1 0 1 0 0 x 0 0 x x 1
1 0 1 1 1 1 0 x 0 1 x x 1
1 1 0 0 1 0 1 x 0 x 1 1 x
1 1 0 1 1 1 1 x 0 x 0 1 x
1 1 1 0 1 1 0 x 0 x 0 x 1
1 1 1 1 0 0 0 x 1 x 1 x 1

Step4: obtain the minimal expressions: From the excitation table we can conclude that J1=1 and
K1=1, because all the entries for J1and K1 are either X or 1. The K-maps for J3, K3,J2 and K2
based on the excitation table and the minimal expression obtained from them are shown in fig.
 00 01 11 10
Q3Q2 Q1M
1
1
X X X X

X X X X

Step5: draw the logic diagram: a logic diagram using those minimal expressions can be drawn as
shown in fig.

Design of a synchronous modulo-6 gray cod counter:

Step 1: the number of flip-flops: we know that the counting sequence for a modulo-6 gray code
counter is 000, 001, 011, 010, 110, and 111. It requires n=3FFs (N≤2 n, i.e., 6≤23). 3 FFs can
have 8 states. So the remaining two states 101 and 100 are invalid. The entries for excitation
corresponding to invalid states are don‘t cares.
Step2: the state diagram: the state diagram of the mod-6 gray code converter is drawn as shown
in fig.
Step3: type of flip-flop and the excitation table: T flip-flops are selected and the excitation table
of the mod-6 gray code counter using T-flip-flops is written as shown in fig.

required
PS NS excitations
Q3 Q2 Q1 Q3 Q2 Q1 T3 T2 T1
0 0 0 0 0 1 0 0 1
0 0 1 0 1 1 0 1 0
0 1 1 0 1 0 0 0 1
0 1 0 1 1 0 1 0 0
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1

Step4: The minimal expressions: the K-maps for excitations of FFs T3,T2,and T1 in terms of
outputs of FFs Q3,Q2, and Q1, their minimization and the minimal expressions for excitations
obtained from them are shown if fig

Step5: the logic diagram: the logic diagram based on those minimal expressions is drawn as
shown in fig.
Design of a synchronous BCD Up-Down counter using FFs:

Step1: the number of flip-flops: a BCD counter is a mod-10 counter has 10 states (0000 through
1001) and so it requires n=4FFs(N≤2n,, i.e., 10≤24). 4 FFS can have 16 states. So out of 16
states, six states (1010 through 1111) are invalid. For selecting up and down mode, a control or
mode signal M is required. , it counts up when M=1 and counts down when M=0. The clock
signal is applied to all FFs.

Step2: the state diagram: The state diagram of the mod-10 up-down counter is drawn as shown
in fig.

Step3: types of flip-flops and excitation table: T flip-flops are selected and the excitation table of
the modulo-10 up down counter using T flip-flops is drawn as shown in fig.

The remaining minterms are don‘t cares(∑d(20,21,22,23,24,25,26,37,28,29,30,31)) from

the excitation table we can see that T1=1 and the expression for T4,T3,T2 are asfollows.
T4=∑m(0,15,16,19)+d(20,21,22,23,24,25,26,27,28,29,30,31)
T3=∑m(7,15,16,8)+d(20,21,22,23,24,25,26,27,28,29,30,31)
T2=∑m(3,4,7,8,11,12,15,16)+d(20,21,22,23,24,25,26,27,28,29,30,31)

PS NS

mode required excitations

Q4 Q3 Q2 Q1 M Q4 Q3 Q2 Q1 T4 T3 T2 T1
0 0 0 0 0 1 0 0 1 1 0 0 1
0 0 0 0 1 0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 0 0 0 0 0 1
0 0 0 1 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 0 0 1 0 0 1 1
0 0 1 0 1 0 0 1 1 0 0 0 1
0 0 1 1 0 0 0 1 0 0 0 0 1
0 0 1 1 1 0 1 0 0 0 1 1 1
0 1 0 0 0 0 0 1 1 0 1 1 1
0 1 0 0 1 0 1 0 1 0 0 0 1
0 1 0 1 0 0 1 0 0 0 0 0 1
0 1 0 1 1 0 1 1 0 0 0 1 1
0 1 1 0 0 0 1 0 1 0 0 1 1
0 1 1 0 1 0 1 1 1 0 0 0 1
0 1 1 1 0 0 1 1 0 0 0 0 1
0 1 1 1 1 1 0 0 0 1 1 1 1
1 0 0 0 0 0 1 1 1 1 1 1 1
1 0 0 0 1 1 0 0 1 0 0 0 1
1 0 0 1 0 1 0 0 0 0 0 0 1
1 0 0 1 1 0 0 0 0 1 0 0 1
 Step4: The minimal expression: since there are 4 state variables and a mode signal, we require 5
variable kmaps. 20 conditions of Q4Q3Q2Q1M are valid and the remaining 12 combinations are
invalid. So the entries for excitations corresponding to those invalid combinations are don‘t
cares. Minimizing K-maps for T2 weget
T 2= Q4Q1‘M+Q4‘Q1M+Q2Q1‘M‘+Q3Q1‘M‘

Step5: the logic diagram: the logic diagram based on the above equation is shown in fig.

Shift register counters:

One of the applications of shift register is that they can be arranged to form several types of
counters. The most widely used shift register counter is ring counter as well as the twisted ring
counter.

Ring counter: this is the simplest shift register counter. The basic ring counter using D flip-
flops is shown in fig. the realization of this counter using JK FFs. The Q output of each stage is
connected to the D flip-flop connected back to the ringcounter.

FIGURE: logic diagram of 4-bit ring counter using D flip-flops

Only a single 1 is in the register and is made to circulate around the register as long as clock
pulses are applied. Initially the first FF is present to a 1. So, the initial state is 1000, i.e., Q1=1,
Q2=0,Q3=0,Q4=0. After each clock pulse, the contents of the register are shifted to the right by
one bit and Q4 is shifted back to Q1. The sequence repeats after four clock pulses. The number
 of distinct states in the ring counter, i.e., the mod of the ring counter is equal to number of FFs
used in the counter. An n-bit ring counter can count only n bits, where as n-bit ripple counter can
count 2n bits. So, the ring counter is uneconomical compared to a ripple counter but has
advantage of requiring no decoder, since we can read the count by simply noting which FF is set.
Since it is entirely a synchronous operation and requires no gates external FFs, it has the further
advantage of being veryfast.

Timing diagram:

Twisted Ring counter (Johnson counter):

This counter is obtained from a serial-in, serial-out shift register by providing feedback
from the inverted output of the last FF to the D input of the first FF. the Q output of each is
connected to the D input of the next stage, but the Q‘ output of the last stage is connected to the
D input of the first stage, therefore, the name twisted ring counter. This feedback arrangement
produces a unique sequence ofstates.

The logic diagram of a 4-bit Johnson counter using D FF is shown in fig. the realization
of the same using J-K FFs is shown in fig.. The state diagram and the sequence table are shown
in figure. The timing diagram of a Johnson counter is showninfigure.

Let initially all the FFs be reset, i.e., the state of the counter be 0000. After each clock
pulse, the level of Q1 is shifted to Q2, the level of Q2to Q3, Q3 to Q4 and the level of Q4‘to Q1
and the sequences given in fig.
 Figure: Johnson counter with JK flip-flops

Figure: timing diagram

POST MCQ:

1. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to
which configuration feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling
2. When both inputs of a J-K flip-flop cycle, the output will ___________
a) Be invalid
b) Change
c) No change
d) Toggle
3. Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
4. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift
register with an initial state 01110. After three clock pulses, the register contains ________
a) 01110
b) 00001
c) 00101
d) 00110
5. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
6. What is the hold condition of a flip-flop?
a) Both S and R inputs activated
b) No active S or R input
c) Only S is active
d) Only R is active
7. The parallel outputs of a counter circuit represent the _____________
a) Parallel data word
b) Clock frequency
c) Counter modulus
d) Clock count
8. What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of
‘n’ number of flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2n+1/2
9. The main difference between a register and a counter is ___________
a) A register has no specific sequence of states
b) A counter has no specific sequence of states
c) A register has capability to store one bit of information but counter has n-bit
d) A register counts data
 UNIT IV
ASYNCHRONOUS SEQUENTIAL LOGIC
AIM:

PRE MCQ:
1. Asynchronous circuits are useful in application where the input signals may
a. Change at any time
b. Never change
c. Both A and B
d. Continuously change. Answer : c

2. The SR latch consists of

a. 1 input
b.2 inputs
c.3 inputs
d.4 inputs Answer : b

3. The table that is not a part of the asynchronous analysis procedure is

a.Transition table
b.State table
c.Flow table
d.Excitation table Answer : d

4. What is the Significant capacity s of memory elements utilized in the sequential circuits ?
a.Storage of binary information
b.Specify the state of sequential
c.Both a & b
d.State machine Answer : d

5.The output of the SR latch is

a. X and y
b. A and b
c. S and r
d. Q and q bar Answer : d
6. In the asynchronous circuit, the changes occur with the change of
a. Input
b. Output
c. Clock pulse
d. Time Answer : a

7. The race in which stable state depends on an order is called

a. Critical race
b. Identical race
c. Non critical race
d. Defined race Answer : a
 8. Unclocked flip-flops are known as
a. Latches
b. Register
c. Transition tables
d. Clocked flip-flop Answer : a

9. In primitive flow table for the gated latch, each state has
a. 1 row
b. 2 rows
c. 3 rows
d. 4 rows Answer : a

10. In all the cases the final stable state is

a. Changed
b. Same
c. Inverted
d. Undefined Answer : b

THEORY:
An asynchronous (ripple) counter is a single JK-type flip-flop, with its J (data) input fed
from its own inverted output. This circuit can store one bit, and hence can count from zero to one
before it overflows (starts over from 0). This counter will increment once for every clock cycle
and takes two clock cycles to overflow, so every cycle it will alternate between a transition from
0 to 1 and a transition from 1 to 0. Notice that this creates a new clock with a 50% duty cycle at
exactly half the frequency of the input clock. If this output is then used as the clock signal for a
similarly arranged D flip-flop (remembering to invert the output to the input), one will get
another 1 bit counter that counts half as fast. Putting them together yields a two-bitcounter:

Two-bit ripple up-counter using negative edge triggered flip flop:

Two bit ripple counter used two flip-flops. There are four possible states from 2 – bit up-
counting I.e. 00, 01, 10 and11.

· The counter is initially assumed to be at a state 00 where the outputs of the tow flip-flops
are noted as Q1Q0. Where Q1 forms the MSB and Q0 forms theLSB.

· For the negative edge of the first clock pulse, output of the first flip-flop FF1 toggles its
state. Thus Q1 remains at 0 and Q0 toggles to 1 and the counter state are now read as01.

· During the next negative edge of the input clock pulse FF1 toggles and Q0 = 0. The output
Q0 being a clock signal for the second flip-flop FF2 and the present transition acts as a negative
edge for FF2 thus toggles its state Q1 = 1. The counter state is now read as10.

· For the next negative edge of the input clock to FF1 output Q0 toggles to 1. But this
transition from 0 to 1 being a positive edge for FF2 output Q1 remains at 1. The counter state is
now read as11.
· For the next negative edge of the input clock, Q0 toggles to 0. This transition from 1 to 0
acts as a negative edge clock for FF2 and its output Q1 toggles to 0. Thus the starting state 00 is
attained. Figure shownbelow

Two-bit ripple down-counter using negative edge triggered flip flop:

A 2-bit down-counter counts in the order 0,3,2,1,0,1…….,i.e, 00,11,10,01,00,11 …..,etc. the
above fig. shows ripple down counter, using negative edge triggered J-K FFs and its timing
diagram.
 For down counting, Q1‘ of FF1 is connected to the clock of Ff2. Let initially all theFF1
toggles, so, Q1 goes from a 0 to a 1 and Q1‘ goes from a 1 to a0.
 The negative-going signal at Q1‘ is applied to the clock input of FF2, toggles Ff2 and,
therefore, Q2 goes from a 0 to a 1.so, after one clock pulse Q2=1 and Q1=1, I.e., the state
of the counter is11.
 At the negative-going edge of the second clock pulse, Q1 changes from a 1 to a 0 and
Q1‘ from a 0 to a1.
 This positive-going signal at Q1‘ does not affect FF2 and, therefore, Q2 remains at a 1.
Hence , the state of the counter after second clock pulse is10
 At the negative going edge of the third clock pulse, FF1 toggles. So Q1, goes from a 0 to
a 1 and Q1‘ from 1 to 0. This negative going signal at Q1‘ toggles FF2 and, so, Q2
changes from 1 to 0, hence, the state of the counter after the third clock pulse is01.
 At the negative going edge of the fourth clock pulse, FF1 toggles. So Q1, goes from a 1
to a 0 and Q1‘ from 0 to 1. . This positive going signal at Q1‘ does not affect FF2 and, so,
Q2 remains at 0, hence, the state of the counter after the fourth clock pulse is00.

Two-bit ripple up-down counter using negative edge triggered flip flop:

Figure: asynchronous 2-bit ripple up-down counter using negative edge triggered flip flop:
  As the name indicates an up-down counter is a counter which can count both in upward
and downward directions. An up-down counter is also called a forward/backward counter
or a bidirectional counter. So, a control signal or a mode signal M is required to choose
the direction of count. When M=1 for up counting, Q1 is transmitted to clock of FF2 and
when M=0 for down counting, Q1‘ is transmitted to clock of FF2. This is achieved by
using two AND gates and one OR gates. The external clock signal is applied toFF1.
 Clock signal to FF2= (Q1.Up)+(Q1‘. Down)=Q1m+Q1‘M‘

Design of Asynchronous counters:

To design a asynchronous counter, first we write the sequence , then tabulate the values of
reset signal R for various states of the counter and obtain the minimal expression for R and R‘
using K-Map or any other method. Provide a feedback such that R and R‘ resets all the FF‘s after
the desired count.
Design of a Mod-6 asynchronous counter using T FFs:
A mod-6 counter has six stable states 000, 001, 010, 011, 100, and 101. When the sixth
clock pulse is applied, the counter temporarily goes to 110 state, but immediately resets to 000
because ofthe feedback provided. it is―divide by-6-counter‖, in the sense that it dividesthe input
clock frequency by 6.it requires three FFs, because the smallest value of n satisfying the
conditionN≤2n is n=3; three FFs can have 8 possible states, out of which only six are utilized and
the remaining two states 110and 111, are invalid. If initially the counter is in 000 state, then after
the sixth clock pulse, it goes to 001, after the second clock pulse, it goes to 010, and soon.

After sixth clock pulse it goes to 000. For the design, write the truth table with present state
outputs Q3, Q2 and Q1 as the variables, and reset R as the output and obtain an expression for R
in terms of Q3, Q2, and Q1that decides the feedback into be provided. From the truth table,
R=Q3Q2. For active-low Reset, R‘ is used. The reset pulse is of very short duration, of the order
of nanoseconds and it is equal to the propagation delay time of the NAND gate used. The
expression for R can also be determined as follows.

R=0 for 000 to 101, R=1 for 110, and R=X=for111

Therefore,
R=Q3Q2Q1‘+Q3Q2Q1=Q3Q2

The logic diagram and timing diagram of Mod-6 counter is shown in the above fig.

The truth table is as shown in below.

After States
pulses Q3 Q2 Q1 R

0 0 0 0 0
1 0 0 1 0
2 0 1 0 0
3 0 1 1 0
4 1 0 0 0
5 1 0 1 0
6 1 1 0 1

0 0 0 0
7 0 0 0 0
Design of a mod-1010 asynchronous counter using T T-flip-flops:
A mod-1010 counter is a decade counter. It also called a BCD counter or a divide-by-10
divide
counter. It requires four flip-flops n
flops (condition 10 ≤2 is n=4). So, there are 16 possible states, out
of which ten are valid and remaining six are invalid. The counter has ten stable state, 0000
through 1001, i.e., it counts from 0 to 9. The initial state is 0000 and after nine clock pulses it
goes to 1001. When the tenth clock pulse is applied, the counter goes to state 1010 temporarily,
but because of the feedback provide
provided,
d, it resets to initial state 0000. So, there will be a glitch in
the waveform of Q2. The state 1010 is a temporary state for which the reset signal R=1, R=0 for
0000 to 1001, and R=C for 1011 to1111.

The count table and the K-Map

Map for reset are shown in fig. from the K K-Map
Map R=Q4Q2. So,
feedback is provided from second and fourth FFs. For active –HIGH HIGH reset, Q4Q2 is applied to
the clear terminal. For active-LOW
LOW reset 4 2 is connected isof allFlip=flops.

After Count
pulses Q4 Q3 Q2 Q1
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 0 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 0 1 0 1
10 0 0 0 0
Generation of A State Diagram from A TimingChart
 A common method in describing digital systems uses a timing chart. This chart
indicates the operations must take place during particular time slots in order for the
system to function properly. These operations are initiated by control signals and the
timing chart indicates when each control signal must beasserted.

 The state diagram is essential in the hardware design of the system and hence after the
timing chart, the system design can proceed to the development of the state diagram. A
trial-and- error procedure is often the most efficient method to beused.

 Let us consider the following timing chart of a simple digitalcontroller.

Fig. 6.6: A digital system timing chart

 Here, X and Y are the system inputs and the clock signal is also shown. The system
does not give the output as long as X & Y are simultaneously 0. We have to develop a
state diagram to implement this timing chart with a minimum number of states and
without usingcounters.

From this timing chart we can say that,

 All state changes must take place on the positive-going transitions of the clock since
the inputs change on the negativetransition.
The output assertions begin at the positive transition of theclock

Equivalent state & redundantstate

• In state machine design, one of the first tools used is the state diagram. Some of these
diagrams may contain extra or redundant states that could be eliminated to decrease the design
complexity. In a state machine, two major tasks are completed during each stage:

• Outputs are generated, if necessary

• The signals producing the correct next state must be generated.

Equivalent states: If a state machine is started from either of two states and identical output sequences
are generated from every possible set of input sequences, the two states are said to be identical.

Redundant states: A state that is equivalent to another state is called a redundant state.

• The redundant states can be removed. Hence a reduced state diagram contains no equivalent
states. There is an orderly method available to identify and eliminate redundant states. This
method is a simplified version of a more complex method that is generally applied to
asynchronous system.
 • For practical synchronous systems, the following method is often sufficient to create the
reduced state diagram.

a) The next state table for the state diagram is constructed

b) Equivalent states are then identified
c) As equivalent states are identified, all but one are considered redundant and thus be
considered single state.

• Actually, the simplified method of reducing states does not guarantee a minimal no. of states.
More complex method can be carried out by executing the following steps:

a) Reduce the state table as far as possible using the simple method.
b) Group states having equivalent outputs together.
c) Within each group, eliminate those states that are not potentially equivalent.
d) Within each group, assume the equivalence of every possible pair of states.

• By following this procedure, final reduced state diagram can be obtained.

General State MachineArchitecture

Traditional State Machines

 The general block diagram of the state machine along with 2 possible variations is shown
below.

1. General state machine

 The general state machine architecture consists of input forming logic, memory
and output forming logic. The next state and the outputs are generated according
 to the design.

2. State machine with output-holding register

 The output holding register is added to latch the outputs into this register at the
midpoint of the state machine or after the state flip-flops settle. This
arrangement is used to filter out the glitches from the output decoder.

3. State machine with input-synchronizing register

 A synchronizing register is used to convert asynchronous inputs to synchronous

variables. The state machine is then controlled by synchronous variables.
Although, no output holding register is used, it may be added to the system if

needed.
6.9.2 The“One-Hot” state machine

• The methods of state machine design are based on the use of minimum number of state flip-
flops. If m states are required to implement a sequential controller, the no of state flip-flops
required n, is found by selecting the minimum value of n to satisfy: 2n ≥ m
• This approach minimizes hardware requirements but there are certain disadvantages in certain
applications.

• In sequential controllers for digital computers, there is often a need for the state machine to be
in 2 states simultaneously. Since, conventional state machines always exist in a single unique
state at any given time, only one series of operations can be controlled.

• The “one-hot” state machine, which associates each state with the assertion of a specific state
flip-flop, can solve this problem. In a sequential system that progresses through a series of
unique states, only one flip-flop is asserted during each stage. However, if two states must exist
simultaneously, two flip-flops can be asserted. The output signals produced by each state flip-
flop can then be used to control two operations simultaneously.

• These types of system allow the implementation of the fork and join operations in digital
controllers. The figure below shows the idea of forking and jerking in a state machine controller.

• The state machine progresses from state a to b. at this point, depending on an input, the system
creates two states, c and g, that exist during t3. Two states also exist during t4 (d and h) and
during t5 (e and i). As t6 is entered, the system returns to a single state f. during time slots t3
, t4 & t5 , two separate processes can be controlled concurrently.

Advantages of “one-hot” state machine design:

a) State machine can enter in two states simultaneously.
b) Design methods are simpler
 c) This type of controller is more preferable for computer-aided design techniques than is
the conventional state machine.
d) This design leads to shorter development time

Problems of AsynchronousCircuits
 Asynchronous state machines are not as widely used as synchronous machines since
there are three problems such as hazards, oscillations and criticalraces.

1. Hazards

 A glitch is when a signal temporary takes on the wrong value. Glitches caused by
structure of circuit and propagation delays are calledhazards.

 There are two types ofhazards;

a) StaticHazards
 When signal is not supposed to change its value in response to a specific change in
an input, but instead momentarily does change is known as statichazard.

b) DynamicHazards
 This is when a signal is supposed to change value, but there is a smalloscillation.

Fig. : Static and Dynamic hazard

 A change to a primary input often has more than one path of propagation to an
output. When one path has a longer propagation delay than the others, we may find
a statichazard.
  This can be eliminated by examining the K-map of the output. A potential hazard exists
whenever two adjacent ones (or 0’s if we are doing a product-of-sum implementation) are not
covered by a common product term (sum term forproduct-of-sum).
 To guarantee no static hazards, obtain a cover such that each pair of adjacent one’s(zero’s)
is covered by a common product term (sum term).

 A dynamic hazard is caused by the structure of a circuit. It is caused by a circuit with more
than two levels, in which changes to an input have more than one path to propagate. A circuit
with a dynamic hazard must also contain a statichazard

 To avoid dynamic hazards, design two-level circuits with no statichazards.

2. Oscillations

 A second problem that can occur in a poorly designed circuit is that of oscillation. Consider the
excitation map as shownbelow.

Fig. : An excitation map

 If the system is in state a, a change of input from B = 0 to B = 1 sends the system to state c.
State c is the transient state, and thus the excitation variable X changes to1.
 A short time later, x changes to 1, moving the system to state d. This state is also the transient
state changing back X to 0, followed by change in x to0.
 The system now oscillates between states c and d. this is known as oscillation and is
unacceptable in most systems. Hence, the situation depicted by states c and d of the map
must beavoided.
 3. Criticalraces

 A third problem in asynchronous design is that of critical races. This

situation can occur only when two or more feedback variables are present in
the system. The below figure demonstrates the critical raceproblem.

 This system has two external inputs, A and B, and two excitation variables,
X and Y, that are feedback to the input of thecircuit.

 Due to unequal propagation delays, one of the excitation variables will reach
a value of 1, while the other has not changed from a value of 0. The final
stable state reached from this condition depends on the relative switching
speeds of variables X and Y. This situation is referred to as criticalrace.

 In some cases, a final state is never reached. Such a situation is also called
critical race. Critical races obviously must beavoided.

Fig. : An excitation map with critical races

Hence, in designing asynchronous circuits, hazards, oscillations and critical races must
be avoided.

POST MCQ:
1. The second step of making the transition table is
a. Determining feedback loop
b. Designating output of loops
c. Deriving functions of Y
d. Plotting Y Answer : b

2. Each logic gate gives a delay of

 a. 1 to 5 ns
b. 2 to 10 ns
c. 3 to 10 ns
d. 3 to 5 ns Answer : b

3. The NAND latch works when both inputs are

a. 1
b. 0
c. Inverted
d. Don’t cares Answer : a

4. The change in state occurs during

a. Pulse transition
b. Outputs
c. Clock pulses
d. Inputs Answer : a

5. Asynchronous sequential logic circuit not uses

a. Inputs
b. Outputs
c. Clock pulses
d. Time Answer : c

6. Naming the states is done in

a. Transition table
b. Stable state
c. Flow table
d. Excitation table Answer : c

7. The delay elements provide

a. Large memory
b. Outputs
c. Clock pulses
d. Short term memory Answer : d

8. The analysis of Asynchronous sequential circuits are used to obtain

a. A table
b. A diagram
c. Graph
d. Flow chart Answer : a
9. During the design of asynchronous sequential circuits, it is more convenient to name
the state by letters this type of table is known as
a. Square table
b. Latch table
c. Flow table
d. None of above Answer : a

10. In the design procedure of the asynchronous circuit, the flow of the table
a. Increased to maximum states
b. Reduced to minimum states
c. Changed
d. Remain same Answer : b
 UNIT V
LOGIC FAMILIES AND PROGRAMMABLE LOGIC DEVICES
AIM
Expose the students to various memorydevices and to Design the Digital
circuits using HDL programming

POST MCQ:
1. Once a PAL has been programmed:

a. It cannot be reprogrammed
b. Its outputs are only active HIGHs
c. Its outputs are only active LOWs
d. Its logic capacity is lost
Answer: a

2. The difference between a PLA and a PAL is:

a. The PLA has a programmable OR plane and a programmable AND plane, while the
PAL only has a programmable AND plane
b. The PAL has a programmable OR plane and a programmable AND plane, while the
PLA only has a programmable AND plane
c. The PAL has more possible product terms than the PLA
d. PALs and PLAs are the same thing.
Answer: A

3. .Which among the following are used in programming array logic (PAL) for reducing the
loading on inputs?

a. Input buffers
b. Output buffers
c. OR matrix
d. AND matrix
Answer: A

4. PAL refers to

a. Programmable Array Loaded

b. Programmable Logic Array
c. ProgrammableArrayLogic
d.None of the Mentioned
 Answer: C

5. PLA is used to implement

a. A complex sequential circuit

b. A simple sequential circuit
c. A complex combinational circuit
d. A simple combinational circuit
Answer: C

6. Applications of PLAs are

a. Registered PALs
b. Configurable PALs
c. PAL programming
d. All of the Mentioned
Answer: d

THEORY
Introduction
Logic families represent kind of digital circuit/methodologies for logic expression
Integration levels:
SSI: Small scale integration 12 gates/chip
MSI: Medium scale integration 100 gates/chip
LSI: Large scale integration 1K gates/chip
VLSI: Very large scale integration 10K gates/chip
ULSI: Ultra large scale integration 100K gates/chip
Classification
Logic Family
 Bipolar Logic Family
o Saturated
 RTL(resistor transistor logic)
 DCTL(direct coupled transistor logic)
 IIL(integrated injection logic)
 DTL(diode transistor logic)
 HTL(high threshold logic)
 TTL(transistor transistor logic)
o Non Saturated
  Schottky TTL
 ECL(emitter coupled logic)
 ULF(unipolar logic family)
o PMOS(p-channel MOSFET)
o NMOS(n-channel MOSFET)
o CMOS

Fan In
o Fan in or gate is the number of inputs that can practically be supported without degrading
practically input voltage level.

Fan in = 4
Fan Out
o The maximum number of digital input that the output of a single logic gate can feed and
the gate must be same logic family.

o Fan Out is calculated from the amount of current available in the output of a gate and the
amount of current needed in each input of the connecting gate.

o It is specified by manufacturer and is provided in the data sheet.

o Exceeding the specified maximum load may cause a malfunction because the circuit will
not be able supply the demanded power.

Fanout = 4
Noise Margin

o Noise is present in all real systems. This adds random fluctuations to voltages
 representing logic levels.

o Hence, the voltage ranges defining the logic levels are more tightly constrained at the
output of a gate than at the input.

o Small amounts of noise will not affect the circuit. The maximum noise voltage that can
be tolerated by a circuit is termed its noise immunity (noise Margin).

Propagation Delay
Transistor as a switch

o A circuit that can turn on/off current in electrical circuit is referred to a switching
circuit and transistor can be employed as an electronic switch
o Cut off region - OFF State
o Both junctions are reverse biased, Ic = 0 and V(BE) < 0.7 v
o Saturation region - ON State Ic = maximum and V(BE)>0.7 v

Resistor Transistor Logic(RTL)

o The basic
asic RTL device is a NOR gate.

o The inputs represent either logic level HIGH (1) or LOW (0).

o The logic level LOW is the voltage that drives corresponding transistor in cut-off
cut region,
while logic level HIGH drives it into saturation region.

o If both the inputs

nputs are LOW, then both the transistors are in cut
cut-off
off i.e. they are turned-off.
turned
Thus, voltage Vcc appears at output I.e. HIGH.
 o If either transistor or both of them are applied HIGH input, the voltage Vcc drops across
Rc and output is LOW.

(NOR GATE USING RTL)

Advantages of RTL Logic circuit:

The primary advantage of RTL technology was that it involved a minimum number of
transistors, which was an important consideration before integrated circuit technology, as
transistors were the most expensive component to produce

Limitations:

The obvious disadvantage of RTL is its high current dissipation when the transistor conducts to
overdrive the output biasing resistor. This requires that more current be supplied to and heat be
removed from RTL circuits. In contrast, TTL circuits minimize both of these requirements.
Diode Transistor Logic

o The diode-transistor logic, also termed as DTL, replaced RTL family because of greater
fan-out
o capability and more noise margin.

o DTL circuits mainly consists of diodes and transistors that comprises DTL devices.
 o The basic DTL device is a NAND gate.

o Two inputs to the gate are applied through diodes viz. D1, D2 . The diode will conduct
only when corresponding input is LOW.

o If any of the diode is conducting i.e. when at least one input is LOW, the voltage at
output keeps transistor T in cut-off and subsequently, output of transistor is HIGH. If all
inputs are HIGH, all diodes are non-conducting, transistor T is in saturation, and its
output is LOW.

.
Due to number of diodes used in this circuit, the speed of the circuit is significantly low. Hence
this family of logic gates is modified to transistor-transistor logic i.e. TTL family which has been
discussed on next slide.

(DL AND GATE) (SATURATING

INVERTER)
Transistor Transistor Logic

o TTL family is a modification to the DTL. It has come to existence so as to overcome the
speed limitations of DTL family. The basic gate of this family is TTL NAND gate.

o Q3 is cutoff (act like a high RC ) when output transistor Q4 is saturated and Q3 is

saturated (act like a low RC ) when output transistor Q4 is cutoff . Thus one transistor is
ON at one time.

o The combination of Q3 and Q4 is called TOTEM POLE arrangement.

 o Q1 is called input transistor, which is multi emitter transistor, that drive transistor Q2
which is used to control Q3 and Q4.

o Diode D1 and D2 are used to protect Q1 from unwanted negative voltages and diode D3
ensures when Q4 is ON, Q3 is OFF.

The output impedance is asymmetrical between the high and low state, making them unsuitable
for driving transmission lines. This drawback is usually overcome by buffering the outputs with
special line-driver devices where signals need to be sent through cables. ECL, by virtue of its
symmetric low-impedance output structure, does not have this drawback

Emitter Coupled Logic

o ECL logic family implements the gates in differential amplifier configuration in which
transistors are never driven in the saturation region thereby improving the speed of circuit
to a great extent. The ECL family is fastest of all logic families.

o Based on BJT, but removes problems of delay time by preventing the transistors from
saturating.

o Very fast operation - propagation delays of 1ns or less.

o Low noise immunity of about 0.2-0.25 V .

 o The input impedance is high and the output impedance is low. As a result, the transistors
change states quickly, gate delays are low, and the fan out capability is high.

(ECL 2 Input OR/NOR GATE)

Function Table
Truth Table

Complimentary MOS (CMOS)

o Considerably lower energy consumption than TTL and ECL, which has made portable
electronics possible.

o Most widely used family for large-scale devices

o Combines high speed with low power consumption

o Usually operates from a single supply of 5 – 15 V

o Excellent noise immunity of about 30% of supply voltage

o Can be connected to a large number of gates (about 50)

Some statistical characteristics data of different logic families

INTRODUCTION TO PROGRAMMABLE LOGIC DEVICES (PLD):
Programmable Logic Circuit
1. Hardwire System / Circuit
 The operation of any circuit depends on IC chips used & electrical connection between
chips.
 No access to internal interconnections of IC chips.
 To design circuit, internal circuit diagram is to be specified.
 Once designed, the intended function can be performed.
 If the function changes, design needs to modified.
 So the internal circuit diagram needs to be changed.
 Such systems are called HARDWIRED SYSTEM.
2. Programmable Circuit
 It uses programmable components.
 Device includes arrays of logic elements on a chip & allows the user to specify or
program many internal connections between these components on the chip.
 Logic elements could be various gates, inverters, buffers and even flip flops.
 A system function can be created on the chip, simply by programming the chip or telling
the chip where the interconnections are to be made.
 Such devices in general are called PROGRAMMABLE LOGIC DEVICE.
3. Programmable Logic Devices (PLD):-
 PLD is an IC chip that includes arrays of logic elements and allows a user to specify the
connections among many of these elements.

Advantages:
  Chip count & physical size of a system can be minimized.
 Time from conception of system to marketing of the system can be minimized.
 Less chip count leads to integration of system on a single chip or small no. of chips.
 Low development cost.
 Less space requirement.
 High reliability.
 Easy circuit testing.
 Easy design modification.
Disadvantages:
 Interconnections between elements on the chip must be specified or programmed.
 PLDs also have hard wired connection but they cannot function until they are
programmed while Hardwired System functions.

TYPES OF PROGRAMMABLE LOGIC DEVICES (PLD):

Programmable Arrays
 OR Array
 AND Array
Classifications of Simple Programmable Logic Devices (SPLD)
 Read-Only Memory (ROM)
 Programmable Array Logic (PAL)
 Programmable Logic Array (PLA)
 Programmable Logic Sequencer (PLS)
More complex
 FPGA (Field Programmable Gate Arrays)
 CPLD (Complex Programmable Logic Devices)

Classifications of Simple Programmable Logic Devices (SPLD)

Read Only Memory (ROM / PROM):
 N-input address lines, m-output data lines.
 Address lines point locations within ROM that store words of m bits.
 ROM size is defined by the no. of locations & the word size.
 A 256 X 4 ROM indicates that the device has 256 storage locations each holding a 4-bit
word.
 This ROM would require eight address lines to access 256 locations.
 ROM of 32 X 8 has 32 memory locations each of 8-bit word and requires 5 address lines.
 Structure of ROM is as shown below;

 So No. of address lines (Input Lines) = n.

 No. of data lines (Output Lines) = m.
 ROM size = 2n X m.
 Size of decode which is to be used = n X 2n .
 ROM Consists of an array of semiconductor devices interconnected to store an array of
binary data.
 Can’t be changed once burned in.
 Conceptually, consist of a decoder and a memory array.
 Circuit diagram of ROM

Advantages:
 Design become extremely easy.
 It is possible to change or modify the design quickly.
 Reduced cost.
 Modification takes less time than SSI/MSI circuits.
Disadvantages:
 Increase in power requirement.
 Complete circuit is not utilizes
 Increase in size with increase in number of input variables.

EXAMPLE 1: Tabulate the truth for an 8 X 4 ROM / PROM that implements the following four
Boolean functions:
A(X,Y,Z) = ∑m(1,3,4,6)
B(X,Y,Z) = ∑m(2,4,5,7)
C(X,Y,Z) = ∑m(0,1,5,7)
D(X,Y,Z) = ∑m(1,2,3,4)
ANS:
Here, total No. of inputs are three  A,B,C Total No. of outputs are four  A,B,C,D
ROM size is = 8 X 4 So, according 2n X m  Inputs = n = 3, Output = m = 4, Size of
Decoder = n X 2n = 3 X 8

INPUT OUTPUT
A B C D
X’Y’Z’(000 0 0 1 0
)
X’Y’Z 1 0 1 1
(001)
X’YZ’ 0 1 0 1
(010)
X’YZ(011) 1 0 0 1
XY’Z’ 1 1 0 1
(100)
XY’Z 0 1 1 0
(101)
XYZ’ 1 0 0 0
(110)
XYZ (111) 0 1 1 0
 Here, * = Programmed Connection
● = Fixed Connection
EXAMPLE 2: What are functions F3, F2, F1 and F0 in terms of (A2, A1,A0) ?

ANS:
 F3 = D7 + D5 + D2 = A2A0 + A2’A1A0’
 F2 = D7 + D0 = A2A1A0 + A2’A1’A0’
 F1 = D4 + D1 = A2 A1’A0’ + A2’A1’A0
 F0 = D7 + D5 + D1 = A2A0 + A1’A0
EXAMPLE 3: Tabulate the truth for an 8 X 4 ROM / PROM that implements the following four
Boolean functions:
A(X,Y,Z) = ∑m(3,6,7);
B(X,Y,Z) = ∑m(0,1,4,5,6)
C(X,Y,Z) = ∑m(2,3,4);
D(X,Y,Z) = ∑m(2,3,4,7)

ANS:
ROM size is = 8 X 4 So, according 2n X m
Inputs = n = 3, Output = m = 4,
Size of Decoder = n X 2n = 3 X 8
Inputs are -> X,Y,Z
Outputs are -> A,B,C,D
Programmable Array Logic (PAL):
 PAL is most commonly used type of PLD. It is a programmable array of logic gates.
 The array of logic gates is on single chip and it is in the AND-OR configuration.
 The special feature of PLA is that a programmable AND array and fixed OR array.
 Also note that in each OR gate in the OR array gets input from some of the AND gates.
That means output of all AND gates are not applied to any of the OR gates

 Un-programmed and programmed PAL are shown in below figure.

Un-programmed PAL
Programmed PAL
 In Un-programmed PAL all the links are connected with Fusible Link as shown in below
figure.
 As per required output function one needs to burn the fusible link and this kind of PAL is
known as a programmed PAL.
  Simplified representation of PAL is shown in below figure.

Input Buffers:
 Input buffer in a PAL is used for avoiding the loading of sources connected at the inputs.
 The buffer produce inverted and non-inverted versions of their corresponding inputs.
 One such buffer is used for each of the input lines as shown in above figure.
AND Matrix:
 AND matrix is shown as above figure.
 The (X) mark indicate that a connection is present. Each AND gate has 2M input which
are shown only by a single line (e.g. A,B,C, etc….). Where M is the No. of inputs.
 When a logic function is to be implemented, we have to program the array. In
programming the desired connections are left with the (X) marks and such mark is not
used when connection is not required.
OR Matrix:
 OR matrix is shown as above figure. In PAL fixed OR array is used so there is no need to
do programming to the OR array.
 No. of OR arrays are equal to the required No. of functions at the output.
Input and Output Circuit:
 The input and output circuit of PAL are similar to those PLAs.
 The No. of fusible link in PAL is equal to 2M x n. where M = No. of available inputs and
n = Corresponds to No. of product terms.
Advantages:
 For given internal complexity, a PAL can have larger N and M.
 Some PALs have outputs that can be complemented, adding POS functions.
 No multilevel circuit implementations in ROM (without external connections from output
to input). PAL has outputs from OR terms as internal inputs to all AND terms, making
implementation of multi-level circuits easier.
Disadvantages:
 n x m ROM guaranteed to implement any m functions of n inputs. PAL may have too few
inputs to the OR gates.

Designing steps of Combinational Circuits using PAL

 STEP 1: Prepare the Truth Table.
 STEP 2: Write a Boolean expression in SOP form.
 STEP 3: Reduce / Find the Boolean expressions using K-map or reducing Boolean
expression method.
 STEP 4: List of product terms for each of the function and decide total No. of AND &
OR gates required.
 STEP 5: Decide connections of AND and OR matrix & draw logic diagram.
NOTE: Out of first three steps, all three steps may not require in all examples
EXAMPLE 1: A combinational circuit is defined by given truth Table for that Implement the

circuit using PAL

ANS:
 STEP 1: Prepare the Truth Table.
This step is not required in this example because it is given.
 STEP 2: Write a Boolean expression in SOP form.
This step is not required in this example
 STEP 3: Find the Boolean expressions using K-map or reducing Boolean expression
method

 STEP 4: List of product terms for each of the function and decide total No. of AND &
OR gates required.
W = A + BD + BC
X = BC’
Y=B+C
Z = A’B’C’D + BCD + AD’ + B’CD’
Total No. of AND gate = 16 (B’cz maximum No. of product terms are in function Z (4
product terms) and total No. of functions are 4 so 4 X 4 = 16).
Total No. of OR gates = Total No. of required functions at the output side (W,X,Y,Z) = 4.
 STEP 5: Decide connections of AND and OR matrix & draw logic diagram
Programmable Logic Array (PLA):
 A PLD generally consist of programmable array of logic gates. Interconnections are
made with the array inputs.
 PLA consist two levels of logic, an AND-plane and an OR-plane, where both levels are
programmable.
 The outputs are connected to the device pins through inverting or non-inverting buffers
and flip flops.
 The basic block diagram of a PLA is shown in below figure.
 Here programmable AND matrix can be used to implement the product terms in the SOP
 form and the programmable OR array can be used for implementing the sum of the
product terms.
 Logic gates used can be two level AND-OR, NAND-NAND or NOR-NOR
configuration. Sometimes AND-OR-EXOR configuration is also used. But generally
AND-OR is most preferable configuration.
 Simplified representation of PLA is shown in below figure.

Simplified block diagram of PLA

Simplified representation of PLA

In PLA No. of outputs = No. of OR gates.
And No. of Product terms = No. of AND gates

Size of PLA is defines as M x P x N

Where M = No. of inputs, P = No. of product terms, N = No. of outputs

Input Buffers:
 Input buffer in PLA is used for avoiding the loading of sources connected at the inputs.
 Buffer of two types namely, inverted buffers and non-inverted buffers as shown in below
 figure.
 One such buffer is used in each of the M input lines.

AND Matrix:
AND matrix
 The X indicates that a connection is present. Each AND gate has 2M inputs which are
shown only by single line where, M is No. of inputs (e.g. A,B,C, etc….).
 When a logic function is to be implemented, we have to program the array. In
programming the desired connections are left with the (X) marks and such mark is not
used when connection is not required.
OR Matrix:

OR Matrix:
 Above figure shows simplified representation of the OR matrix.
 It is possible to program the OR matrix, by open circuiting the unwanted fusible links.
The open fusible links are equivalent to a ‘0’ at the input of corresponding OR gate.
Applications of PLA:
1. We can implement combinational circuit using PLA. For this only ouput buffers are
used.
2. We can also implement sequential circuit using PLA. For implement this flip flops and
buffers are included in output stage.

Designing steps of Combinational Circuits using PLA

 STEP 1: Prepare the Truth Table.
 STEP 2: Write a Boolean expression in SOP form.
 STEP 3: Reduce / Find the Boolean expressions using K-map or reducing Boolean
expression method.
 STEP 4: List of unique product terms.
 STEP 5: PLA table implementation.
 STEP 6: Decide connections of AND and OR matix & draw logic diagram.
NOTE: Out of first three steps, all three steps may not require in all examples

EXAMPLE 1: Draw combinational circuit for a PLA with three inputs, three product terms and
two outputs.
ANS:
Given, No. of inputs = 3 = I0, I1, I2
No. of Outputs = 2 = No. of OR gates.
NO. of product terms = No. of AND gates
Difference between ROM, PAL and PLA.

ROM/PROM PA PL
L A
Consist of fixed AND gate Consist of programmable Consist of programmable
array andprogrammable AND gate array and fixed AND gate array and
OR array. OR array. Programmable OR array.
Medium speed High speed (only one Slow (two programmable
programmable gates gates arrays)
arrays)
Cheap (High-volume Intermediate cost (less than Most expensive (Most
component) PLA) complex in design)
Not flexible Not flexible Offering maximum
programmingflexibility
It is possible to decode any We can get any desired We can get any desired
minterms minterms by programming minterms by programming
the AND matrix the AND & OR matrix
SOP function in the Any SOP function can be Any SOP function can be
standard form only canbe implemented implemented
implemented

POST MCQ:
1. PAL stands for
a. Portable array logic
b. Programmable advanced logic
c. Programmable array logic
d. Portable advanced logic
Answer: C

2. ROM stands for

a. Random optical memory
b. Read optical memory
c. Random only memory
d. Read only memory
Answer: d
3. What do the Programmable Logic Devices (PLDs) designed especially for the combinational
circuits comprise?
a. Only gates
b. Only flip flops
c. Both a and b
d. None of the above
Answer: a

4. Which gates are used on the output side as buffers in order to provide a programmable output
polarity in PAL 16 P8 devices?
a. AND
b. OR
c. EX-OR
d. NAND
Answer: C

5. In VHDL, which object/s is/are used to connect entities together for the model formation?
a. Constant
b. Variable
c. Signal
d. All of the above
Answer: C

6. A for loop is initiated as given below, in total how many iterations will be there for the FOR
loop?
FORiIN0TO5LOOP
a) 3
b) 4
c) 5
d) 6
Answer: D

7. Which type of simulation mode is used to check the timing performance of a design?
a. Behavioural
b. Switch-level
c. Transistor-level
d. Gate-level
Answer: D

8. What kind of circuit may be described by using the following statement?

ASSERTNOT(s=’1’ and r = ‘1’)REPORT ‘’INVALID! S and R both can’t be 1” SEVERITY
ERROR
a) Flip flop
b) Multiplexer
c) Decoder
d) Counter
Answer: A
9. How many forms of WAIT statement are there in VHDL?
a) 1
b) 2
c) 3
d) 4
Answer: C

10. What is the use of assert statement in VHDL?

a) To print any string
b) To check the consistency and generate a message
c) Cause execution of sequential statements to wait
d) To check if a condition can stop the execution
Answer: B

COURSE OUTCOME
The students should be able to:
 Understand the basic number system and Boolean algebra.
 Understand the basics of combinational and Sequential circuits.
 Know about Flip flops and their designing.
 Analyze about State reduction techniques and various hazards present in the
circuit.
 Understanding the concepts of VHDL programming for designing Digital circuits.

TEXT BOOKS
1. W.H. Gothmann, “Digital Electronics - An Introduction, Theory and Practice”,
Prentice Hall of India.2nd Edition, 2000.
2. M. Morris Mano, “Digital Design”, 4th Edition, Prentice Hall of India Pvt. Ltd., 2008
/ Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003..
3. Frank Vahid “VHDL for Digital Design-With RTL design, VHDL & Verilog”- John
Wiley & Sons, 2010.
4. Jain—Modern Digital Electronics, 2/e ,TMH

References
o Switching Circuit and Logic Design by Prof. Indranil Sengupta, IIT KGP
o Modern digital Electronics by R P Jain
o NPTEL VIDEO by Dr. Amitava Dasgupta, IITM
o Logic Families by Dr. Basem Elhalawany
o Logic Gates and Family by Dr. A. P. VAJPEYI, IITG