ILI6122

ILI6122
1200-Output Channel
TFT LCD Source Driver with TCON
Specification
Preliminary
Version: V0.08
Document No.: ILI6122_SPEC_V008.pdf
ILI TECHNOLOGY CORP.

8F, No. 38, Taiyuan St., Jhubei City,
Hsinchu Country 302 Taiwan R.O.C.
Tel.886-3-5600099; Fax.886-3-5670585
http://www.ilitek.com
1200-Output Channels
TFT LCD SOURCE DRIVER WITH TCON ILI6122
Table of Contents
Section Page
1. Introduction.................................................................................................................................................... 4
2. Features ........................................................................................................................................................ 4
3. Block Diagram ............................................................................................................................................... 6
3.1. Function Block Diagram ................................................................................................................... 6
3.2. Application Block Diagram ............................................................................................................... 7
3.2.1. 800(RGB) x 480 (Gate driver on left side)............................................................................. 7
3.2.2. 800(RGB) x 600 (Gate driver on left side)............................................................................. 8
3.2.3. 800(RGB) x 480 (Gate driver on right side)........................................................................... 9
3.2.4. 800(RGB) x 600 (Gate driver on right side)......................................................................... 10
4. Pin Descriptions .......................................................................................................................................... 11
5. Operation Description ................................................................................................................................. 16
5.1. Relationship between input data and output channels .................................................................. 16
5.1.1. Stripe Mode ......................................................................................................................... 16
5.2. Dot Polarity Inversion ..................................................................................................................... 17
5.3. Gate Scan Sequence ..................................................................................................................... 18
5.4. CABC (Content Adaptive Brightness Control) ............................................................................... 20
5.5. Application Block Diagram ............................................................................................................. 21
5.6. Display Data Input Timing .............................................................................................................. 23
5.6.1. Vertical Input Timing ............................................................................................................ 23
5.6.2. Horizontal Input Timing........................................................................................................ 23
5.6.2.1. SYNC Mode (MODE=”L”).................................................................................................... 23
5.6.2.2. DE Mode (MODE=”H”) ........................................................................................................ 24
5.7. Relationship between gamma correction and output voltage ........................................................ 25
5.8. Power ON/OFF Sequence ............................................................................................................. 27
5.9. Standby ON/OFF Control ............................................................................................................... 28
5.10. The BIST Patterns for Aging Mode Test......................................................................................... 29
5.11. The Command Format for 3-line Serial Interface .......................................................................... 30
5.12. Command List ................................................................................................................................ 31
5.13. Command Description.................................................................................................................... 32
5.13.1. Write Display Brightness Value (51h) .................................................................................. 32
5.13.2. Read Display Brightness Value (52h).................................................................................. 32
5.13.3. Write CTRL Display Value (53h).......................................................................................... 32
5.13.4. Read CTRL Display Value (54h) ......................................................................................... 33
5.13.5. Write Content Adaptive Brightness Control Value (82h)...................................................... 33
5.13.6. Read Content Adaptive Brightness Control Value (82h) ..................................................... 34
5.13.7. Write CABC Minimum Brightness (5Eh).............................................................................. 34
5.13.8. Read CABC Minimum Brightness (5Fh).............................................................................. 34
5.13.9. CABC Control 1 (60h).......................................................................................................... 35
Page 2 of 57 Version: 0.08

5.13.10. CABC Control 2 (61h) ..................................................................................................... 36
5.13.11. CABC Control 3 (62h) ..................................................................................................... 37
5.13.12. CABC Control 4 (63h) ..................................................................................................... 38
5.13.13. CABC Control 5 (64h) ..................................................................................................... 39
5.13.14. CABC Control 6 (65h) ..................................................................................................... 39
6. DC Characteristic ........................................................................................................................................ 40
6.1. Absolute Maximum Rating (DGND = AGND=0V, Ta=25℃)........................................................... 40
6.2. DC Electrical Characteristics (DGND=AGND=0V, Ta=25℃) ......................................................... 40
7. AC Characteristics ...................................................................................................................................... 41
7.1. AC Timing characteristics............................................................................................................... 41
7.2. Display Timing characteristics........................................................................................................ 45
7.2.1. Resolution: 800x480............................................................................................................ 45
7.2.2. Resolution: 800x600............................................................................................................ 47
8. Pad Sequence (Bump Side)........................................................................................................................ 48
9. Pad Arrangement and Coordination............................................................................................................ 49
10. Revision History .......................................................................................................................................... 57

1. Introduction
ILI6122 is a 1200-channel output source driver with TTL interface timing controller (TCON). The
interface follows digital 24-bit parallel RGB input format. The TCON generates the 800x480 and 800x600
resolutions and provides horizontal and vertical control timing to source driver and gate driver. It also supports
dithering feature, apply source driver with 6-bit DAC to perform 8-bit resolution 256 gray scales. Operating
parameters can be set via pin control for all control features. Since the output circuit of this source driver
incorporates an operational amplifier with low power dissipation, and performs wide voltage supply range and
small output deviation.
ILI6122 can be configured as dual-gate operation mode for reducing FPC amount and saving the cost.
With wide range of supply voltages and many pin control features make this chip mode suitable for various
applications.
2. Features
TCON
¾ Supports display resolution 800x480 and 800x600
¾ Supports digital 24-bit parallel RGB input mode
¾ Supports to configure CABC block via 3-line SPI mode
¾ Source output with 8-bit resolution for 256 gray scales (2-bit dithering)
¾ Supports dual-gate operation mode
¾ Supports Stripe CF configuration
¾ Maximum Operation frequency: 50 MHz
¾ Provide flip and mirror scan mode by pin control
¾ Supports stand-by mode for saving power consumption
¾ Operation Voltage Level 3.0V to 3.6V
¾ Hardware Pin Control CABC Mode Selection
Source Driver
¾ 1200 channels output source driver for TFT LCD panel
¾ Embedded custom-made Gamma table for special custom request
¾ Supports external V1~V14 pad for Gamma adjustment
¾ Output dynamic range : 0.1 ~ VDDA-0.1V
¾ Voltage deviation of outputs: ±20mV
¾ Power for source driver voltage (VDDA) : 6.5V ~ 13.5V

Others
¾ COG package
¾ Supports CABC (Content Adaptive Brightness Control) function

3. Block Diagram
3.1. Function Block Diagram

3.2. Application Block Diagram
3.2.1. 800(RGB) x 480 (Gate driver on left side)
(1,1) G1
(800,1) (800,1) G1 (1,1)
PATH
STV1
PATH
STV1
R G B R G B R G B R G B R G B R G B
G1
G2 G2
G1
G3 G3
ILI5960
ILI5960
G4 G4
G477 G477
G960 R G B R G B R G B R G B R G B R G B
G480
G960 G478
G478
G479 G479
G480 G480
800RGB*480 800RGB*480
PATH
STV2
CKV
UD
OE
(1,480) (800, 480) (800,480) (1, 480)

PATH
STV2
CKV
OE
UD
OE S1 S1200 OE S1 S1200
ILI6122
UD
ILI6122
UD
CKV CKV
STV1 STV1
STV2 STV2
RES0=L(800 X480) RES0=L(800 X480)

SHLR=H(S1 S1200) SHLR=L(S1200 S1)
UPDN=H(G1 G960) UPDN=H(G1 G960)
(1,480) G1 (800,480) (800,480) (1,480)

PATH
STV1
G1
PATH
STV1
R G B R G B R G B
R G B R G B R G B
G1 G2
G3 G2
G3
R G B R G B R G B
ILI5960
ILI5960
R G B R G B R G B
G4
G4
G477
G477
R G B R G B R G B
G960 R G B R G B R G B
G478
G479 G478
G479
R G B R G B R G B
R G B R G B R G B
G480
G480
800RGB*480
PATH
STV2
800RGB*480
CKV
UD
OE
(1,1) (800, 1)
PATH
STV2
UD
OE
CKV
(800,1) (1,1)
OE S1 S1200 S1 S1200
OE
ILI6122
UD
CKV UD
STV1
STV2
CKV
STV1
STV2
ILI6122
RES0=L(800 X480) RES0=L(800 X480)
UPDN=L(G960 G1) UPDN=L(G480 G1)

3.2.2. 800(RGB) x 600 (Gate driver on left side)
(1,1) G1 (800,1) (800,1) G1

(1,1)
PATH
PATH
STV1
STV1
G1 G1
G2
ILI5600
ILI5600
G2
G3 G3
G1
G1
G4 G4
G600 G600
PATH
STV2
PATH
STV2
CKV
CKV
UD
OE
UD
OE
G597 G597
G1 G1
R G B R G B R G B
ILI5600
ILI5600
R G B R G B R G B
G480
G480
G598 G598
G599 G599
G600 G600 G600
G600
800RGB*600 800RGB*600
PATH
STV2
CKV
PATH
UD
OE
STV2
CKV
UD
OE
(1,600) (800, 600) (800,600) (1, 600)
OE S1 S1200 S1 S1200
OE
UD UD
CKV
STV1
STV2
ILI6122 CKV
STV1 ILI6122
STV2
RES0=H(800 X600) RES0=H(800 X600)

(1,600) G1 (800,600) (800,600) G1 (1,600)

PATH
PATH
STV1
STV1
G1 G1
G2 G2
ILI5600
ILI5600
G3 G3
G1
G1
G4 G4
G600 G600
STV2
PATH
PATH
STV2
CKV
CKV
UD
OE
UD
OE
G597 G597
G1 G1
R G B R G B R G B
ILI5600
R G B R G B R G B
ILI5600
G480
G480
G598 G598
G599 G599
G600 G600 G600 G600
800RGB*600 800RGB*600
PATH
STV2
CKV
PATH
UD
OE
STV2
CKV
UD
OE
(1,1) (800, 1) (800,1) (1, 1)

OE S1 S1200 OE S1 S1200
UD UD
CKV
STV1
STV2
ILI6122 CKV
STV1
STV2
ILI6122
RES0=H(800 X600) RES0=H(800 X600)


3.2.3. 800(RGB) x 480 (Gate driver on right side)
(1,1) G480 (800,1) (800,1) G480 (1,1)

ST V2
PATH
ST V2
PATH
G479 G960 G479 G960
G478 G478
ILI5960
ILI5960
G477 G477
G4 G4
G1 G1
G3 G3
G2 G2
PATH
PATH
STV1
G1
STV1
G1
CKV
CKV
UD
UD
OE
OE
800RGB*480 800RGB*480
(1,480) (800, 480) (800,480) (1, 480)
OE OE
S1 S1200 UD S1 S1200 UD
ILI6122 CKV
STV2 ILI6122 CKV
STV2
STV1 STV1
RES0=L(800 X480) RES0=L(800 X480)

(1,480) G480 (800,480) (800,480) G480 (1,480)

ST V2
ST V2
PATH
PATH
G479 G960
G479 G960
G478 G478
ILI5960
ILI5960
G477 G477
G4 G4
G1 G1
G3 G3
G2 G2
PATH
PATH
G1
STV1
STV1
CKV
CKV
G1
UD
UD
OE
OE
800RGB*480 800RGB*480
(1,1) (800, 1) (800,1) (1, 1)
OE OE
S1 S1200 S1 S1200
UD UD
ILI6122 CKV
STV2
STV1
ILI6122 CKV
STV2
STV1
RES0=L(800 X480) RES0=L(800 X480)


3.2.4. 800(RGB) x 600 (Gate driver on right side)
(1,1) G600 (800,1) (800,1) G600 (1,1)
PATH
PATH
STV2
STV2
G599 G600 G599 G600
ILI5600
ILI5600
G598 G598
G597 G597
G1 G1
PATH
PATH
STV1
STV1
CKV
CKV
OE
UD
OE
UD
G4 G4
R G B R G B R G B G600 G600
R G B R G B R G B
ILI5600
ILI5600
G1
G1
G3 G3
G2 G2
G1 G1
G1 G1
800RGB*600 800RGB*600
PATH
PATH
STV1
STV1
CKV
CKV
OE
UD
OE
UD
(1,600) (800, 600) (800,600) (1, 600)
S1 S1200 OE S1 S1200 OE
UD UD
ILI6122 CKV
STV2
ILI6122 CKV
STV2
STV1 STV1
RES0=H(800 X600) RES0=H(800 X600)

(1,600) G600 (800,600) (1,1) G600 (800,1)

PATH
PATH
STV2
STV2
G599 G600 G599 G600
ILI5600
ILI5600
G598 G598
G597 G597
G1 G1
PATH
PATH
STV1
STV1
CKV
CKV
OE
UD
OE
UD
G4 G4
G600 G600
ILI5600
ILI5600
G1
G1
G3 G3
G2 G2
G1 G1
G1 G1
800RGB*600 800RGB*600
PATH
PATH
STV1
STV1
CKV
CKV
OE
UD
OE
UD
(1,1) (800, 1) (1,600) (800, 600)
S1 S1200 OE S1 S1200 OE
UD UD
ILI6122 CKV
STV2
ILI6122 CKV
STV2
STV1 STV1
RES0=H(800 X600) RES0=H(800 X600)


4. Pin Descriptions
Pin Name I/O Descriptions
Clock for input data. Data latched at rising/falling edge of this signal. Default is
CLKIN I
falling edge.
Digital data input. Dx0 is LSB and Dx7 is MSB.
D0[7:0]
D0[7:0] = R[7:0] data; D1[7:0] = G[7:0] data; D2[7:0]=B[7:0] data
D1[7:0] I
When 18-bit RGB interface (disable dithering function), please use Dx[7:2] as
D2[7:0]
6-bit input and connect Dx[1:0] to DGND.
HSD I Horizontal sync input in digital parallel RGB. Negative polarity.
VSD I Vertical sync input in digital parallel RGB. Negative polarity.
Input data enable control. When DE mode, active High to enable data input.
DEN I
(Normally pull low)
Data inverted control. Normally pull low

REV I REV=”1”: Data inverted for normally black LCD
REV=”0”: Data not inverted for normally white LCD. (Default)
DE / SYNC mode select. (Normally pull high)
MODE I MODE=“L”, for entering SYNC mode.
MODE=“H”, for entering DE mode.
A chip select signal. (Normally pull high)
CSX=”L”, the chip is selected and accessible
CSX I CSX=”H”, the chip is not selected and not accessible
Fix to the VDD level when not in use.
Multi-Function Selection:
When DBC/3=”L”, this pin act as 3-wire “SCL” pin.
SCL/DBCM[0] I Serial clock input. This pin is used for CABC command set only.
When DBC/3=”H”, this pin act as DBC mode select pin LSB (DBCM[0])
Note: Normal pull high and Fix to the VDD level when not in use.
Multi-Function Selection:
When DBC/3=”L”, this pin act as 3-wire “SDA” pin.
SDA/DBCM[1] I/O Serial data input / output. This pin is used for CABC command set only.
When DBC/3=”H”, this pin act as DBC mode select pin MSB (DBCM[1])
Note: Normal pull high and Fix to the VDD level when not in use.
RSTB I Hardware global reset. Low active. (Normally pull high)
The driving polarity inversion select. This pin is used for CABC command set
only. (Normally pull low)
INVSEL I
INVSEL=”L”, 2-dot inversion.
INVSEL=”H”, 1-dot inversion

Display resolution selection. (Normally pull low)
RES0 I RES0=“L”, for 800(RGB)x480 display resolution.
RES0=“H”, for 800(RGB)x600 display resolution.
Dithering function enable control. (Normally pull high)
DITHB I DITHB=“L”, to enable internal dithering function.
DITHB=“H”, to disable internal dithering function.
Input clock edge selection. (Normally pull low)
CLKPOL I CLKPOL=“L”, latch data at CLKIN falling edge.
CLKPOL=“H”, latch data at CLKIN rising edge.
DBC/3-wire selection pin(Normal pull high)
DBC/3 I DBC/3=”H”, Select DBC hardware control function.
DBC/3=”L”, Select 3-wire SPI interface function.
When VSET=“L”, the internal Gamma table is used and V1~V14 pins are
unused.
V1 ~ V14 I/O When VSET=“H”, V1~V14 pins are the external adjustment point for Gamma
correction. The relationship between V1~V14 must be :
AGND<V14<V13<V12<V11<V10<V9<V8<V7<V6<V5<V4<V3<V2<V1<VDDA
Gate on sequence. (Normally pull low)
GOSEQ=“L”, INVBRR/INVBRL will output “H” and gate on sequence is
GOSEQ I “G1ÆG2ÆG3ÆG4ÆG5ÆG6ÆG7ÆG8Æ……….ÆGn-3ÆGn-2ÆGn-1ÆGn”
GOSEQ=“H”, INVBRR/INVBRL will output “L” and gate on sequence is
“G1ÆG2ÆG4ÆG3ÆG5ÆG6ÆG8ÆG7Æ……….ÆGn-3ÆGn-2ÆGnÆGn-1”
Gamma correction source select. (Normally pull low)
VSET I VSET=“L”, to use internal Gamma reference voltage (VDDA).
VSET=“H”, to use external Gamma correction input (V1~V14).
DCMP enable control signal. (Normally pull low)
DCMP_EN I DCMP_EN=”L”, the DCMPL/DCMPR signals are disable.
DCMP_EN=”H”, the DCMPL/DCMPR signals are enable.
Standby mode control. (Normally pull high)
STBYB=“L”, enter standby mode for power saving. Timing controller and
STBYB I
source driver will turn off, all outputs are Hi-Z.
STBYB=“H”, normal operation.
Source shift direction control. (Normally pull high)
SHLR=“L”, shift direction is “S1200 Æ S1199Æ 1198 Æ • • • S3Æ Æ S2 Æ S1”
SHLR I
SHLR=“H”, shift direction is “S1 Æ S2Æ S3 Æ • • • Æ S1198 Æ S1199 Æ
S1200”.
Gate scan direction control (Normally pull low)
UPDN I
UPDN=“L”, STV2 outputs the vertical start pulse and UD pin outputs “L” to

Gate driver.
UPDN=“H”, STV1 outputs the vertical start pulse and UD pin outputs “H” to
Gate driver.
Normal operation / BIST pattern select. (Normally pull low)
BIST I BIST=“L”, Normal operation
BIST=“H”, BIST (DCLK input is not needed)
CABC function enable control. (Normally pull low)
CABC_EN=“L”, BLKEN pin is used to be backlight control signal for external
CABC_EN I backlight controller.
CABC_EN=“H”, ILI6122 will refer the gray scale content of display image to
output a PWM frequency to LED driver via BLKEN pin.
The backlight control signal for external backlight controller.
BLKEN=“L”, turn off the external backlight controller.
BLKEN=“H”, turn on the external backlight controller.
BLKEN O
Note : Refer to the Power ON/OFF sequence for the detail information when
CABC_EN is set to “L”.
Note: Keep Open when not in use.
OEVR/OEVL O Gate driver control signal.
UDR/UDL O Gate driver control signal.
CKVR/CKVL O Gate driver control signal.
STV1R/STV1L O Gate driver control signal.
STV2R/STV2L O Gate driver control signal.
STBNR/STBNL O Gate driver control signal.
INVBRR/INVBRL O Gate driver control signal.
DCMPL/DCMPR O Data line compensation.
VDDA P Power supply for analog block.
AGND P Ground level for analog block.
VDD P Power supply for digital block.
DGND P Ground level for digital block.
S1 ~ S1200 O Source driver output signals.
ALIGN -- For assembly alignment.
COM1_B COM1_B and COM2_B are short-circuited within ILI6122 for contact
--
COM2_B resistance measurement. Please leave it open when not in use.
COM1_T COM1_T and COM2_T are short-circuited within ILI6122 for contact resistance
--
COM2_T measurement. Please leave it open when not in use.
TP0 ~ TP4 I Test pins, not accessible to user, must be left open. (Normally pull low)
TP6 ~ TP10 O Test pins, not accessible to user, must be left open.
SHIELDING -- IC shielding pads. Those pins are internally connected to AGND level.

DASHD -- Data bus shielding pad. Those pins are internally connected to DGND level.
DUMMY -- Dummy pads. Please leave it open when not in use.
FB -- Reserved pins, not accessible to user.
DRV -- Reserved pins, not accessible to user.
PWM_EN -- Reserved pins, not accessible to user. (Normally pull low)
DBC/3 for CABC Function Control description:

DBC/3
Pin Name
L H ( Default )
CSX
Disable SPI Function, CABC Function mode by Hardware Pin control
SDA/DBCM[1] SCL/DBCM[0] Mode
SCL/DBCM[0] 0 0 User interface image
Enable SPI Function 0 1 CABC OFF
1 0 Moving image
1 1 Still picture
SDA/DBCM[1] Remark: Default Still Mode

Note: (1) Please power on following the sequence VDD Æ logic input Æ VDDA and V1 ~ V14. Reverse the
sequence to shut down.
(2) To stabilize the supply voltages, please be sure to insert a 0.1uF bypass capacitor between
VDD↔DGND and VDDA↔AGND. Furthermore, for increased precision of the D/A converter, insertion of a
bypass capacitor of about 0.01uF is also advised between the gamma-corrected power supply terminals (V1,
V2, …, V14) and AGND.
(3) Please keep V1~V14 not cross to the toggle signals as possible to avoid the AC coupling on the DC
V1~V14 voltage. When used as cascade mode, please keep the coupled amount of V1~V10 are the same
between the two chips.
(4) The input wiring resistance values affect power or signal integrity and the display quality. So be sure to
design using values that do not exceed those recommended as below.
Pin Name Wiring resistance value(Ω )
VDDA <5
AGND <5
VDD < 10
DGND < 10
V1 ~ V14 < 10
Dx[0:7] < 50
CLKIN < 50
VSD < 50
HSD < 50
DEN < 50
BLK_EN < 200
CSX < 200
SCL/DBCM[0] < 200
SDA/DBCM[1] < 200
RESX < 500
STBYB < 500
DITHB < 500
SHLR < 500
UPDN < 500
BIST < 500
MODE < 500
RES0 < 500
CLKPOL < 500
DBC/3 < 500
VSET < 500
INVBRR/INVBRL < 500
OEVR / OEVL < 500
UDR / UDL < 500
CKVR / CKVL < 500
STV1R / STV1L < 500
STV2R / STV2L < 500
STV2R / STV2L < 500
STBNR / STBNL < 500
Others < 500

5. Operation Description
5.1. Relationship between input data and output channels
5.1.1. Stripe Mode

The relationship between input display data and source output channels is illustrated as below:
SHLR=“L”, Left Shift Direction

Output S1 S2 S3 Å S1198 S1199 S1200
Order Last data --- First data
Odd Line / Gn D0[7:0] D2[7:0] D1[7:0] --- D0[7:0] D2[7:0] D1[7:0]
Odd Line / Gn+1 D1[7:0] D0[7:0] D2[7:0] --- D1[7:0] D0[7:0] D2[7:0]
Even Line / Gn D0[7:0] D2[7:0] D1[7:0] --- D0[7:0] D2[7:0] D1[7:0]
Even Line / Gn+1 D1[7:0] D0[7:0] D2[7:0] --- D1[7:0] D0[7:0] D2[7:0]
SHLR=“H”, Right Shift Direction

Output S1 S2 S3 Æ S1198 S1199 S1200
Order First data --- Last data
Odd Line / Gn D0[7:0] D2[7:0] D1[7:0] --- D0[7:0] D2[7:0] D1[7:0]
Odd Line / Gn+1 D1[7:0] D0[7:0] D2[7:0] --- D1[7:0] D0[7:0] D2[7:0]
Even Line / Gn D0[7:0] D2[7:0] D1[7:0] --- D0[7:0] D2[7:0] D1[7:0]
Even Line / Gn+1 D1[7:0] D0[7:0] D2[7:0] --- D1[7:0] D0[7:0] D2[7:0]

5.2. Dot Polarity Inversion
ILI6122 supplies both of 1-dot and 2-dot inversion, the pixel polarity inversion was illustrated as below:

5.3. Gate Scan Sequence
Based on special panel request, ILI6122 supports two kinds of gate scan sequences and illustrated as below:
GOSEQ="L" & UPDN="H" INVBRR/INVBRL="H" (Traditional Scan, For General Gate Driver)
DCMP
G1
R G B R G B R G B
Gate ON
Sequence
G2
G3
R G B R G B R G B
G4
G5
R G B R G B R G B
G6
G7
R G B R G B R G B
G8
SO1 SO2 SO3 SO4


5.4. CABC (Content Adaptive Brightness Control)
ILI61220 provides a dynamic backlight control function as CABC (Content adaptive brightness control)
to reduce the power consumption of the luminance source. ILI6122 will refer the gray scale content of display
image to output a PWM waveform to LED driver for backlight brightness control. Content adaptation means
that the content of gray sale can be increased while simultaneously lowering brightness of the backlight to
achieve the same perceived brightness. The adjusted gray level scale and thus the power consumption
reduction depend on the content of the image.
VSD S1
HSD
CLKIN RGB Interface CABC Source DAC
D0[7:0]
D1[7:0]
D2[7:0] S1200
The CABC function can be turned ON/OFF via external pin as CABC_EN and also can be configured by
software commands via SPI mode for performance optimization. IL6122 can calculate the backlight
brightness level and send a PWM pulse to LED driver via BLKEN pin for backlight brightness control purpose.
The figure in the following is the basic timing diagram which is applied ILI6122 to control LED driver.

5.5. Application Block Diagram
The configuration examples of the ILI6122 are illustrated as the following figure.
XONL
PATHL
STVU
VGGL
VGGL
VCCL
VCCL
OE3L
OE2L
OE1L
U\DL
CLKL
MODEL
(G1)
G480
(G2) G479 VEEL
G478 VGGL
VCCL
MODEL
GNDL
ILI5480
GNDR
MODER
VCCR
VGGR
VEER
G3
Display area G2
G1
(G479)
Top view
MODER
PATHR
VGGR
VGGR
XONR
VCCR
VCCR
(G480)
OE3R
OE2R
OE1R
CLKR
STVV
U\DR
Display
1200(dot) Xarea
960
Top view
1200 dot X 960
XONL
OE3L
OE2L
OE1L
U\DL
CLKL
PATHL
STVU
VGGL
VGGL
VCCL
VCCL
MODEL
(G1) G480
(G2) G479
G478
VEEL
VGGL
VCCL
MODEL
GNDL
ILI5480
GNDR
1200CH
MODER
VCCR
VGGR
G3 VEER
(G479) G2
(G480) G1
MODER
PATHR
VGGR
VGGR
XONR
VCCR
VCCR
OE3R
OE2R
OE1R
CLKR
STVR
U\DR
S1199
S1200
S1
S2
SHIELDING
SHIELDING
SHIELDING
SHIELDING
COM1_R
COM1_L
DCMPR
DCMPL
S1198
S1199
S1200
S0
S1
S2
INVBRR INVBRL
OEVR OEVL
UDR UDL
UDR CKVL
CKVR STV1L
STV1R
STV2R
ILI6122 STV2L
STV1L
STV1R STBNL
STBNR DUML
DUMR
SHIELDING
SHIELDING
SHIELDING
SHIELDING
SHIELDING
SHIELDING
SHIELDING
COM2_B
COM1_B
DASHD
VDDA
AGND
DRV
FB
PWM_EN
CABC_EN
VCOM
VCOM
GOSEQ
VCOM
VCOM
STBYB
VEE
VEE
AGND
BLKEN
VCC
VCC
GND
GND
D2[7:0]
D1[7:0]
VGG
VGG
DITHB
MODE
RSTB
UPDN
INVSEL
CLKPOL
D0[7:0]
CSX
DGND
AGND
SCL
SHLR
RES0
BIST
VSET
SDA
VDDA
DBC/3
CLKIN
VDD
HSD
DEN
VSD
V14
V1
V2

S1
S2
UDR
UDR
CKVR
OEVR
STV1R
STV2R
STV1R
DUMR
VCOM
STBNR
INVBRR
VCOM
SHIELDING
DCMPR
COM1_B SHIELDING
SHIELDING COM1_R
AGND SHIELDING
SHIELDING
FB
SHIELDING
DRV
AGND S0
S1
INVSEL S2
CABC_EN
PWM_EN
CSX
SCL
SDA
GOSEQ
BIST
RES0
DBC/3
CLKPOL
DITHB
MODE
SHLR
UPDN 1200CH
STBYB
RSTB
ILI6122
BLKEN
VSET
V1
V2
Top view
Display area
1200(dot) X 960
V14
AGND
DGND
VDD
VSD S1198
HSD S1199
S1200
DEN
CLKIN
D2[7:0]
D1[7:0]
D0[7:0] DASHD DCMPL
VDDA SHIELDING SHIELDING
VDDA COM1_L
SHIELDING SHIELDING
COM2_B
SHIELDING
Page 22 of 57
STV1L
STV2L
STV1L
UDL
CKVL
OEVL
DUML
STBNL
INVBRL
VGG
VGG
VCC
VC
VEE
VEE
GND
GND
VCOM
VCOM
S1199
S1200
(G960)
(G959)
(G2)
(G1)
G2
G1
G959
G960
TFT LCD SOURCE DRIVER WITH TCON
XON …………………… XON

OE OE
RL RL
CPV CPV
PASS PASS
STVR STVL
SEL ILI5960 SEL
VGH VGH
VDD VDD
VEE VEE
VSS VSS
………………
MODE0
MODE1
MODE1
MODE0
ILI6122
Version: 0.08
5.6. Display Data Input Timing
5.6.1. Vertical Input Timing
ILI6122 provides two different interface modes, SYNC mode and DE mode. Both modes can be selected
by MODE pin, ILI6122 will enter the SYNC mode while MODE pin is set to ‘L” and enter DE mode while
MODE pin is set t “H”.
5.6.2. Horizontal Input Timing
5.6.2.1. SYNC Mode (MODE=”L”)

ILI6122 will enter SYNC mode while MODE pin is fixed at “L” level. Every HSD period is consists of
Horizontal Back Porch, Active Area and Horizontal Front Porch time. The first active display data is
transmitted at the first falling/rising edge of CLKIN after Horizontal Back Porch period and the last display data
is transmitted at the last falling/rising edge of CLKIN before Horizontal Front Porch period.
ILI6122 will latch the display data on Dx[7:0] bus at falling edge of CLKIN when CLKPOL is set to “L”, the
input data timing is illustrated as below:

ILI6122 will latch the display data on Dx[7:0] bus at rising edge of CLKIN when CLKPOL is set to “H”, the input
data timing is illustrated as below:
5.6.2.2. DE Mode (MODE=”H”)

ILI6122 will enter DE mode while MODE pin is fixed at “H” level. ILI6122 will treat the data on Dx[7:0] bus as
active display data while DEN is at “H” level and ignore the data on Dx[7:0] bus while DEN is at “L” level.
H Pulse Width(tPW)
HSD
DEN
CLKIN
0 1 2 3 4 5 6 7 8 9 791 792 793 794 795 796 797 798 799
D0[7:0] R R R R R R R R R R R R R R R R R R R
D1[7:0] G G G G G G G G G G G G G G G G G G G
D2[7:0] B B B B B B B B B B B B B B B B B B B
H. Back Porch Active Area (tHD) H. Front Porch
Totale Area (tH)

5.7. Relationship between gamma correction and output voltage
The output voltage is determined by the 6-bit digital input data, and the V1 ~ V14 gamma correction
reference voltage inputs. The figure in the following shows the relationship between the input data and the
output voltage. Refer the next page for the relative values and voltage calculation method.
Gamma correction characteristic curve:
Note : VDDA−0.1 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 ≥ V6 ≥ V7 ≥ V8 ≥ V9 ≥ V10 ≥ V11 ≥ V12 ≥ V13 ≥ V14 ≥ AGND+0.1

The internal Gamma Table is shown as below. (VSET=“L”)
Display Data (Hex) Positive Polarity Negative Polarity VDDA=10.4V
00h VDDA x 0.961 VDDA x 0.019 VGMA Code Voltage
01h VDDA x 0.937 VDDA x 0.045 V1 00h 9.99 V
02h VDDA x 0.903 VDDA x 0.081 V2 01h 9.74 V
03h VDDA x 0.880 VDDA x 0.106 V3 10h 8.06 V
04h VDDA x 0.861 VDDA x 0.126 V4 20h 7.62 V
05h VDDA x 0.847 VDDA x 0.142 V5 30h 7.32 V
06h VDDA x 0.836 VDDA x 0.155 V6 3Eh 6.91 V
07h VDDA x 0.826 VDDA x 0.166 V7 3Fh 6.28 V
08h VDDA x 0.818 VDDA x 0.176 V8 3Fh 5.09 V
09h VDDA x 0.810 VDDA x 0.184 V9 3Eh 4.40 V
0Ah VDDA x 0.804 VDDA x 0.192 V10 30h 3.47 V
0Bh VDDA x 0.798 VDDA x 0.199 V11 20h 2.96 V
0Ch VDDA x 0.793 VDDA x 0.205 V12 10h 2.36 V
0Dh VDDA x 0.788 VDDA x 0.211 V13 01h 0.47 V
0Eh VDDA x 0.783 VDDA x 0.217 V14 00h 0.198 V
0Fh VDDA x 0.779 VDDA x 0.222
10h VDDA x 0.775 VDDA x 0.227
11h VDDA x 0.772 VDDA x 0.231
12h VDDA x 0.768 VDDA x 0.236
13h VDDA x 0.765 VDDA x 0.240
14h VDDA x 0.762 VDDA x 0.244
15h VDDA x 0.759 VDDA x 0.248
16h VDDA x 0.757 VDDA x 0.252
17h VDDA x 0.754 VDDA x 0.256
18h VDDA x 0.751 VDDA x 0.259
19h VDDA x 0.749 VDDA x 0.263
1Ah VDDA x 0.746 VDDA x 0.266
1Bh VDDA x 0.744 VDDA x 0.269
1Ch VDDA x 0.742 VDDA x 0.272
1Dh VDDA x 0.740 VDDA x 0.276
1Eh VDDA x 0.737 VDDA x 0.279
20h VDDA x 0.733 VDDA x 0.285
21h VDDA x 0.731 VDDA x 0.288
22h VDDA x 0.729 VDDA x 0.291
23h VDDA x 0.728 VDDA x 0.294
24h VDDA x 0.726 VDDA x 0.297
25h VDDA x 0.724 VDDA x 0.300
26h VDDA x 0.721 VDDA x 0.302
27h VDDA x 0.719 VDDA x 0.305
28h VDDA x 0.717 VDDA x 0.308
29h VDDA x 0.716 VDDA x 0.311
30h VDDA x 0.704 VDDA x 0.334
31h VDDA x 0.702 VDDA x 0.337
32h VDDA x 0.700 VDDA x 0.340
33h VDDA x 0.698 VDDA x 0.344
34h VDDA x 0.697 VDDA x 0.349
35h VDDA x 0.695 VDDA x 0.353
36h VDDA x 0.693 VDDA x 0.358
37h VDDA x 0.692 VDDA x 0.363
38h VDDA x 0.690 VDDA x 0.368
39h VDDA x 0.688 VDDA x 0.374

5.8. Power ON/OFF Sequence
To prevent the device damage from latch up, the power ON/OFF sequence shown below must be followed.
Power ON: VDD, DGNDÆ VDDA, AGND Æ V1 to V14
Power OFF: V1 to V14 Æ VDDA, AGNDÆ VDD, DGND
In order to prevent ILI6122 from power ON reset fail, the rising time (tPOR) of the digital power supply
VDD should be maintained within given specifications. The power ON/OFF timing sequence is illustrated as
below:
>16ms
Power ON Sequence Power OFF Sequence
VDD
TPOR<20ms
VDDA
tRST>10us
RSTB
STBYB
tDELAY>1us
1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 4 5 6 7 8
VSD
4 VSD 3 VSD 4 VSD
Source
00h Normal Display 00h 3Fh
Output
BLKEN Enable Disable

10VSD
(Output)
Note: For prevent anormal operation, tRST must be longer than 10us during Power ON sequence.

5.9. Standby ON/OFF Control
ILI6122 supports Standby mode for saving power consumption, the source driver will turn off and all
source output channel will be Hi-Z state when chip in Standby mode. The Standby mode can be controlled via
STBYB pin and the Standby ON/FF timing sequence is illustrated as below:

5.10. The BIST Patterns for Aging Mode Test
ILI6122 supports the function to generate BIST patterns for Aging mode test automatically. When
external BIST pin goes “H” level, then ILI6122 will leave Normal operation mode and starts to generate the
BIST patterns to LCD panel without external clock signal, The BIST patterns is illustrated as below:
1 2 3 4
Red Green Blue Black
5 6 7 8
White Vertical 8-color stripe Horizontal 64-gray scale Vertical 64-gray scale
9 10 11 12
Gray with black block Gray with black dot Gray with black line Black with white frame

5.11. The Command Format for 3-line Serial Interface
ILI6122 using the 3-line serial port as communication interface for all the commands and parameters of
CABC function. This 3-line serial communication can be bi-directional controlled by the “R/W” bit in address
field. Under read mode, the 3-line engine in ILI6122 will return the data during “Data phase”. The returned
data should be latched at the rising edge of SPCK by external controller. Data in the “Hi-Z phase” will be
ignored by 3-line engine during write operation, and should be ignored during read operation also. During
read operation, external controller should float SPDA pin under “Hi-Z phase” and “Data phase”.
Each Read/Write operation should be exactly 17 bit. To prevent from incorrect setting of the internal register,
any write operation with more or less than 17 bit data during a CSX Low period will be ignored by 3-line
engine.
The timing diagram of read/write operation is illustrated as below:

5.12. Command List
Command Function D/C R/W D7 D6 D5 D4 D3 D2 D1 D0 Hex

0 0 0 1 0 1 0 0 0 1 51h
Write Display Brightness Value
1 0 DBV[7:0] XX
0 0 0 1 0 1 1 0 0 0 52h
Read Display Brightness Value
1 1 DBV[7:0] XX
0 0 0 1 0 1 0 0 1 1 53h
Write CTRL Display
1 0 0 0 BCTRL 0 DD BL 0 0 XX
0 0 0 1 0 1 0 1 0 0 54h
Read CTRL Display
1 1 0 0 BCTRL 0 DD BL 0 0 XX
0 0 1 0 0 0 0 0 1 0 82h
Write Content Adaptive Brightness Control
1 0 0 0 C[1:0] 0 0 0 0 XX
0 0 1 0 0 0 0 0 1 0 82h
Read Content Adaptive Brightness Control
1 1 0 0 C[1:0] 0 0 0 0 XX
0 0 0 1 0 1 1 1 1 0 5Eh
Write CABC Minimum Brightness
1 0 CMB[7:0] XX
0 0 0 1 0 1 1 1 1 1 5Fh
Read CABC Minimum Brightness
1 1 CMB[7:0] XX
0 0 0 1 1 0 0 0 0 0 60h
CABC Control 1
1 0 PWM_DIV[7:0] XX
0 0 0 1 1 0 0 0 0 1 61h
CABC Control 2
1 0 THRES_MOV[3:0] THRES_STILL[3:0] XX
0 0 0 1 1 0 0 0 1 0 62h
CABC Control 3
1 0 0 0 0 0 THRES_UI[3:0] XX
0 0 0 1 1 0 0 0 1 1 63h
CABC Control 4
1 0 DTH_MOV[3:0] DTH_STILL[3:0] XX
0 0 0 1 1 0 0 1 0 0 64h
CABC Control 5
1 0 0 0 0 0 DTH_UI[3:0] XX
0 0 0 1 1 0 0 1 0 1 65h
CABC Control 6
1 0 DIM_OPT2[3:0] DIM_OPT1[2:0] XX
Register Default Value Table

Command Function Address Default
Display Brightness Value 52h FFh
CTRL Display 54h 2Ch
Content Adaptive Brightness Control 82h 20h
CABC Minimum Brightness 5Fh 00h
CABC Control 1 60h 12h
CABC Control 2 61h B8h
CABC Control 4 63h C9h
Note : 1. These commands above can be transmitted from host to driver IC via 3-line SPI mode only.
2. When D/C in the table above is ‘0’, it means the data on SDA/DBCM[1] pin is treated as
“Command” and the data is treated as “Parameter” when D/C is set to ‘1’.
3. When R/W in the table above is ‘0’, it means the “Write” operation is executed and the “Read”
operation is executed when R/W is set to ‘1’

5.13. Command Description
5.13.1. Write Display Brightness Value (51h)

51h WRDISBV (Write Display Brightness)
D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 0 1 0 0 0 1 51h
Parameter DBV[7:0] XX
This command is used to adjust the brightness value of the display.
DBV[7:0]: 8 bit, for display brightness of manual brightness setting and CABC in ILI6122. There is a PWM output signal,
Description
BLKEN pin, to control the LED driver IC in order to control display brightness.
5.13.2. Read Display Brightness Value (52h)

52h RDDISBV (Read Display Brightness Value)
Command 0 1 0 1 0 0 1 0 52h
Parameter DBV[7:0] XX
Default 1 1 1 1 1 1 1 1 FFh
This command is used to return the brightness value of the display.
DBV[7:0] is ‘0’ when bit BCTRL of “Write CTRL Display Value (53h)” command is ‘0’.
DBV[7:0] is manual set brightness specified with “Write CTRL Display Value (53h)” command when BCTRL bit is ‘1’.
Description
When bit BCTRL of “Write CTRL Display Value (53h)” command is ‘1’ and C1/C0 bit of “Write Content Adaptive Brightness
Control Value (55h)” command are ‘0’, DBV[7:0] output is the brightness value specified with “ Write Display Brightness
Value (51h)” command.
5.13.3. Write CTRL Display Value (53h)

53h WRCTRLD (Write Control Display)
Command 0 1 0 1 0 0 1 1 53h
Parameter X X BCTRL X DD BL X X XX
This command is used to control display brightness.
BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness for display.
BCTRL Description
0 Brightness Control Block OFF (DBV[7:0]=00h)
1 Brightness Control Block ON (DBV[7:0] is active)
DD: Display Dimming Control. This function is only for manual brightness setting.
Description
DD Description
0 Display Dimming OFF
1 Display Dimming ON

BL: Backlight Control On/Off
BL Description
0 Backlight Control OFF
1 Backlight Control ON
Dimming function is adapted to the brightness registers for display when bit BCTRL is changed at DD=1, e.g. BCTRL: 0 ->
1 or 1-> 0.
When BL bit change from “On” to “Off”, backlight is turned off without gradual dimming, even if dimming-on (DD=1) are
selected.
X = Don’t care
5.13.4. Read CTRL Display Value (54h)

54h RDCTRLD (Read Control Display Value)
Command 0 1 0 1 0 1 0 0 54h
Parameter X X BCTRL X DD BL X X XX
Default 0 0 1 0 1 1 0 0 2Ch
This command is used to control display brightness.
BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness for display.
BCTRL Description
0 Brightness Control Block OFF (DBV[7:0]=00h)
1 Brightness Control Block ON (DBV[7:0] is active)
DD: Display Dimming Control. This function is only for manual brightness setting.
Description DD Description
0 Display Dimming OFF
1 Display Dimming ON
BL: Backlight Control On/Off
BL Description
0 Backlight Control OFF
1 Backlight Control ON
X = Don’t care
5.13.5. Write Content Adaptive Brightness Control Value (82h)

55h WRCABC (Write Content Adaptive Brightness Control)
Command 1 0 0 0 0 0 1 0 82h
Parameter X X C[1:0] X X 0 0 XX
This command is used to set parameters for image content based adaptive brightness control functionality.
There is possible to use 4 different modes for content adaptive image functionality, which are defined on a table below.
C[1:0] Description
Description 0 0 CABC OFF
0 1 User Interface Image
1 0 Still Picture
1 1 Moving Image
X = Don’t care

5.13.6. Read Content Adaptive Brightness Control Value (82h)
56h RDCABC (Read Content Adaptive Brightness Control)
Command 1 0 0 0 0 0 1 0 82h
Parameter X X C[1:0] X X 0 0 XX
Default 0 0 1 0 0 0 0 0 20h
This command is used to read the settings for image content based adaptive brightness control functionality. There is
possible to use 4 different modes for content adaptive image functionality which are defined on the table below.
C[1:0] Description
Description 0 0 CABC OFF
0 1 User Interface Image
1 0 Still Picture
1 1 Moving Image
X = Don’t care
5.13.7. Write CABC Minimum Brightness (5Eh)

5Eh WRCABCMB (Write CABC Minimum Brightness)
Command 0 1 0 1 1 1 1 0 5Eh
Parameter CMB[7:0] XX
This command is used to set the minimum brightness value of the display for CABC function.
CMB[7:0]: CABC minimum brightness control, this parameter is used to avoid too much brightness reduction.
When CABC is active, CABC can not reduce the display brightness to less than CABC minimum brightness setting. Image
processing function is worked as normal, even if the brightness can not be changed.
This function does not affect to the other function, manual brightness setting. Manual brightness can be set the display
Description
brightness to less than CABC minimum brightness. Smooth transition and dimming function can be worked as normal.
When display brightness is turned off (BCTRL=0 of “Write CTRL Display (53h)”), CABC minimum brightness setting is
ignored.
In principle relationship is that 00h value means the lowest brightness for CABC and FFh value means the highest
brightness for CABC.
5.13.8. Read CABC Minimum Brightness (5Fh)

5Fh RDCABCMB (Read CABC Minimum Brightness)
Command 0 1 0 1 1 1 1 1 5Fh
Parameter CMB[7:0] XX
Default 0 0 0 0 0 0 0 0 00h
This command returns the minimum brightness value of CABC function.
In principle the relationship is that 00h value means the lowest brightness and FFh value means the highest
Description
brightness.
CMB[7:0] is CABC minimum brightness specified with “Write CABC minimum brightness (5Eh)” command.

5.13.9. CABC Control 1 (60h)
60h CABCCTRL1 (CABC Control 1)
Command 0 1 1 0 0 0 0 0 60h
Parameter PWM_DIV[7:0] XX
Default 0 0 0 1 0 0 1 0 12h
PWM_DIV[7:0]: BLKEN output period control. This command is used to adjust the PWM waveform period of BLKEN. The PWM
period can be calculated using the equation in the following.
6MHz
f BLKEN =
(PWM_DIV[7 : 0] + 1) × 255
PWM_DIV[7:0]
FBLKEN_
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 25.53KHz
0 0 0 0 0 0 0 1 11.76KHz
0 0 0 0 0 0 1 0 7.84KHz
0 0 0 0 0 0 1 1 5.88KHz
0 0 0 0 0 1 0 0 4.71KHz
:
:
0 0 0 1 0 0 1 0 1.24KHz
Description :
:
1 1 1 1 1 0 1 1 93.37
1 1 1 1 1 1 0 0 93.00
1 1 1 1 1 1 0 1 92.64
1 1 1 1 1 1 1 0 92.27
1 1 1 1 1 1 1 1 91.91
BLKEN
Note : The output frequency tolerance of internal frequency divider in BLKEN pin is ±10%

Command 0 1 1 0 0 0 0 1 61h
Parameter THRES_MOV[3:0] THRES_STILL[3:0] XX
Default 1 0 1 1 1 0 0 0 B8h
THRES_MOV[3:0]: This parameter is used to set the ratio (percentage) of the maximum number of pixels that makes
display image white (data=”63) to the total of pixels by image process in MOVING image mode. After this parameter sets
the number of pixels that makes display image white, threshold grayscale value (DTH) that makes display image white is
set so that the number of the pixels set by this parameter does not change.
THRES_MOV[3:0] THRES_MOV[3:0]
Description Description
D3 D2 D1 D0 D3 D2 D1 D0
0 0 0 0 99 % 1 0 0 0 84 %
0 0 0 1 98 % 1 0 0 1 82 %
0 0 1 0 96 % 1 0 1 0 80 %
0 0 1 1 94 % 1 0 1 1 78 %
0 1 0 0 92 % 1 1 0 0 76 %
0 1 0 1 90 % 1 1 0 1 74 %
0 1 1 0 88 % 1 1 1 0 72 %
0 1 1 1 86 % 1 1 1 1 70 %
THRES_STILL[3:0]: This parameter is used to set the ratio (percentage) of the maximum number of pixels that makes
display image white (data=”63) to the total of pixels by image process in STILL mode. After this parameter sets the number
of pixels that makes display image white, threshold grayscale value (DTH) that makes display image white is set so that
the number of the pixels set by this parameter does not change.
Description THRES_STILLI[3:0] THRES_STILL[3:0]

D3 D2 D1 D0 D3 D2 D1 D0
0 0 0 0 99 % 1 0 0 0 84 %
0 0 0 1 98 % 1 0 0 1 82 %
0 0 1 0 96 % 1 0 1 0 80 %
0 0 1 1 94 % 1 0 1 1 78 %
0 1 0 0 92 % 1 1 0 0 76 %
0 1 0 1 90 % 1 1 0 1 74 %
0 1 1 0 88 % 1 1 1 0 72 %
0 1 1 1 86 % 1 1 1 1 70 %

Command 0 1 1 0 0 0 1 0 62h
Parameter 0 0 0 0 THRES_UI[3:0] XX
Default 0 0 0 0 0 1 0 0 04h
THRES_UI[3:0]: This parameter is used to set the ratio (percentage) of the maximum number of pixels that makes display
image white (data=”63) to the total of pixels by image process in USER INTERFACE mode. After this parameter sets the
number of pixels that makes display image white, threshold grayscale value (DTH) that makes display image white is set
so that the number of the pixels set by this parameter does not change.
THRES_UI[3:0] THRES_UI[3:0]
D3 D2 D1 D0 D3 D2 D1 D0
0 0 0 0 99 % 1 0 0 0 84 %
0 0 0 1 98 % 1 0 0 1 82 %
0 0 1 0 96 % 1 0 1 0 80 %
0 0 1 1 94 % 1 0 1 1 78 %
0 1 0 0 92 % 1 1 0 0 76 %
0 1 0 1 90 % 1 1 0 1 74 %
0 1 1 0 88 % 1 1 1 0 72 %
Description 0 1 1 1 86 % 1 1 1 1 70 %

Command 0 1 1 0 0 0 1 1 63h
Parameter DTH_MOV[3:0] DTH_STILL[3:0] XX
Default 1 1 0 0 1 0 0 1 C9h
DTH_MOV[3:0]: This parameter is used set the minimum limitation of grayscale threshold value in MOVING image mode.
DTH_MOV[3:0] DTH_MOV[3:0]
D3 D2 D1 D0 D3 D2 D1 D0
0 0 0 0 224 1 0 0 0 192
0 0 0 1 220 1 0 0 1 188
0 0 1 0 216 1 0 1 0 184
0 0 1 1 212 1 0 1 1 180
0 1 0 0 208 1 1 0 0 176
0 1 0 1 204 1 1 0 1 172
0 1 1 0 200 1 1 1 0 168
0 1 1 1 196 1 1 1 1 164
DTH_OPT[2:0]: This parameter is used to set the minimum limitation of grayscale threshold value in STILL image mode.
DTH_STILLI[3:0] DTH_STILL[3:0]
D3 D2 D1 D0 D3 D2 D1 D0
0 0 0 0 224 1 0 0 0 192
0 0 0 1 220 1 0 0 1 188
Description 0 0 1 0 216 1 0 1 0 184
0 0 1 1 212 1 0 1 1 180
0 1 0 0 208 1 1 0 0 176
0 1 0 1 204 1 1 0 1 172
0 1 1 0 200 1 1 1 0 168
0 1 1 1 196 1 1 1 1 164

Command 0 1 1 0 0 1 0 0 64h
Parameter 0 0 0 0 DTH_UI[3:0] XX
Default 0 0 0 0 0 1 0 0 04h
DTH_UI[3:0]: This parameter is used set the minimum limitation of grayscale threshold value in USER INTERFACE mode.
DTH_UI[3:0] DTH_UI[3:0]
D3 D2 D1 D0 D3 D2 D1 D0
0 0 0 0 252 1 0 0 0 220
0 0 0 1 248 1 0 0 1 216
0 0 1 0 244 1 0 1 0 212
0 0 1 1 240 1 0 1 1 208
0 1 0 0 236 1 1 0 0 2-4
0 1 0 1 232 1 1 0 1 200
0 1 1 0 228 1 1 1 0 196
0 1 1 1 224 1 1 1 1 192
Description

Command 0 1 1 0 0 1 0 1 65h
Parameter DIM_OPT2[3:0] 0 DIM_OPT1[2:0] XX
Default 0 1 1 1 0 0 1 1 73h
DIM_OPT1[2:0]: This parameter is used set the transition time of brightness level change to avoid the sharp brightness
change on vision.
DIM_OPT1[2:0]
Description
D2 D1 D0
0 0 0 1 frame
0 0 1 1 frame
0 1 0 2 frames
Description
0 1 1 4 frames
1 0 0 8 frames
1 0 1 16 frames
1 1 0 32 frames
1 1 1 64 frames
DIM_OPT2[3:0]: This parameter is used to set the imitation of minimum brightness change. If this parameter is large than
the difference between target brightness and current brightness, then the brightness will not change.

6. DC Characteristic
6.1. Absolute Maximum Rating (DGND = AGND=0V, Ta=25℃)
Spec
Parameter Symbol Unit
Min. Typ. Max.
Power supply voltage 1 VDD -0.5 -- +5.0 V
Power supply voltage 2 VDDA -0.5 -- +13.5 V
Gamma correction voltage V1 ~ V14 -0.5 -- +13.5 V
Input voltage Vin 0 -- VDD+0.3 V
Operation temperature TOPR -20 -- +85 °C
Storage temperature TSTG -55 -- +125 °C
Note: (1) All of the voltages listed above are with respective to DGND=AGND=0V.
(2) Device is subject to be damaged permanently if stresses beyond those absolute maximum ratings listed above.
6.2. DC Electrical Characteristics (DGND=AGND=0V, Ta=25℃)

Spec
Parameter Symbol Unit Conditions
Min. Typ. Max.
Power supply voltage VDD 3.0 3.3 3.6 V
Power supply voltage VDDA 6.5 10.4 13.5 V
Low level input voltage VIL 0 -- 0.3VCC V For the digital circuit block
High level input voltage VIH 0.7VDD -- VCC V For the digital circuit block
Output low voltage VOL -- -- GND+0.4 V IOL=+400μA
Output high voltage VOH VDD-0.4 -- -- V IOH=-400μA
Input leakage current IIN -- -- ±1 μA No pull up or pull down.
Input level of V1~V7 VREF1 0.4VDDA -- VDDA-0.1 V Gamma correction voltage input
Input level of V8~V14 VREF2 0.1 -- 0.6VDDA V Gamma correction voltage input
VO=AGND+0.1V ~ AGND+0.5V and
Output voltage deviation VOD1 -- ±20 ±35 mV
VO=VDDA-0.1V ~ VDDA-0.5V
Output voltage deviation VOD2 -- ±15 ±20 mV VO= AGND+0.5V ~ VDDA-0.5V
DC offset VOS ±20 mV VO= AGND+0.5V ~ VDDA-0.5V
Dynamic output range VDR 0.1 -- AVDD-0.1 V S1 ~ S1200
Pull high/low resistance RH 200 250 300 kΩ For digital input pins at VDD=3.3V
Output sinking current IOL 80 -- -- μA S1~S1200, VO =0.1V vs. 1.0V, VDDA=13.5V
Output driving current IOH 80 -- -- μA S1~S1200, VO=13.4V vs. 12.5V, VDDA=13.5V
Without loading, FCLK=50MHz, FLD=48kHz,
Analog operating current IDDA -- 10 12 mA
VDDA=10V, V1=8V, V14=0.4V
Digital operating current IDD -- 8 10 mA FCLK=50MHz, FLD=48kHz, VDD=3.3V
Analog standby current ISTBA -- 10 50 μA No loading, clock and all functions are stopped
Digital standby current ISTBD -- 10 50 μA Clock and all functions are stopped
Note: VDD=3.0 ~ 3.6V, VDDA=6.5~13.5V, DGND=AGND=0V, Ta=-20~+85℃

7. AC Characteristics
7.1. AC Timing characteristics
SYNC Mode (MODE=‘0’)
CLKIN 70%
(CLKPOL=‘1’)
tVST tVHD
VSD
30% 30%
tHHD
HSD
30% 30% 30%
tHST
tH

Vertical Timing Diagram of DE Mode (Dual Gate)
Line Line Line Line Line

DEN
1 2 3 N-1 N
Dx[7:0] 1 2 3 N-1 N
Internal DE falling to internal VSD

VSD DE falling to internal HSD = 2 CLKINs = 2048 CLKINs
Internal
HSD
STV TSTV=User Define
CLKV
OEV

Spec
Min. Typ. Max.
VDD Power ON slew rate tPOR -- -- 20 ms 0V ~ 0.9VDD
RSTB pulse width tRST 10 -- -- us CLKIN=50MHz
CLKIN cycle time tCPH 20 -- -- ns
CLKIN pulse duty tCWH 40 50 60 %
VSD setup time tVST 8 -- -- ns
VSD hold time tVHD 8 -- -- ns
HSD setup time tHST 8 -- -- ns
HSD hold time tHHD 8 -- -- ns
Data setup time tDST 8 -- -- ns D0[7:0], D1[7:0], D2[7:0] to CLKIN
Data hold time tDHD 8 -- -- ns D0[7:0], D1[7:0], D2[7:0] to CLKIN
DE setup time tEST 8 -- -- ns
DE hold time tEHD 8 -- -- ns
10% to 90% target voltage.
Output stable time tSST -- -- 6 us
CL=120pF, R=10KΩ
CLKIN frequency fCLK -- 40 50 MHz VDD=3.0 ~ 3.6V
CLKIN cycle time tCLK 20 25 -- ns
CLKIN pulse duty tCWH 40 50 60 % TCLK
Time from HSD to Source output tHSO -- 20 -- CLKIN
Time from HSD to LD tHLD -- 20 -- CLKIN Note (2)
Time from HSD to STV tHSTV -- 2 -- CLKIN
Time from HSD to CKV tHCKV -- 20 -- CLKIN
Time from HSD to OEV tHOEV -- 4 -- CLKIN
LD pulse width tWLD -- 10 -- CLKIN Note (2)
CKV pulse width tWCKV -- 66 -- CLKIN
OEV pulse width tWOEV -- 74 -- CLKIN
Note: (1) VDD=3.0 ~ 3.6V, VDDA=6.5~13.5V, DGND=AGND=0V, Ta=-20~+85℃
(2) The contents of the data register are transferred to the latch circuit at the rising edge of LD. Then the
gray scale voltage is output from the device at the falling edge of LD.
(3) Output loading condition :

Spec
Min. Typ. Max.
SCL period TCK 60 -- -- ns
SCL high width TCKH 30 -- -- ns
SCL low width TCKL 30 -- -- ns
Data setup time TSU1 12 -- -- ns
Data hold time THD1 12 -- -- ns
CSX to SCL setup time TCS 20 -- -- ns
CSX to SDA hold time TCE 20 -- -- ns
CSX high pulse width TCD 50 -- -- ns

7.2. Display Timing characteristics
7.2.1. Resolution: 800x480

H Pulse Width(tHPW)
HSD
DE
CLKIN
0 1 2 3 4 5 6 7 8 9 791 792 793 794 795 796 797 798 799
H. Back Porch (tHBP) Active Area (tHD) H. Front Porch (tHFP)
Totale Area (tH)
Horizontal Input Timing

Value
Min. Typ. Max.
Horizontal display area tHD -- 800 -- CLKIN
CLKIN frequency fCLK -- 33.3 50 MHz
1 Horizontal line period tH 862 1056 1200 CLKIN
Min. -- 1 -- CLKIN
HSD pulse
Typ. tHPW -- -- -- CLKIN
width
Max. -- 40 -- CLKIN
HSD back
SYNC tHBP 46 46 46 CLKIN
porch
HSD front
SYNC tHFP 16 210 354 CLKIN
porch

Vertical Input Timing

Value
Min. Typ. Max.
Vertical display area tVD -- 480 -- HSD
VSD period time tV 510 525 650 HSD
VSD pulse width tVPW 1 -- 20 HSD
VSD back porch tVBP 23 23 23 HSD
VSD front porch tVFP 7 22 147 HSD

7.2.2. Resolution: 800x600
H Pulse Width(tHPW)
HSD
DE
CLKIN
0 1 2 3 4 5 6 7 8 9 791 792 793 794 795 796 797 798 799
H. Back Porch (tHBP) Active Area (tHD) H. Front Porch (tHFP)
Totale Area (tH)
Horizontal Input Timing

Value
Min. Typ. Max.
Horizontal display area tHD -- 800 -- CLKIN
CLKIN frequency fCLK -- 40 50 MHz
1 Horizontal line period tH 862 1056 1200 CLKIN
Min. -- 1 -- CLKIN
HSD pulse
Typ. tHPW -- -- -- CLKIN
width
Max. -- 40 -- CLKIN
HSD back
SYNC tHBP 46 46 46 CLKIN
porch
HSD front
SYNC tHFP 16 210 354 CLKIN
porch
Vertical Input Timing

Value
Min. Typ. Max.
Vertical display area tVD -- 600 -- HSD
VSD period time tV 624 635 700 HSD
VSD pulse width tVPW 1 -- 20 HSD
VSD back proch tVBP 23 23 23 HSD
VSD front porch tVFP 1 12 77 HSD

8. Pad Sequence (Bump Side)

9. Pad Arrangement and Coordination
Chip size: 22578 um x 1040 um(Include 80um scribe line).

Chip height: 400 um .

No. Pad name X Y No. Pad name X Y No. Pad name X Y No. Pad name X Y
1 SHIELDING -11196.5 -408 61 DBC/3 -5950 -408 121 V4 -850 -408 181 DEN 4250 -408
2 SHIELDING -11111.5 -408 62 SHIELDING -5865 -408 122 SHIELDING -765 -408 182 DASHD 4335 -408
3 SHIELDING -11026.5 -408 63 CLKPOL -5780 -408 123 V5 -680 -408 183 CLKIN 4420 -408
4 SHIELDING -10825 -408 64 CLKPOL -5695 -408 124 V5 -595 -408 184 CLKIN 4505 -408
5 COM1_B -10710 -408 65 SHIELDING -5610 -408 125 SHIELDING -510 -408 185 DASHD 4590 -408
6 COM1_B -10625 -408 66 DITHB -5525 -408 126 V6 -425 -408 186 D27 4675 -408
7 SHIELDING -10540 -408 67 DITHB -5440 -408 127 V6 -340 -408 187 D27 4760 -408
8 SHIELDING -10455 -408 68 SHIELDING -5355 -408 128 SHIELDING -255 -408 188 D26 4845 -408
9 AGND -10370 -408 69 MODE -5270 -408 129 V7 -170 -408 189 D26 4930 -408
10 AGND -10285 -408 70 MODE -5185 -408 130 V7 -85 -408 190 DASHD 5015 -408
11 AGND -10200 -408 71 SHIELDING -5100 -408 131 SHIELDING 0 -408 191 D25 5100 -408
12 AGND -10115 -408 72 SHLR -5015 -408 132 V8 85 -408 192 D25 5185 -408
13 SHIELDING -10030 -408 73 SHLR -4930 -408 133 V8 170 -408 193 D24 5270 -408
14 FB (Reserved) -9945 -408 74 SHIELDING -4845 -408 134 SHIELDING 255 -408 194 D24 5355 -408
15 FB (Reserved) -9860 -408 75 UPDN -4760 -408 135 V9 340 -408 195 DASHD 5440 -408
16 SHIELDING -9775 -408 76 UPDN -4675 -408 136 V9 425 -408 196 D23 5525 -408
17 DRV (Reserved) -9690 -408 77 SHIELDING -4590 -408 137 SHIELDING 510 -408 197 D23 5610 -408
18 DRV (Reserved) -9605 -408 78 STBYB -4505 -408 138 V10 595 -408 198 D22 5695 -408
19 TP0 -9520 -408 79 STBYB -4420 -408 139 V10 680 -408 199 D22 5780 -408
20 TP0 -9435 -408 80 SHIELDING -4335 -408 140 SHIELDING 765 -408 200 DASHD 5865 -408
21 TP1 -9350 -408 81 RSTB -4250 -408 141 V11 850 -408 201 D21 5950 -408
22 TP1 -9265 -408 82 RSTB -4165 -408 142 V11 935 -408 202 D21 6035 -408
23 TP2 -9180 -408 83 SHIELDING -4080 -408 143 SHIELDING 1020 -408 203 D20 6120 -408
24 TP2 -9095 -408 84 BLKEN -3995 -408 144 V12 1105 -408 204 D20 6205 -408
25 TP3 -9010 -408 85 BLKEN -3910 -408 145 V12 1190 -408 205 DASHD 6290 -408
26 TP3 -8925 -408 86 SHIELDING -3825 -408 146 SHIELDING 1275 -408 206 D17 6375 -408
27 TP4 -8840 -408 87 VSET -3740 -408 147 V13 1360 -408 207 D17 6460 -408
28 TP4 -8755 -408 88 VSET -3655 -408 148 V13 1445 -408 208 D16 6545 -408
29 Dummy -8670 -408 89 TP6 -3570 -408 149 SHIELDING 1530 -408 209 D16 6630 -408
30 REV -8585 -408 90 TP6 -3485 -408 150 V14 1615 -408 210 DASHD 6715 -408
31 SHIELDING -8500 -408 91 TP7 -3400 -408 151 V14 1700 -408 211 D15 6800 -408
32 INVSEL -8415 -408 92 TP7 -3315 -408 152 SHIELDING 1785 -408 212 D15 6885 -408
33 INVSEL -8330 -408 93 TP8 -3230 -408 153 AGND 1870 -408 213 D14 6970 -408
34 SHIELDING -8245 -408 94 TP8 -3145 -408 154 AGND 1955 -408 214 D14 7055 -408
35 CABC_EN -8160 -408 95 TP9 -3060 -408 155 AGND 2040 -408 215 DASHD 7140 -408
36 CABC_EN -8075 -408 96 TP9 -2975 -408 156 AGND 2125 -408 216 D13 7225 -408
37 SHIELDING -7990 -408 97 TP10 -2890 -408 157 AGND 2210 -408 217 D13 7310 -408
38 PWM_EN (Reserved) -7905 -408 98 Dummy -2805 -408 158 AGND 2295 -408 218 D12 7395 -408
39 PWM_EN (Reserved) -7820 -408 99 DCMP_EN -2720 -408 159 AGND 2380 -408 219 D12 7480 -408
40 SHIELDING -7735 -408 100 DUMMY -2635 -408 160 AGND 2465 -408 220 DASHD 7565 -408
41 CSX -7650 -408 101 SHIELDING -2550 -408 161 SHIELDING 2550 -408 221 D11 7650 -408
42 CSX -7565 -408 102 AVDD -2465 -408 162 SHIELDING 2635 -408 222 D11 7735 -408
43 SHIELDING -7480 -408 103 AVDD -2380 -408 163 GND 2720 -408 223 D10 7820 -408
44 SCL/DBC[0] -7395 -408 104 AVDD -2295 -408 164 GND 2805 -408 224 D10 7905 -408
45 SCL/DBC[0] -7310 -408 105 AVDD -2210 -408 165 GND 2890 -408 225 DASHD 7990 -408
46 SHIELDING -7225 -408 106 AVDD -2125 -408 166 GND 2975 -408 226 D07 8075 -408
47 SDA/DBC[1] -7140 -408 107 AVDD -2040 -408 167 SHIELDING 3060 -408 227 D07 8160 -408
48 SDA/DBC[1] -7055 -408 108 AVDD -1955 -408 168 SHIELDING 3145 -408 228 D06 8245 -408
49 SHIELDING -6970 -408 109 AVDD -1870 -408 169 VDD 3230 -408 229 D06 8330 -408
50 SHIELDING -6885 -408 110 SHIELDING -1785 -408 170 VDD 3315 -408 230 DASHD 8415 -408
51 GOSEQ -6800 -408 111 V1 -1700 -408 171 VDD 3400 -408 231 D05 8500 -408
52 GOSEQ -6715 -408 112 V1 -1615 -408 172 VDD 3485 -408 232 D05 8585 -408
53 SHIELDING -6630 -408 113 SHIELDING -1530 -408 173 DASHD 3570 -408 233 D04 8670 -408
54 BIST -6545 -408 114 V2 -1445 -408 174 VSD 3655 -408 234 D04 8755 -408
55 BIST -6460 -408 115 V2 -1360 -408 175 VSD 3740 -408 235 DASHD 8840 -408
57 RES0 -6290 -408 117 V3 -1190 -408 177 HSD 3910 -408 237 D03 9010 -408
58 RES0 -6205 -408 118 V3 -1105 -408 178 HSD 3995 -408 238 D02 9095 -408
60 DBC/3 -6035 -408 120 V4 -935 -408 180 DEN 4165 -408 240 DASHD 9265 -408

241 D01 9350 -408 301 SO[16] 10365.5 128 361 SO[76] 9345.5 128 421 SO[136] 8325.5 128
242 D01 9435 -408 302 SO[17] 10348.5 268 362 SO[77] 9328.5 268 422 SO[137] 8308.5 268
243 D00 9520 -408 303 SO[18] 10331.5 408 363 SO[78] 9311.5 408 423 SO[138] 8291.5 408
244 D00 9605 -408 304 SO[19] 10314.5 128 364 SO[79] 9294.5 128 424 SO[139] 8274.5 128
245 DASHD 9690 -408 305 SO[20] 10297.5 268 365 SO[80] 9277.5 268 425 SO[140] 8257.5 268
246 SHIELDING 9775 -408 306 SO[21] 10280.5 408 366 SO[81] 9260.5 408 426 SO[141] 8240.5 408
250 AVDD 10115 -408 310 SO[25] 10212.5 128 370 SO[85] 9192.5 128 430 SO[145] 8172.5 128
251 AVDD 10200 -408 311 SO[26] 10195.5 268 371 SO[86] 9175.5 268 431 SO[146] 8155.5 268
252 AVDD 10285 -408 312 SO[27] 10178.5 408 372 SO[87] 9158.5 408 432 SO[147] 8138.5 408
253 AVDD 10370 -408 313 SO[28] 10161.5 128 373 SO[88] 9141.5 128 433 SO[148] 8121.5 128
256 COM2_B 10625 -408 316 SO[31] 10110.5 128 376 SO[91] 9090.5 128 436 SO[151] 8070.5 128
257 COM2_B 10710 -408 317 SO[32] 10093.5 268 377 SO[92] 9073.5 268 437 SO[152] 8053.5 268
259 SHIELDING 11026.5 -408 319 SO[34] 10059.5 128 379 SO[94] 9039.5 128 439 SO[154] 8019.5 128
262 DUMMY 11049 -232 322 SO[37] 10008.5 128 382 SO[97] 8988.5 128 442 SO[157] 7968.5 128
263 DUMMY 11179 -232 323 SO[38] 9991.5 268 383 SO[98] 8971.5 268 443 SO[158] 7951.5 268
264 STBNL 11049 -152 324 SO[39] 9974.5 408 384 SO[99] 8954.5 408 444 SO[159] 7934.5 408
265 STBNL 11179 -152 325 SO[40] 9957.5 128 385 SO[100] 8937.5 128 445 SO[160] 7917.5 128
266 STV1L 11049 -72 326 SO[41] 9940.5 268 386 SO[101] 8920.5 268 446 SO[161] 7900.5 268
267 STV1L 11179 -72 327 SO[42] 9923.5 408 387 SO[102] 8903.5 408 447 SO[162] 7883.5 408
268 STV2L 11049 8 328 SO[43] 9906.5 128 388 SO[103] 8886.5 128 448 SO[163] 7866.5 128
269 STV2L 11179 8 329 SO[44] 9889.5 268 389 SO[104] 8869.5 268 449 SO[164] 7849.5 268
270 STV1L 11049 88 330 SO[45] 9872.5 408 390 SO[105] 8852.5 408 450 SO[165] 7832.5 408
271 STV1L 11179 88 331 SO[46] 9855.5 128 391 SO[106] 8835.5 128 451 SO[166] 7815.5 128
272 CKVL 11049 168 332 SO[47] 9838.5 268 392 SO[107] 8818.5 268 452 SO[167] 7798.5 268
273 CKVL 11179 168 333 SO[48] 9821.5 408 393 SO[108] 8801.5 408 453 SO[168] 7781.5 408
274 UDL 11049 248 334 SO[49] 9804.5 128 394 SO[109] 8784.5 128 454 SO[169] 7764.5 128
275 UDL 11179 248 335 SO[50] 9787.5 268 395 SO[110] 8767.5 268 455 SO[170] 7747.5 268
276 OEVL 11179 328 336 SO[51] 9770.5 408 396 SO[111] 8750.5 408 456 SO[171] 7730.5 408
277 INVBRL 11179 408 337 SO[52] 9753.5 128 397 SO[112] 8733.5 128 457 SO[172] 7713.5 128
278 OEVL 11049 328 338 SO[53] 9736.5 268 398 SO[113] 8716.5 268 458 SO[173] 7696.5 268
279 INVBRL 11049 408 339 SO[54] 9719.5 408 399 SO[114] 8699.5 408 459 SO[174] 7679.5 408
280 DCMPL 10914 428 340 SO[55] 9702.5 128 400 SO[115] 8682.5 128 460 SO[175] 7662.5 128
281 DCMPL 10864 428 341 SO[56] 9685.5 268 401 SO[116] 8665.5 268 461 SO[176] 7645.5 268
282 SHIELDING 10814 428 342 SO[57] 9668.5 408 402 SO[117] 8648.5 408 462 SO[177] 7628.5 408
283 COM2_T 10764 428 343 SO[58] 9651.5 128 403 SO[118] 8631.5 128 463 SO[178] 7611.5 128
284 COM2_T 10714 428 344 SO[59] 9634.5 268 404 SO[119] 8614.5 268 464 SO[179] 7594.5 268
285 SHIELDING 10664 428 345 SO[60] 9617.5 408 405 SO[120] 8597.5 408 465 SO[180] 7577.5 408
286 SO[1] 10620.5 128 346 SO[61] 9600.5 128 406 SO[121] 8580.5 128 466 SO[181] 7560.5 128
287 SO[2] 10603.5 268 347 SO[62] 9583.5 268 407 SO[122] 8563.5 268 467 SO[182] 7543.5 268
288 SO[3] 10586.5 408 348 SO[63] 9566.5 408 408 SO[123] 8546.5 408 468 SO[183] 7526.5 408
289 SO[4] 10569.5 128 349 SO[64] 9549.5 128 409 SO[124] 8529.5 128 469 SO[184] 7509.5 128
290 SO[5] 10552.5 268 350 SO[65] 9532.5 268 410 SO[125] 8512.5 268 470 SO[185] 7492.5 268
291 SO[6] 10535.5 408 351 SO[66] 9515.5 408 411 SO[126] 8495.5 408 471 SO[186] 7475.5 408
292 SO[7] 10518.5 128 352 SO[67] 9498.5 128 412 SO[127] 8478.5 128 472 SO[187] 7458.5 128
293 SO[8] 10501.5 268 353 SO[68] 9481.5 268 413 SO[128] 8461.5 268 473 SO[188] 7441.5 268
294 SO[9] 10484.5 408 354 SO[69] 9464.5 408 414 SO[129] 8444.5 408 474 SO[189] 7424.5 408
295 SO[10] 10467.5 128 355 SO[70] 9447.5 128 415 SO[130] 8427.5 128 475 SO[190] 7407.5 128
296 SO[11] 10450.5 268 356 SO[71] 9430.5 268 416 SO[131] 8410.5 268 476 SO[191] 7390.5 268
297 SO[12] 10433.5 408 357 SO[72] 9413.5 408 417 SO[132] 8393.5 408 477 SO[192] 7373.5 408
298 SO[13] 10416.5 128 358 SO[73] 9396.5 128 418 SO[133] 8376.5 128 478 SO[193] 7356.5 128
299 SO[14] 10399.5 268 359 SO[74] 9379.5 268 419 SO[134] 8359.5 268 479 SO[194] 7339.5 268
300 SO[15] 10382.5 408 360 SO[75] 9362.5 408 420 SO[135] 8342.5 408 480 SO[195] 7322.5 408

481 SO[196] 7305.5 128 541 SO[256] 6285.5 128 601 SO[316] 5265.5 128 661 SO[376] 4245.5 128
482 SO[197] 7288.5 268 542 SO[257] 6268.5 268 602 SO[317] 5248.5 268 662 SO[377] 4228.5 268
483 SO[198] 7271.5 408 543 SO[258] 6251.5 408 603 SO[318] 5231.5 408 663 SO[378] 4211.5 408
484 SO[199] 7254.5 128 544 SO[259] 6234.5 128 604 SO[319] 5214.5 128 664 SO[379] 4194.5 128
485 SO[200] 7237.5 268 545 SO[260] 6217.5 268 605 SO[320] 5197.5 268 665 SO[380] 4177.5 268
486 SO[201] 7220.5 408 546 SO[261] 6200.5 408 606 SO[321] 5180.5 408 666 SO[381] 4160.5 408
487 SO[202] 7203.5 128 547 SO[262] 6183.5 128 607 SO[322] 5163.5 128 667 SO[382] 4143.5 128
488 SO[203] 7186.5 268 548 SO[263] 6166.5 268 608 SO[323] 5146.5 268 668 SO[383] 4126.5 268
489 SO[204] 7169.5 408 549 SO[264] 6149.5 408 609 SO[324] 5129.5 408 669 SO[384] 4109.5 408
490 SO[205] 7152.5 128 550 SO[265] 6132.5 128 610 SO[325] 5112.5 128 670 SO[385] 4092.5 128
491 SO[206] 7135.5 268 551 SO[266] 6115.5 268 611 SO[326] 5095.5 268 671 SO[386] 4075.5 268
492 SO[207] 7118.5 408 552 SO[267] 6098.5 408 612 SO[327] 5078.5 408 672 SO[387] 4058.5 408
493 SO[208] 7101.5 128 553 SO[268] 6081.5 128 613 SO[328] 5061.5 128 673 SO[388] 4041.5 128
494 SO[209] 7084.5 268 554 SO[269] 6064.5 268 614 SO[329] 5044.5 268 674 SO[389] 4024.5 268
495 SO[210] 7067.5 408 555 SO[270] 6047.5 408 615 SO[330] 5027.5 408 675 SO[390] 4007.5 408
496 SO[211] 7050.5 128 556 SO[271] 6030.5 128 616 SO[331] 5010.5 128 676 SO[391] 3990.5 128
497 SO[212] 7033.5 268 557 SO[272] 6013.5 268 617 SO[332] 4993.5 268 677 SO[392] 3973.5 268
498 SO[213] 7016.5 408 558 SO[273] 5996.5 408 618 SO[333] 4976.5 408 678 SO[393] 3956.5 408
499 SO[214] 6999.5 128 559 SO[274] 5979.5 128 619 SO[334] 4959.5 128 679 SO[394] 3939.5 128
500 SO[215] 6982.5 268 560 SO[275] 5962.5 268 620 SO[335] 4942.5 268 680 SO[395] 3922.5 268
501 SO[216] 6965.5 408 561 SO[276] 5945.5 408 621 SO[336] 4925.5 408 681 SO[396] 3905.5 408
502 SO[217] 6948.5 128 562 SO[277] 5928.5 128 622 SO[337] 4908.5 128 682 SO[397] 3888.5 128
503 SO[218] 6931.5 268 563 SO[278] 5911.5 268 623 SO[338] 4891.5 268 683 SO[398] 3871.5 268
504 SO[219] 6914.5 408 564 SO[279] 5894.5 408 624 SO[339] 4874.5 408 684 SO[399] 3854.5 408
505 SO[220] 6897.5 128 565 SO[280] 5877.5 128 625 SO[340] 4857.5 128 685 SO[400] 3837.5 128
506 SO[221] 6880.5 268 566 SO[281] 5860.5 268 626 SO[341] 4840.5 268 686 SO[401] 3820.5 268
507 SO[222] 6863.5 408 567 SO[282] 5843.5 408 627 SO[342] 4823.5 408 687 SO[402] 3803.5 408
508 SO[223] 6846.5 128 568 SO[283] 5826.5 128 628 SO[343] 4806.5 128 688 SO[403] 3786.5 128
509 SO[224] 6829.5 268 569 SO[284] 5809.5 268 629 SO[344] 4789.5 268 689 SO[404] 3769.5 268
510 SO[225] 6812.5 408 570 SO[285] 5792.5 408 630 SO[345] 4772.5 408 690 SO[405] 3752.5 408
511 SO[226] 6795.5 128 571 SO[286] 5775.5 128 631 SO[346] 4755.5 128 691 SO[406] 3735.5 128
512 SO[227] 6778.5 268 572 SO[287] 5758.5 268 632 SO[347] 4738.5 268 692 SO[407] 3718.5 268
513 SO[228] 6761.5 408 573 SO[288] 5741.5 408 633 SO[348] 4721.5 408 693 SO[408] 3701.5 408
514 SO[229] 6744.5 128 574 SO[289] 5724.5 128 634 SO[349] 4704.5 128 694 SO[409] 3684.5 128
515 SO[230] 6727.5 268 575 SO[290] 5707.5 268 635 SO[350] 4687.5 268 695 SO[410] 3667.5 268
516 SO[231] 6710.5 408 576 SO[291] 5690.5 408 636 SO[351] 4670.5 408 696 SO[411] 3650.5 408
517 SO[232] 6693.5 128 577 SO[292] 5673.5 128 637 SO[352] 4653.5 128 697 SO[412] 3633.5 128
518 SO[233] 6676.5 268 578 SO[293] 5656.5 268 638 SO[353] 4636.5 268 698 SO[413] 3616.5 268
519 SO[234] 6659.5 408 579 SO[294] 5639.5 408 639 SO[354] 4619.5 408 699 SO[414] 3599.5 408
520 SO[235] 6642.5 128 580 SO[295] 5622.5 128 640 SO[355] 4602.5 128 700 SO[415] 3582.5 128
521 SO[236] 6625.5 268 581 SO[296] 5605.5 268 641 SO[356] 4585.5 268 701 SO[416] 3565.5 268
522 SO[237] 6608.5 408 582 SO[297] 5588.5 408 642 SO[357] 4568.5 408 702 SO[417] 3548.5 408
523 SO[238] 6591.5 128 583 SO[298] 5571.5 128 643 SO[358] 4551.5 128 703 SO[418] 3531.5 128
524 SO[239] 6574.5 268 584 SO[299] 5554.5 268 644 SO[359] 4534.5 268 704 SO[419] 3514.5 268
525 SO[240] 6557.5 408 585 SO[300] 5537.5 408 645 SO[360] 4517.5 408 705 SO[420] 3497.5 408
526 SO[241] 6540.5 128 586 SO[301] 5520.5 128 646 SO[361] 4500.5 128 706 SO[421] 3480.5 128
527 SO[242] 6523.5 268 587 SO[302] 5503.5 268 647 SO[362] 4483.5 268 707 SO[422] 3463.5 268
528 SO[243] 6506.5 408 588 SO[303] 5486.5 408 648 SO[363] 4466.5 408 708 SO[423] 3446.5 408
529 SO[244] 6489.5 128 589 SO[304] 5469.5 128 649 SO[364] 4449.5 128 709 SO[424] 3429.5 128
530 SO[245] 6472.5 268 590 SO[305] 5452.5 268 650 SO[365] 4432.5 268 710 SO[425] 3412.5 268
531 SO[246] 6455.5 408 591 SO[306] 5435.5 408 651 SO[366] 4415.5 408 711 SO[426] 3395.5 408
532 SO[247] 6438.5 128 592 SO[307] 5418.5 128 652 SO[367] 4398.5 128 712 SO[427] 3378.5 128
533 SO[248] 6421.5 268 593 SO[308] 5401.5 268 653 SO[368] 4381.5 268 713 SO[428] 3361.5 268
534 SO[249] 6404.5 408 594 SO[309] 5384.5 408 654 SO[369] 4364.5 408 714 SO[429] 3344.5 408
535 SO[250] 6387.5 128 595 SO[310] 5367.5 128 655 SO[370] 4347.5 128 715 SO[430] 3327.5 128
536 SO[251] 6370.5 268 596 SO[311] 5350.5 268 656 SO[371] 4330.5 268 716 SO[431] 3310.5 268
537 SO[252] 6353.5 408 597 SO[312] 5333.5 408 657 SO[372] 4313.5 408 717 SO[432] 3293.5 408
538 SO[253] 6336.5 128 598 SO[313] 5316.5 128 658 SO[373] 4296.5 128 718 SO[433] 3276.5 128
539 SO[254] 6319.5 268 599 SO[314] 5299.5 268 659 SO[374] 4279.5 268 719 SO[434] 3259.5 268
540 SO[255] 6302.5 408 600 SO[315] 5282.5 408 660 SO[375] 4262.5 408 720 SO[435] 3242.5 408

721 SO[436] 3225.5 128 781 SO[496] 2205.5 128 841 SO[556] 1185.5 128 901 SO[604] -488.5 408
722 SO[437] 3208.5 268 782 SO[497] 2188.5 268 842 SO[557] 1168.5 268 902 SO[605] -505.5 268
723 SO[438] 3191.5 408 783 SO[498] 2171.5 408 843 SO[558] 1151.5 408 903 SO[606] -522.5 128
724 SO[439] 3174.5 128 784 SO[499] 2154.5 128 844 SO[559] 1134.5 128 904 SO[607] -539.5 408
725 SO[440] 3157.5 268 785 SO[500] 2137.5 268 845 SO[560] 1117.5 268 905 SO[608] -556.5 268
726 SO[441] 3140.5 408 786 SO[501] 2120.5 408 846 SO[561] 1100.5 408 906 SO[609] -573.5 128
727 SO[442] 3123.5 128 787 SO[502] 2103.5 128 847 SO[562] 1083.5 128 907 SO[610] -590.5 408
728 SO[443] 3106.5 268 788 SO[503] 2086.5 268 848 SO[563] 1066.5 268 908 SO[611] -607.5 268
729 SO[444] 3089.5 408 789 SO[504] 2069.5 408 849 SO[564] 1049.5 408 909 SO[612] -624.5 128
730 SO[445] 3072.5 128 790 SO[505] 2052.5 128 850 SO[565] 1032.5 128 910 SO[613] -641.5 408
731 SO[446] 3055.5 268 791 SO[506] 2035.5 268 851 SO[566] 1015.5 268 911 SO[614] -658.5 268
732 SO[447] 3038.5 408 792 SO[507] 2018.5 408 852 SO[567] 998.5 408 912 SO[615] -675.5 128
733 SO[448] 3021.5 128 793 SO[508] 2001.5 128 853 SO[568] 981.5 128 913 SO[616] -692.5 408
734 SO[449] 3004.5 268 794 SO[509] 1984.5 268 854 SO[569] 964.5 268 914 SO[617] -709.5 268
735 SO[450] 2987.5 408 795 SO[510] 1967.5 408 855 SO[570] 947.5 408 915 SO[618] -726.5 128
736 SO[451] 2970.5 128 796 SO[511] 1950.5 128 856 SO[571] 930.5 128 916 SO[619] -743.5 408
737 SO[452] 2953.5 268 797 SO[512] 1933.5 268 857 SO[572] 913.5 268 917 SO[620] -760.5 268
738 SO[453] 2936.5 408 798 SO[513] 1916.5 408 858 SO[573] 896.5 408 918 SO[621] -777.5 128
739 SO[454] 2919.5 128 799 SO[514] 1899.5 128 859 SO[574] 879.5 128 919 SO[622] -794.5 408
740 SO[455] 2902.5 268 800 SO[515] 1882.5 268 860 SO[575] 862.5 268 920 SO[623] -811.5 268
741 SO[456] 2885.5 408 801 SO[516] 1865.5 408 861 SO[576] 845.5 408 921 SO[624] -828.5 128
742 SO[457] 2868.5 128 802 SO[517] 1848.5 128 862 SO[577] 828.5 128 922 SO[625] -845.5 408
743 SO[458] 2851.5 268 803 SO[518] 1831.5 268 863 SO[578] 811.5 268 923 SO[626] -862.5 268
744 SO[459] 2834.5 408 804 SO[519] 1814.5 408 864 SO[579] 794.5 408 924 SO[627] -879.5 128
745 SO[460] 2817.5 128 805 SO[520] 1797.5 128 865 SO[580] 777.5 128 925 SO[628] -896.5 408
746 SO[461] 2800.5 268 806 SO[521] 1780.5 268 866 SO[581] 760.5 268 926 SO[629] -913.5 268
747 SO[462] 2783.5 408 807 SO[522] 1763.5 408 867 SO[582] 743.5 408 927 SO[630] -930.5 128
748 SO[463] 2766.5 128 808 SO[523] 1746.5 128 868 SO[583] 726.5 128 928 SO[631] -947.5 408
749 SO[464] 2749.5 268 809 SO[524] 1729.5 268 869 SO[584] 709.5 268 929 SO[632] -964.5 268
750 SO[465] 2732.5 408 810 SO[525] 1712.5 408 870 SO[585] 692.5 408 930 SO[633] -981.5 128
751 SO[466] 2715.5 128 811 SO[526] 1695.5 128 871 SO[586] 675.5 128 931 SO[634] -998.5 408
752 SO[467] 2698.5 268 812 SO[527] 1678.5 268 872 SO[587] 658.5 268 932 SO[635] -1015.5 268
753 SO[468] 2681.5 408 813 SO[528] 1661.5 408 873 SO[588] 641.5 408 933 SO[636] -1032.5 128
754 SO[469] 2664.5 128 814 SO[529] 1644.5 128 874 SO[589] 624.5 128 934 SO[637] -1049.5 408
755 SO[470] 2647.5 268 815 SO[530] 1627.5 268 875 SO[590] 607.5 268 935 SO[638] -1066.5 268
756 SO[471] 2630.5 408 816 SO[531] 1610.5 408 876 SO[591] 590.5 408 936 SO[639] -1083.5 128
757 SO[472] 2613.5 128 817 SO[532] 1593.5 128 877 SO[592] 573.5 128 937 SO[640] -1100.5 408
758 SO[473] 2596.5 268 818 SO[533] 1576.5 268 878 SO[593] 556.5 268 938 SO[641] -1117.5 268
759 SO[474] 2579.5 408 819 SO[534] 1559.5 408 879 SO[594] 539.5 408 939 SO[642] -1134.5 128
760 SO[475] 2562.5 128 820 SO[535] 1542.5 128 880 SO[595] 522.5 128 940 SO[643] -1151.5 408
761 SO[476] 2545.5 268 821 SO[536] 1525.5 268 881 SO[596] 505.5 268 941 SO[644] -1168.5 268
762 SO[477] 2528.5 408 822 SO[537] 1508.5 408 882 SO[597] 488.5 408 942 SO[645] -1185.5 128
763 SO[478] 2511.5 128 823 SO[538] 1491.5 128 883 SO[598] 471.5 128 943 SO[646] -1202.5 408
764 SO[479] 2494.5 268 824 SO[539] 1474.5 268 884 SO[599] 454.5 268 944 SO[647] -1219.5 268
765 SO[480] 2477.5 408 825 SO[540] 1457.5 408 885 SO[600] 437.5 408 945 SO[648] -1236.5 128
766 SO[481] 2460.5 128 826 SO[541] 1440.5 128 886 SHIELDING 403.5 408 946 SO[649] -1253.5 408
772 SO[487] 2358.5 128 832 SO[547] 1338.5 128 892 SHIELDING -233.5 408 952 SO[655] -1355.5 408
778 SO[493] 2256.5 128 838 SO[553] 1236.5 128 898 SO[601] -437.5 408 958 SO[661] -1457.5 408
779 SO[494] 2239.5 268 839 SO[554] 1219.5 268 899 SO[602] -454.5 268 959 SO[662] -1474.5 268
780 SO[495] 2222.5 408 840 SO[555] 1202.5 408 900 SO[603] -471.5 128 960 SO[663] -1491.5 128

961 SO[664] -1508.5 408 1021 SO[724] -2528.5 408 1081 SO[784] -3548.5 408 1141 SO[844] -4568.5 408
962 SO[665] -1525.5 268 1022 SO[725] -2545.5 268 1082 SO[785] -3565.5 268 1142 SO[845] -4585.5 268
963 SO[666] -1542.5 128 1023 SO[726] -2562.5 128 1083 SO[786] -3582.5 128 1143 SO[846] -4602.5 128
964 SO[667] -1559.5 408 1024 SO[727] -2579.5 408 1084 SO[787] -3599.5 408 1144 SO[847] -4619.5 408
965 SO[668] -1576.5 268 1025 SO[728] -2596.5 268 1085 SO[788] -3616.5 268 1145 SO[848] -4636.5 268
966 SO[669] -1593.5 128 1026 SO[729] -2613.5 128 1086 SO[789] -3633.5 128 1146 SO[849] -4653.5 128
967 SO[670] -1610.5 408 1027 SO[730] -2630.5 408 1087 SO[790] -3650.5 408 1147 SO[850] -4670.5 408
968 SO[671] -1627.5 268 1028 SO[731] -2647.5 268 1088 SO[791] -3667.5 268 1148 SO[851] -4687.5 268
969 SO[672] -1644.5 128 1029 SO[732] -2664.5 128 1089 SO[792] -3684.5 128 1149 SO[852] -4704.5 128
970 SO[673] -1661.5 408 1030 SO[733] -2681.5 408 1090 SO[793] -3701.5 408 1150 SO[853] -4721.5 408
971 SO[674] -1678.5 268 1031 SO[734] -2698.5 268 1091 SO[794] -3718.5 268 1151 SO[854] -4738.5 268
972 SO[675] -1695.5 128 1032 SO[735] -2715.5 128 1092 SO[795] -3735.5 128 1152 SO[855] -4755.5 128
973 SO[676] -1712.5 408 1033 SO[736] -2732.5 408 1093 SO[796] -3752.5 408 1153 SO[856] -4772.5 408
974 SO[677] -1729.5 268 1034 SO[737] -2749.5 268 1094 SO[797] -3769.5 268 1154 SO[857] -4789.5 268
975 SO[678] -1746.5 128 1035 SO[738] -2766.5 128 1095 SO[798] -3786.5 128 1155 SO[858] -4806.5 128
976 SO[679] -1763.5 408 1036 SO[739] -2783.5 408 1096 SO[799] -3803.5 408 1156 SO[859] -4823.5 408
977 SO[680] -1780.5 268 1037 SO[740] -2800.5 268 1097 SO[800] -3820.5 268 1157 SO[860] -4840.5 268
978 SO[681] -1797.5 128 1038 SO[741] -2817.5 128 1098 SO[801] -3837.5 128 1158 SO[861] -4857.5 128
979 SO[682] -1814.5 408 1039 SO[742] -2834.5 408 1099 SO[802] -3854.5 408 1159 SO[862] -4874.5 408
980 SO[683] -1831.5 268 1040 SO[743] -2851.5 268 1100 SO[803] -3871.5 268 1160 SO[863] -4891.5 268
981 SO[684] -1848.5 128 1041 SO[744] -2868.5 128 1101 SO[804] -3888.5 128 1161 SO[864] -4908.5 128
982 SO[685] -1865.5 408 1042 SO[745] -2885.5 408 1102 SO[805] -3905.5 408 1162 SO[865] -4925.5 408
983 SO[686] -1882.5 268 1043 SO[746] -2902.5 268 1103 SO[806] -3922.5 268 1163 SO[866] -4942.5 268
984 SO[687] -1899.5 128 1044 SO[747] -2919.5 128 1104 SO[807] -3939.5 128 1164 SO[867] -4959.5 128
985 SO[688] -1916.5 408 1045 SO[748] -2936.5 408 1105 SO[808] -3956.5 408 1165 SO[868] -4976.5 408
986 SO[689] -1933.5 268 1046 SO[749] -2953.5 268 1106 SO[809] -3973.5 268 1166 SO[869] -4993.5 268
987 SO[690] -1950.5 128 1047 SO[750] -2970.5 128 1107 SO[810] -3990.5 128 1167 SO[870] -5010.5 128
988 SO[691] -1967.5 408 1048 SO[751] -2987.5 408 1108 SO[811] -4007.5 408 1168 SO[871] -5027.5 408
989 SO[692] -1984.5 268 1049 SO[752] -3004.5 268 1109 SO[812] -4024.5 268 1169 SO[872] -5044.5 268
990 SO[693] -2001.5 128 1050 SO[753] -3021.5 128 1110 SO[813] -4041.5 128 1170 SO[873] -5061.5 128
991 SO[694] -2018.5 408 1051 SO[754] -3038.5 408 1111 SO[814] -4058.5 408 1171 SO[874] -5078.5 408
992 SO[695] -2035.5 268 1052 SO[755] -3055.5 268 1112 SO[815] -4075.5 268 1172 SO[875] -5095.5 268
993 SO[696] -2052.5 128 1053 SO[756] -3072.5 128 1113 SO[816] -4092.5 128 1173 SO[876] -5112.5 128
994 SO[697] -2069.5 408 1054 SO[757] -3089.5 408 1114 SO[817] -4109.5 408 1174 SO[877] -5129.5 408
995 SO[698] -2086.5 268 1055 SO[758] -3106.5 268 1115 SO[818] -4126.5 268 1175 SO[878] -5146.5 268
996 SO[699] -2103.5 128 1056 SO[759] -3123.5 128 1116 SO[819] -4143.5 128 1176 SO[879] -5163.5 128
997 SO[700] -2120.5 408 1057 SO[760] -3140.5 408 1117 SO[820] -4160.5 408 1177 SO[880] -5180.5 408
998 SO[701] -2137.5 268 1058 SO[761] -3157.5 268 1118 SO[821] -4177.5 268 1178 SO[881] -5197.5 268
999 SO[702] -2154.5 128 1059 SO[762] -3174.5 128 1119 SO[822] -4194.5 128 1179 SO[882] -5214.5 128
1000 SO[703] -2171.5 408 1060 SO[763] -3191.5 408 1120 SO[823] -4211.5 408 1180 SO[883] -5231.5 408
1001 SO[704] -2188.5 268 1061 SO[764] -3208.5 268 1121 SO[824] -4228.5 268 1181 SO[884] -5248.5 268
1002 SO[705] -2205.5 128 1062 SO[765] -3225.5 128 1122 SO[825] -4245.5 128 1182 SO[885] -5265.5 128
1003 SO[706] -2222.5 408 1063 SO[766] -3242.5 408 1123 SO[826] -4262.5 408 1183 SO[886] -5282.5 408
1004 SO[707] -2239.5 268 1064 SO[767] -3259.5 268 1124 SO[827] -4279.5 268 1184 SO[887] -5299.5 268
1005 SO[708] -2256.5 128 1065 SO[768] -3276.5 128 1125 SO[828] -4296.5 128 1185 SO[888] -5316.5 128
1006 SO[709] -2273.5 408 1066 SO[769] -3293.5 408 1126 SO[829] -4313.5 408 1186 SO[889] -5333.5 408
1007 SO[710] -2290.5 268 1067 SO[770] -3310.5 268 1127 SO[830] -4330.5 268 1187 SO[890] -5350.5 268
1008 SO[711] -2307.5 128 1068 SO[771] -3327.5 128 1128 SO[831] -4347.5 128 1188 SO[891] -5367.5 128
1009 SO[712] -2324.5 408 1069 SO[772] -3344.5 408 1129 SO[832] -4364.5 408 1189 SO[892] -5384.5 408
1010 SO[713] -2341.5 268 1070 SO[773] -3361.5 268 1130 SO[833] -4381.5 268 1190 SO[893] -5401.5 268
1011 SO[714] -2358.5 128 1071 SO[774] -3378.5 128 1131 SO[834] -4398.5 128 1191 SO[894] -5418.5 128
1012 SO[715] -2375.5 408 1072 SO[775] -3395.5 408 1132 SO[835] -4415.5 408 1192 SO[895] -5435.5 408
1013 SO[716] -2392.5 268 1073 SO[776] -3412.5 268 1133 SO[836] -4432.5 268 1193 SO[896] -5452.5 268
1014 SO[717] -2409.5 128 1074 SO[777] -3429.5 128 1134 SO[837] -4449.5 128 1194 SO[897] -5469.5 128
1015 SO[718] -2426.5 408 1075 SO[778] -3446.5 408 1135 SO[838] -4466.5 408 1195 SO[898] -5486.5 408
1016 SO[719] -2443.5 268 1076 SO[779] -3463.5 268 1136 SO[839] -4483.5 268 1196 SO[899] -5503.5 268
1017 SO[720] -2460.5 128 1077 SO[780] -3480.5 128 1137 SO[840] -4500.5 128 1197 SO[900] -5520.5 128
1018 SO[721] -2477.5 408 1078 SO[781] -3497.5 408 1138 SO[841] -4517.5 408 1198 SO[901] -5537.5 408
1019 SO[722] -2494.5 268 1079 SO[782] -3514.5 268 1139 SO[842] -4534.5 268 1199 SO[902] -5554.5 268
1020 SO[723] -2511.5 128 1080 SO[783] -3531.5 128 1140 SO[843] -4551.5 128 1200 SO[903] -5571.5 128

1201 SO[904] -5588.5 408 1261 SO[964] -6608.5 408 1321 SO[1024] -7628.5 408 1381 SO[1084] -8648.5 408
1202 SO[905] -5605.5 268 1262 SO[965] -6625.5 268 1322 SO[1025] -7645.5 268 1382 SO[1085] -8665.5 268
1203 SO[906] -5622.5 128 1263 SO[966] -6642.5 128 1323 SO[1026] -7662.5 128 1383 SO[1086] -8682.5 128
1204 SO[907] -5639.5 408 1264 SO[967] -6659.5 408 1324 SO[1027] -7679.5 408 1384 SO[1087] -8699.5 408
1205 SO[908] -5656.5 268 1265 SO[968] -6676.5 268 1325 SO[1028] -7696.5 268 1385 SO[1088] -8716.5 268
1206 SO[909] -5673.5 128 1266 SO[969] -6693.5 128 1326 SO[1029] -7713.5 128 1386 SO[1089] -8733.5 128
1207 SO[910] -5690.5 408 1267 SO[970] -6710.5 408 1327 SO[1030] -7730.5 408 1387 SO[1090] -8750.5 408
1208 SO[911] -5707.5 268 1268 SO[971] -6727.5 268 1328 SO[1031] -7747.5 268 1388 SO[1091] -8767.5 268
1209 SO[912] -5724.5 128 1269 SO[972] -6744.5 128 1329 SO[1032] -7764.5 128 1389 SO[1092] -8784.5 128
1210 SO[913] -5741.5 408 1270 SO[973] -6761.5 408 1330 SO[1033] -7781.5 408 1390 SO[1093] -8801.5 408
1211 SO[914] -5758.5 268 1271 SO[974] -6778.5 268 1331 SO[1034] -7798.5 268 1391 SO[1094] -8818.5 268
1212 SO[915] -5775.5 128 1272 SO[975] -6795.5 128 1332 SO[1035] -7815.5 128 1392 SO[1095] -8835.5 128
1213 SO[916] -5792.5 408 1273 SO[976] -6812.5 408 1333 SO[1036] -7832.5 408 1393 SO[1096] -8852.5 408
1214 SO[917] -5809.5 268 1274 SO[977] -6829.5 268 1334 SO[1037] -7849.5 268 1394 SO[1097] -8869.5 268
1215 SO[918] -5826.5 128 1275 SO[978] -6846.5 128 1335 SO[1038] -7866.5 128 1395 SO[1098] -8886.5 128
1216 SO[919] -5843.5 408 1276 SO[979] -6863.5 408 1336 SO[1039] -7883.5 408 1396 SO[1099] -8903.5 408
1217 SO[920] -5860.5 268 1277 SO[980] -6880.5 268 1337 SO[1040] -7900.5 268 1397 SO[1100] -8920.5 268
1218 SO[921] -5877.5 128 1278 SO[981] -6897.5 128 1338 SO[1041] -7917.5 128 1398 SO[1101] -8937.5 128
1219 SO[922] -5894.5 408 1279 SO[982] -6914.5 408 1339 SO[1042] -7934.5 408 1399 SO[1102] -8954.5 408
1220 SO[923] -5911.5 268 1280 SO[983] -6931.5 268 1340 SO[1043] -7951.5 268 1400 SO[1103] -8971.5 268
1221 SO[924] -5928.5 128 1281 SO[984] -6948.5 128 1341 SO[1044] -7968.5 128 1401 SO[1104] -8988.5 128
1222 SO[925] -5945.5 408 1282 SO[985] -6965.5 408 1342 SO[1045] -7985.5 408 1402 SO[1105] -9005.5 408
1223 SO[926] -5962.5 268 1283 SO[986] -6982.5 268 1343 SO[1046] -8002.5 268 1403 SO[1106] -9022.5 268
1224 SO[927] -5979.5 128 1284 SO[987] -6999.5 128 1344 SO[1047] -8019.5 128 1404 SO[1107] -9039.5 128
1225 SO[928] -5996.5 408 1285 SO[988] -7016.5 408 1345 SO[1048] -8036.5 408 1405 SO[1108] -9056.5 408
1226 SO[929] -6013.5 268 1286 SO[989] -7033.5 268 1346 SO[1049] -8053.5 268 1406 SO[1109] -9073.5 268
1227 SO[930] -6030.5 128 1287 SO[990] -7050.5 128 1347 SO[1050] -8070.5 128 1407 SO[1110] -9090.5 128
1228 SO[931] -6047.5 408 1288 SO[991] -7067.5 408 1348 SO[1051] -8087.5 408 1408 SO[1111] -9107.5 408
1229 SO[932] -6064.5 268 1289 SO[992] -7084.5 268 1349 SO[1052] -8104.5 268 1409 SO[1112] -9124.5 268
1230 SO[933] -6081.5 128 1290 SO[993] -7101.5 128 1350 SO[1053] -8121.5 128 1410 SO[1113] -9141.5 128
1231 SO[934] -6098.5 408 1291 SO[994] -7118.5 408 1351 SO[1054] -8138.5 408 1411 SO[1114] -9158.5 408
1232 SO[935] -6115.5 268 1292 SO[995] -7135.5 268 1352 SO[1055] -8155.5 268 1412 SO[1115] -9175.5 268
1233 SO[936] -6132.5 128 1293 SO[996] -7152.5 128 1353 SO[1056] -8172.5 128 1413 SO[1116] -9192.5 128
1234 SO[937] -6149.5 408 1294 SO[997] -7169.5 408 1354 SO[1057] -8189.5 408 1414 SO[1117] -9209.5 408
1235 SO[938] -6166.5 268 1295 SO[998] -7186.5 268 1355 SO[1058] -8206.5 268 1415 SO[1118] -9226.5 268
1236 SO[939] -6183.5 128 1296 SO[999] -7203.5 128 1356 SO[1059] -8223.5 128 1416 SO[1119] -9243.5 128
1237 SO[940] -6200.5 408 1297 SO[1000] -7220.5 408 1357 SO[1060] -8240.5 408 1417 SO[1120] -9260.5 408
1238 SO[941] -6217.5 268 1298 SO[1001] -7237.5 268 1358 SO[1061] -8257.5 268 1418 SO[1121] -9277.5 268
1239 SO[942] -6234.5 128 1299 SO[1002] -7254.5 128 1359 SO[1062] -8274.5 128 1419 SO[1122] -9294.5 128
1240 SO[943] -6251.5 408 1300 SO[1003] -7271.5 408 1360 SO[1063] -8291.5 408 1420 SO[1123] -9311.5 408
1241 SO[944] -6268.5 268 1301 SO[1004] -7288.5 268 1361 SO[1064] -8308.5 268 1421 SO[1124] -9328.5 268
1242 SO[945] -6285.5 128 1302 SO[1005] -7305.5 128 1362 SO[1065] -8325.5 128 1422 SO[1125] -9345.5 128
1243 SO[946] -6302.5 408 1303 SO[1006] -7322.5 408 1363 SO[1066] -8342.5 408 1423 SO[1126] -9362.5 408
1244 SO[947] -6319.5 268 1304 SO[1007] -7339.5 268 1364 SO[1067] -8359.5 268 1424 SO[1127] -9379.5 268
1245 SO[948] -6336.5 128 1305 SO[1008] -7356.5 128 1365 SO[1068] -8376.5 128 1425 SO[1128] -9396.5 128
1246 SO[949] -6353.5 408 1306 SO[1009] -7373.5 408 1366 SO[1069] -8393.5 408 1426 SO[1129] -9413.5 408
1247 SO[950] -6370.5 268 1307 SO[1010] -7390.5 268 1367 SO[1070] -8410.5 268 1427 SO[1130] -9430.5 268
1248 SO[951] -6387.5 128 1308 SO[1011] -7407.5 128 1368 SO[1071] -8427.5 128 1428 SO[1131] -9447.5 128
1249 SO[952] -6404.5 408 1309 SO[1012] -7424.5 408 1369 SO[1072] -8444.5 408 1429 SO[1132] -9464.5 408
1250 SO[953] -6421.5 268 1310 SO[1013] -7441.5 268 1370 SO[1073] -8461.5 268 1430 SO[1133] -9481.5 268
1251 SO[954] -6438.5 128 1311 SO[1014] -7458.5 128 1371 SO[1074] -8478.5 128 1431 SO[1134] -9498.5 128
1252 SO[955] -6455.5 408 1312 SO[1015] -7475.5 408 1372 SO[1075] -8495.5 408 1432 SO[1135] -9515.5 408
1253 SO[956] -6472.5 268 1313 SO[1016] -7492.5 268 1373 SO[1076] -8512.5 268 1433 SO[1136] -9532.5 268
1254 SO[957] -6489.5 128 1314 SO[1017] -7509.5 128 1374 SO[1077] -8529.5 128 1434 SO[1137] -9549.5 128
1255 SO[958] -6506.5 408 1315 SO[1018] -7526.5 408 1375 SO[1078] -8546.5 408 1435 SO[1138] -9566.5 408
1256 SO[959] -6523.5 268 1316 SO[1019] -7543.5 268 1376 SO[1079] -8563.5 268 1436 SO[1139] -9583.5 268
1257 SO[960] -6540.5 128 1317 SO[1020] -7560.5 128 1377 SO[1080] -8580.5 128 1437 SO[1140] -9600.5 128
1258 SO[961] -6557.5 408 1318 SO[1021] -7577.5 408 1378 SO[1081] -8597.5 408 1438 SO[1141] -9617.5 408
1259 SO[962] -6574.5 268 1319 SO[1022] -7594.5 268 1379 SO[1082] -8614.5 268 1439 SO[1142] -9634.5 268
1260 SO[963] -6591.5 128 1320 SO[1023] -7611.5 128 1380 SO[1083] -8631.5 128 1440 SO[1143] -9651.5 128

Pad name X Y No. Pad name X Y
SO[1144] -9668.5 408 1501 SHIELDING -10814 428
SO[1145] -9685.5 268 1502 DCMPR -10864 428
SO[1146] -9702.5 128 1503 DCMPR -10914 428
SO[1147] -9719.5 408 1504 OEVR -11049 328
SO[1148] -9736.5 268 1505 INVBRR -11049 408
SO[1149] -9753.5 128 1506 INVBRR -11179 408
SO[1150] -9770.5 408 1507 OEVR -11179 328
SO[1151] -9787.5 268 1508 UDR -11179 248
SO[1152] -9804.5 128 1509 UDR -11049 248
SO[1153] -9821.5 408 1510 CKVR -11179 168
SO[1154] -9838.5 268 1511 CKVR -11049 168
SO[1155] -9855.5 128 1512 STV1R -11179 88
SO[1156] -9872.5 408 1513 STV1R -11049 88
SO[1157] -9889.5 268 1514 STV2R -11179 8
SO[1158] -9906.5 128 1515 STV2R -11049 8
SO[1159] -9923.5 408 1516 STV1R -11179 -72
SO[1160] -9940.5 268 1517 STV1R -11049 -72
SO[1161] -9957.5 128 1518 STBNR -11179 -152
SO[1162] -9974.5 408 1519 STBNR -11049 -152
SO[1163] -9991.5 268 1520 DUMMY -11179 -232
SO[1164] -10008.5 128 1521 DUMMY -11049 -232
SO[1165] -10025.5 408
SO[1166] -10042.5 268
SO[1167] -10059.5 128
SO[1168] -10076.5 408
SO[1169] -10093.5 268
SO[1170] -10110.5 128
SO[1171] -10127.5 408
SO[1172] -10144.5 268
SO[1173] -10161.5 128
SO[1174] -10178.5 408
SO[1175] -10195.5 268
SO[1176] -10212.5 128
SO[1177] -10229.5 408
SO[1178] -10246.5 268
SO[1179] -10263.5 128
SO[1180] -10280.5 408
SO[1181] -10297.5 268
SO[1182] -10314.5 128
SO[1183] -10331.5 408
SO[1184] -10348.5 268
SO[1185] -10365.5 128
SO[1186] -10382.5 408
SO[1187] -10399.5 268
SO[1188] -10416.5 128
SO[1189] -10433.5 408
SO[1190] -10450.5 268
SO[1191] -10467.5 128
SO[1192] -10484.5 408
SO[1193] -10501.5 268
SO[1194] -10518.5 128
SO[1195] -10535.5 408
SO[1196] -10552.5 268
SO[1197] -10569.5 128
SO[1198] -10586.5 408
SO[1199] -10603.5 268
SO[1200] -10620.5 128
SHIELDING -10664 428
COM1_T -10714 428
COM1_T -10764 428

10. Revision History
Version No. Date Page Description
Modify DCMP_EM (Normally pull low)Æ (Normally pull high)
Spec_0.01 2009/06/23 P08
Modify UPDN (Normally pull low)Æ (Normally pull high)
P34 Modify Analog operating current TBDÆ Typ=10mA Max=12mA

Modify Digital operating current TBD Æ Typ=8mA Max=10mA
Modify Analog standby current TBD Æ Typ=10uA Max=50uA
Spec_0.02 2009/09/25
Modify Digital standby current TBDÆ Typ=10uA Max=50uA
Add Chip size: 22498 um x 960 um.
P43 Add Chip height: 400 um .
Spec_0.03 2009/10/15 P50 Modify the pad location.
P14 Modify Dot Polarity Inversion Diagram.

Spec_0.04 2009/11/13 P11 Add Pin Descriptions.(FB 、DRV、PWM_EN)
P7 Add Application Block Diagram.

P27 Add Register Default Value Table
Spec_0.05 2009/12/14 P28~35 Add Register Default Value
P31 Modify BLKEN Frequency Specification.
Spec_0.06 2010/01/06 P7/P9/P21 Add Application Block Diagram of 800X480 with ILI5960
Spec_0.07 2010/04/08 P30 Modify Content Adaptive Brightness Control register address “55H”Æ”82H”
ALL NEW Logo
P14 Add Hardware Pin Control CABC Mode Selection
P11/P48/P50/P6 Add REV Function.
P12 Modify DCMP_EM (Normally pull high)Æ (Normally pull low)
Spec_0.08 2010/06/11
P12 Modify UPDN (Normally pull high)Æ (Normally pull low)
P21/P22 Modify Application Block Diagram.
P49 Modify Chip size(Include scribe line)
Modify D5 、E2、 E5 Pad Size.

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ILI6122

ILI TECHNOLOGY CORP.

Page 2 of 57 Version: 0.08

Page 3 of 57 Version: 0.08

¾ Supports digital 24-bit parallel RGB input mode

¾ Supports to configure CABC block via 3-line SPI mode

¾ Supports dual-gate operation mode

¾ Supports Stripe CF configuration

¾ Maximum Operation frequency: 50 MHz

¾ Provide flip and mirror scan mode by pin control

¾ Supports stand-by mode for saving power consumption

¾ Operation Voltage Level 3.0V to 3.6V

¾ Hardware Pin Control CABC Mode Selection

¾ Embedded custom-made Gamma table for special custom request

¾ Supports external V1~V14 pad for Gamma adjustment

¾ Output dynamic range : 0.1 ~ VDDA-0.1V

¾ Voltage deviation of outputs: ±20mV

¾ Power for source driver voltage (VDDA) : 6.5V ~ 13.5V

Page 4 of 57 Version: 0.08

¾ Supports CABC (Content Adaptive Brightness Control) function

Page 5 of 57 Version: 0.08

Page 6 of 57 Version: 0.08

(1,480) (800, 480) (800,480) (1, 480)

RES0=L(800 X480) RES0=L(800 X480)

(1,480) G1 (800,480) (800,480) (1,480)

Page 7 of 57 Version: 0.08

(1,1) G1 (800,1) (800,1) G1

RES0=H(800 X600) RES0=H(800 X600)

(1,600) G1 (800,600) (800,600) G1 (1,600)

(1,1) (800, 1) (800,1) (1, 1)

RES0=H(800 X600) RES0=H(800 X600)

Page 8 of 57 Version: 0.08

(1,1) G480 (800,1) (800,1) G480 (1,1)

RES0=L(800 X480) RES0=L(800 X480)

(1,480) G480 (800,480) (800,480) G480 (1,480)

RES0=L(800 X480) RES0=L(800 X480)

Page 9 of 57 Version: 0.08

(1,1) G600 (800,1) (800,1) G600 (1,1)

RES0=H(800 X600) RES0=H(800 X600)

(1,600) G600 (800,600) (1,1) G600 (800,1)

RES0=H(800 X600) RES0=H(800 X600)

Page 10 of 57 Version: 0.08

HSD I Horizontal sync input in digital parallel RGB. Negative polarity.

VSD I Vertical sync input in digital parallel RGB. Negative polarity.

Data inverted control. Normally pull low

RSTB I Hardware global reset. Low active. (Normally pull high)

Page 11 of 57 Version: 0.08

Page 12 of 57 Version: 0.08

Page 13 of 57 Version: 0.08

DBC/3 for CABC Function Control description:

Page 14 of 57 Version: 0.08

Page 15 of 57 Version: 0.08

5.1.1. Stripe Mode

SHLR=“L”, Left Shift Direction

SHLR=“H”, Right Shift Direction

Page 16 of 57 Version: 0.08

Page 17 of 57 Version: 0.08

SO1 SO2 SO3 SO4

Page 18 of 57 Version: 0.08

Page 19 of 57 Version: 0.08