COA Question Bank

Unit-1:
1. Bring out the differences between microprocessors and Microcontrollers.

Outline the Architecture of a Microprocessor.
2. Enumerate the register structure of ARM processor and give the structure of
CPSR.
3. Identify the types of addressing modes used in the following instructions and
how do they execute?
I. MOV R0, #45
II. LDR R6, [R5], #08
III. STR R9, [R5,#-4]!
IV. ADD R1, R2,R3, LSL #2
V. STR R2, [R5,#-4]
4. Write an ARM program to reverse the order of bits in register R2. For
example, if the starting pattern in R2 is 1110 . . . 0100, the final result in R2
should be 0010 0111. (Hint: Use shift and rotate operations.)
5. With a neat block diagram explain the fetch, decode and execution phases of
instruction execution in ARM Processor
6. Highlight the action performed by the following instructions and assembler
directives supported by ARM processor
I. MOVS
II. MUL
III. ORR
IV. BNE
V. BL
VI. EQU
7. Enumerate the syntax of pre-indexed and post-indexed addressing modes
used in LDR and STR Instructions, with an example for each.
8. Write an ALP that checks to find if the given 32-bit number is odd. If yes,
store
‘ODD’ in Processor register else store ‘EVEN’ in the same register
9. Outline the architecture of an 8086 microprocessor and illustrate the
difference between microprocessor and microcontroller.
10. Identify the types of addressing modes used in the following instructions and
how do they execute?
I. MOV R0, R1
II. ADD R6, R5, R3
III. SUB R2, R3, R4
IV. ADD R1, R2, R3, LSL #2
V. STR R2, [R5, #-4]
11. Write an ARM program to demonstrate the subroutine linkage instruction and
explain.
12. With a neat block diagram explain the architecture of ARM processor.
13. Highlight the action performed by the following instructions and assembler
directives supported by ARM processor
I. ADDS
II. CMP
III. EOR
IV. MLA
V. SBC
14. Enumerate the syntax of pre-indexed and post-indexed addressing modes
used in LDR and STR Instructions, with an example for each.
15. Write an ALP that checks to find if the given 16-bit number is EVEN. If yes,
store ‘EVEN’ in Processor register else store ‘ODD’ in the same register.
16. List the various Addressing modes supported by ARM Processor with one example
for each.
17. List the types of Instructions of ARM Instruction set and detail the execution of
following Instructions
ADDS, MUL, BX, BL, AND, BIC, TEQ and CMP
18. Write ALP to find the sum of N 32-bit numbers and check if the sum is odd or
even?
19. Explain the modes of operation of ARM.
20. Outline the importance of Assembler directives used in ARM
Programming
21. Outline the working of the following of the ARM Instructions with one
example for each.
LDRBH ADDS MUL MVN EOR TEQ
22. Outline the importance of Bank registers of ARM.
23. List all the characteristics of ARM processor covering RISC, CISC and its
own special features.
24. Explain the following instructions and assembler directives supported by ARM
processor
MOVCS, SUBS, LDMIA, EOR, B, ENTRY
25. Outline in brief any five operation modes of an ARM processor.
26. Bring out the concept of IOT using the components
27. Bring out the importance of Assembler directives of ARM and elaborate on the
role played by the directives ORG, DCD and END in a program.
Unit-2:
1. With the aid of the logic diagram of a sequential multiplier and demonstrate
multiplication of 22 and 29 in the multiplier.
2. Construct the Booth recoded multiplier for the multiplier ‘100101’
3. Demonstrate the subtraction in a Ripple Carry Adder/Subtractor
4. Compute the product of 14 and -11 using Booth algorithm.
5. With a neat block diagram explain the working of addition and subtraction.
(Using only one circuit)
6. Write an ALP to perform multiplication of a 4-bit unsigned number (1010) by
2 without using MUL instruction.
7. Demonstrate the working of multiplication of 2 unsigned binary numbers with
the help of a circuit.
8. Compute the product of 11 and -13 using Booth algorithm.
9. Demonstrate the Multiplication operation of 17 and 23 using Bit pair recoded
multiplier algorithm.
10. Demonstrate the Division operation of 19/4 using Non-restoring division
Algorithm
11. Demonstrate the Division operation of 22/5 using Restoring division Algorithm.
12. Express (23.29)10 in binary floating-point IEEE 32-bit format (normalized).
13. Convert the multiplier 25 into modified booth multiplier used in multiplication
operation.
14. Demonstrate the Multiplication operation of 13 and -11 using Bit Pair
Recoding Algorithm
15. Demonstrate the Division operation of 23/3 using Restoring division Algorithm
16. Demonstrate the Division operation of 26/3 using non-Restoring division
Algorithm
17. Express (42.79)10 in binary floating-point IEEE 64-bit format (normalized).
18. Make use of Binary division hardware to demonstrate the division of 23/4
employing restoring division algorithm
19. Apply Bit pair recoding multiplier Algorithm to find the product of +19 and
–26
20. Compute the product of 45 and 50 using a fast adder that adds summands
by saving the carry
21. Show how (19.36)10 can be represented in 64-bit IEEE format.
22. State the advantage of sequential multiplier and give the hard ware
setup for performing multiplication on unsigned numbers.
23. Enumerate the concept of carry look-ahead adder used for fast adder.
24. With the aid of the logic diagram of sequential multiplier and
demonstrate multiplication of 14 and 9 in the multiplier
25. Compute the product of -31 and -28 using Booth algorithm
26. Demonstrate the multiplication operation of 13 and -11 using Bit Pair
Recoding Algorithm
Unit-3:
1. Discuss the Organization of 1K X 1 memory organized on a chip and find the

number of external connections required to connect it to Processor
2. List the various mapping functions that map the main memory and Cache.
For a main memory having 4K blocks and Cache with 128 blocks, detail how
the Direct mapping function maps them.
3. Enumerate the process of transferring data directly between main memory
and secondary devices. Detail all the registers involved in the data transfer.
What is its advantage?
4. Discuss the Virtual memory organization. How is the virtual address
translated into Physical address by the MMU?
5. Sketch a Static RAM cell and a Dynamic RAM cell and discuss how Read and
write operations can be performed by the cell?
6. Outline the memory hierarchy of different types of memory used in a
memory system.
7. A main memory having 4K blocks and Cache with 128 blocks have to be
mapped using Set associative mapping function. Two adjacent blocks of the
Cache form a set. Detail the mapping function scheme that performs the
mapping task.
8. Show the Organization of 2M X 8 memory organized using memory chips of
size 512K X 8 that can be used for performing 32-bit Read/Write operations
9. List the various mapping functions that map the main memory and Cache.
For a main memory having 4K blocks and Cache with 128 blocks, detail how
the Associative mapping function maps them.
10. Enumerate the process of transferring data directly between main memory
and secondary devices. Detail all the registers involved in the data transfer.
What is its advantage?
11. Outline the memory hierarchy of different types of memory used in a
memory system.
12. Discuss the Virtual memory organization. How is the virtual address
translated into Physical address by the MMU
13. Sketch a Static RAM cell and a Dynamic RAM cell and discuss how Read and
write operations can be performed by the cell?
14. Show the Organization of 32m X 8 memory that uses Synchronous DRAMS.
When do the cells get refreshed?
15. Discuss the Set Associative Mapping function that maps a main memory
having 4K blocks and Cache with 128 blocks and 2 sets per block
16. Outline the organization of 2M X 8 memory that can be built using
512K X 8 memory chips.

17. Develop Set associative mapping function that maps 128 blocks of
Cache with 2 blocks per set and a main memory having 4k blocks.
18. Show the Memory hierarchy of computer memory system
19. Outline the organization of a 1K X 1 memory chip using static memory

cells. How many external connections does it provide?
20. Outline the translation of Virtual address to Physical address by the
MMU in Virtual memory system

21. What is page fault? How is it handled by Operating System?
Unit-4:
1. Explain with a neat sketch the working of a single bus structure

2. Illustrate between parallel and serial interface circuits
3. List down the interconnection networks and explain any two with suitable
examples
4. Illustrate between synchronous and asynchronous bus in detail
5. Explain how data transfer takes place between I/O device and processor in a
program controlled I/O.
6. Describe in detail about inter connection standards
7. Define hardware multithreading. Explain in detail about vector processing.
8. Illustrate the concept of Arbitration with a suitable example
9. Define USB and explain about USB serial bus structure in detail
10. Explain how data transmission done in PCI bus
11. Explain with the help of neat diagram the working of PCI express
12. Define vector processing and explain about shared memory multiprocessors
13. Explain in detail about Ring based inter connection networks
14. Explain in detail about Crossbar inter connection networks
15. Outline the Bus Arbitration scheme with the aid of a timing diagram for
a case where 3 masters’ assigned priorities by the arbiter contend for
the common bus.
16. Outline the read operation performed on a PCI bus for a 32-bit word
transfer from memory.
17. Demonstrate the serial interfacing of processor and I/O devices with the
aid of a block diagram
18. Outline the concept of hardware multi threading
19. Outline the PCI Interconnection standard and show the PCI express
connections.

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Unit-1:

1. Bring out the differences between microprocessors and Microcontrollers.

1. Discuss the Organization of 1K X 1 memory organized on a chip and find the

512K X 8 memory chips.

19. Outline the organization of a 1K X 1 memory chip using static memory

MMU in Virtual memory system

1. Explain with a neat sketch the working of a single bus structure

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