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    Global Academy of Technology: Question Bank

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    Global Academy of Technology: Question Bank

    Uploaded by

    sourabha prasad
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    QB

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    48 views6 pages

    Global Academy of Technology: Question Bank

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    sourabha prasad

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    © All Rights Reserved
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    GLOBAL ACADEMY OF TECHNOLOGY

    (An Autonomous Institution, affiliated to VTU, Belagavi, recognized by Karnataka and Approved by AICTE, New Delhi.)

    DEPARTMENT OF ARTIFICIAL INTELLIGENCE AND MACHINE LEARNING

    Name of the Faculty: C Christlin Shanuja


    Subject: Computer Organization and Architecture
    Sub. Code: 22AML33

    QUESTION BANK
    Module 1

    1. With a neat diagram explain the different processor registers.


    2. What are the factors that affect the performance? Explain any 4.
    3. What is performance measurement? Explain the overall SPEC rating for a computer
    in a program suite.
    4. Write the difference b/w RISC and CISC processors.
    5. Write a note on byte addressability, big-endian and little-endian assignment.
    6. Explain the basic operational concepts b/w the processor and the memory.
    7. Derive the basic performance equation? Discuss the measures to improve the
    performance.
    8. Explain processor clock and clock rate.
    9. What is an addressing mode? Explain any four addressing modes.
    10. Mention four types of operations to be performed by instructions in a computer.
    11.Explain with neat diagram basic operational concept of computer.
    12. What is performance measurement? Explain overall SPEC rating for computer in a
    program suite.
    13. Draw single bus structure, discuss about memory mapping I/O.
    14. What is addressing mode? Explain all addressing modes with example.
    15. Explain BIG-ENDIAN and LITTLE-ENDIAN method of byte addressing with
    example.
    16. Explain Basic instruction types with example

    Module 2
    1. Define exceptions. Explain two kinds of exceptions.
    2. Define bus arbitration. Explain in detail both approach of bus arbitration.
    3. What is an interrupt; with example illustrate the concept of interrupts
    4. Explain in detail the situation where a number of devices capable of initiating

    interrupts are connected to the processor? How to resolve the problems?

    5. Explain the following terms a) interrupt service routine b) interrupt latency c)interrupt
    disabling.
    6. With a diagram explain daisy chaining technique.
    7. Draw the arrangement of a single bus structure and brief about memory mapped I/O.
    8. Explain interrupt enabling, interrupt disabling, edge triggering with respect to
    interrupts
    9. Draw the arrangement for bus arbitrations using a daisy chain and explain in brief.
    10. With neat sketches explain various methods for handling multiple interrupt requests.
    11. Define memory mapped I/0 and I/0 mapped I/0 with examples.
    12. Explain how interrupt request from several I/0 devices can be communicated to a
    processor through a single INTR line.
    13. What are the different methods of DMA. Explain in brief.
    14. Explain the important functions of a I/0 interface with a neat block diagram
    15. What is DMA? Explain the hardware registers that are required in a DMA controller
    chip.
    16. Explain the use of DMA controller in a computer system with a neat diagram.
    17. with a block diagram a general 8 bit parallel interface.
    18. With supporting diagram explain the following with respect to interrupts:
    Vectored interrupt
    Interrupt nesting
    Simultaneous request
    Daisy-chain method
    19.With a neat diagram, explain the centralized arbitration and distributed bus
    arbitration scheme.
    20.With a neat timing diagram illustrate the asynchronous bus data transfer during an
    I/O operation. Use handshake scheme.
    21.Write a note on register in DMA interface.
    22.With a block diagram explain how the printer interfaced to processor.

    Module 3
    1. With the block diagram explain the operation of a 16-megabit DRAM chip configured
    as 2M*8.
    2. Mention any two differences b/w static and dynamic RAM. Explain the internal
    organization of a memory chip consisting of 16 words of 8 bit each.
    3. Which are the various factors to be considered in the choice of a memory chip. Explain
    4. Give the organization of a 2M*32 memory module using 512k*8 static memory chips
    5. Discuss, the different types of RAM’s bring out their salient features
    6. Define memory latency and bandwidth of synchronous DRAM memory unit.
    7. What is virtual memory? Explain how virtual address is translated to physical address.
    8. Explain direct memory mapping technique
    9. Show with diagram the memory hierarchy with respect to speed, size and cost
    10.Explain different mapping functions used in cache memory.
    11.Define memory latency, memory bandwidth, hit rate and miss penalty.
    12.Briefly explain all mapping functions used in cache memory.
    13.Define cache memory, explain various types with a neat diagram.
    14.With a neat diagram explain the internal organization of memory chip(2M x 8 and
    dynamic memory chip).
    15.Explain the following (i) Hit Rate (ii) miss penalty (iii) valid bit (iv) Dirty bit (v) steal
    data
    16.Draw a diagram and explain the working of 26 Megabit DRAM chip configuration as
    2M x 8
    17.Describe organization of an 2M x 32 memory using512k x 8 memory chip.
    18.Explain synchronous DRAMS with a block diagram.
    19.Define ROM, explain various types of ROM.

    Module 4

    1. With neat diagram, explain the virtual memory organization


    2. Design a logic circuit to perform addition or subtraction of two n –bit numbers X&Y
    3. Explain booth algorithm. Apply booth algorithm to multiply the sign numbers+13&-6
    4. Write the logic diagram of 4-bit carry look ahead adder; explain the operation and how
    it is faster than four bit ripple adder
    5. Perform multiplication for -13&+9 using booth’s algorithm
    6. Write the circuit arrangement for binary division. Perform the restoring division for the
    given binary number 1000/11, show all cycles
    7. Given A=10101 &B=00100 perform a/b using restoring division algorithm
    8. Explain with figure the design and working of 16 bit carry look ahead adder built from
    4 bit adders.
    9. Differentiate between restoring and non-restoring division
    10. Explain with neat diagram, the basic organization of a microprogrammed control.
    11. Write control sequence for the instruction Add R1,R2,R3.
    12. Explain a complete processor with a neat diagram
    13. Write and explain the control sequences for the execution of the following
    instruction: Add (R3), R1.
    14. Bring out the differences between micro programmed control and hardwired control.
    15. Explain multiple bus organization and its advantages.
    16.Draw 4-bit carry-look ahead adder and explain.
    17.With a neat diagram explain single-bus organization of data-path inside a processor.
    18.What are the actions required to execute a complete instruction ADD (R3), R1
    19.Explain multi-bus(or three bus) organization of data-path with a neat diagram. Write
    control sequence for the instruction ADD R4, R5, R6 for the multiple bus
    organization.
    20.Explain with neat diagram, micro-programmed control method design of control unit
    and write the micro-routine for the instruction Branch<0.
    21.Explain Hard wired control unit organization in a processing unit.
    22.Write control sequence for an unconditional branch instruction.
    23.Perform multiplication for -13 and +9 using Booth’s algorithm and bit pair
    multiplication. Explain the Booth’s algorithm of multiplication.
    24.Design 16-bit carry-look ahead adder using 4-bit adder. Also unite the expression for
    C i+1 .
    25.Perform following operation on the 5-bits signed numbers using 2’s complement
    representation system. Also indicate whether overflow has occurred. (i) (-9) + (-7) (ii)
    (+7) - (-8).
    26.Perform division operation on the following unsigned numbers using the restoring and
    non-restoring method. Dividend=(10101) 2 divisor= (00100) 2

    Module 5

    1. Explain the parallel processing concept with a block diagram showing multiple
    functional units.
    2. Explain the role of cache memory in pipelining.
    3. Explain pipelining performance.
    4. Explain pipelining technique with an example.
    5. With an example, explain working of arithmetic pipeline.
    6. What is instruction pipeline? Explain 4-segment instruction pipeline.
    7. Explain the concept of vector processing. Mention few of its application area.
    8. Explain array processors in detail.
    9. With a neat diagram, discuss on RISC pipeline.
    10.Explain 3-segment instruction pipeline and discuss the advantages of it.
    11.Discuss about memory interleaving and matrix multiplication.

    Course Instructor HOD(AIML)

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