QB.1, 4 and 5 Modules

Module 1
3 Marks Questions
1. With a neat diagram, explain the internal architecture of the CPU.
2. Differentiate between Big-endian and Little-endian assignment for word addressing.
3. Differentiate between big-endian and little-endian byte assignments.
4. What are condition codes? List the different condition codes.
5. Explain one, two and three address instruction with an example for each
6. Write the three-address, two-address and one-address representations of the
operation below with relevant assumptions: C🡨 [A] + [B]
7. Describe auto increment addressing mode with the help of an example.
8. Give the relevance of MAR, PC and IR in a typical computer system with neat
diagram.
9. Illustrate the advantages of using multiple bus organization over single bus
organization with the help of a sample instruction execution.
10. Enumerate the sequence of actions involved in executing an unconditional branch
instruction.
11. Write down the sequence of actions needed to fetch and execute the instruction:
Store R6, X(R8).
12. Give the control sequence for execution of instruction Add[R2],R1 using a single bus
organization
13. Give the significance of instruction cycle.
4 Marks/ 5 Marks Questions

1. Illustrate the basic operational concepts in transferring data between main memory
and processor with neat diagram
2. What is meant by instruction sequencing? Discuss the different types of instruction
sequencing with example.
3. With the help of a diagram, describe the data-path inside the processor.
4. With the help of examples, explain the different addressing modes.
5. Describe any 4 addressing modes with examples.
6. Write notes on three address, two address and one address instructions, giving
example for each.
7. Define Addressing mode and explain Different types of addressing modes with an
example for each.
8. Discuss the data path inside the processor with single bus organization with neat
diagram
9. Explain single bus organization with the help of a diagram. Specify with examples,
how memory operations are done in the given organization.
10. Compare and contrast single bus and multiple bus organisation of CPU.
11. Write down the control sequence for the execution of the instruction Add (RI), R2 in
single bus organization
12. Draw the diagram of a multi-bus organization with 3 buses. Write the control
sequence for the instruction Add R4, R5, R6 for the above mentioned multi-bus
organization
13. Give the sequence of control steps required to perform the operation Add [R3], R1in
a single-bus organization.
9/10/14 Mark Questions

1. List various addressing modes explain any four with an example for each
2. Illustrate various addressing modes with proper examples.
3. Write the control sequence for the instruction DIV R1,[R2] in a three bus structure.
4. Explain the concept of a single bus organization with the help of a diagram. Write
the control sequence for the instruction ADD [R1],[R2]. (14 marks)
5. Draw the diagram of a multi-bus organization with 3 buses. Write the control
sequence for the instruction Add R4, R5, R6 for the above mentioned multi-bus
organization.
6.
MODULE 4
1.Design a hard-wired control unit based on the one flip-flop per state method to
add/subtract 2 signed numbers represented in the sign-and-magnitude form.(10/14 marks)
2.Explain the organization of a microprogrammed computer with a block diagram.(10/14 marks)
3.Draw a neat block diagram of a microprogram sequencer and explain its working.(10/14
marks)
4.With the help of a flowchart for sign-magnitude addition/subtraction, explain the
steps involved in developing a hardwired control unit.(10/14 marks)
5.Using a block diagram analyse the design of a microprogram control for a
processor unit.(10/14 marks)
6.With the help of a diagram establish the functioning of microprogram sequencer
in a microprogram controlled processor.(10/14 marks)
7.Compare vertical and horizontal microinstruction formats, giving examples.(10/14 marks)
8.With a diagram, explain how control signals are generated using hardwired
control.(10/14 marks)
9.Describe the purpose of microprogram sequencing. How is it carried out?(10/14 marks)
10.Explain with the help of a diagram, the working of microprogram sequencer.(10/14 marks)
11.Describe the steps in control logic design with the help of an example.
(Example can be realised using either hardwired or microprogrammed control
organization.)(10/14 marks)
MODULE 5
1.What are vectored interrupts?(3 marks)
2.Compare synchronous and asynchronous DRAM.
3.Define temporal locality and spatial locality.
4.Compare the two main modes of DMA transfer.
5.Explain any two priority interrupt schemes.
6.which design feature of SRAM cells helps in value retention without refresh?
7.Explain the functions of i/o interface circuits.
8.List and describe the registers in a DMA interface.
9.The cache block size in many computers is in the range of 32 to 128 bytes.
What would be the main advantages and disadvantages of making the size of
cache blocks larger?
10.A computer system has a main memory consisting of 1M 16-bit words. It also
has a 4K-word cache organized in the block-set-associative manner, with 4
blocks per set and 64 words per block. Calculate the number of bits in each of
the Tag, Set, and Word fields.
11.Briefly explain the LRU cache replacement algorithm
12.Describe centralized bus arbitration.
13.Write notes on static memories.
14.Differentiate between programmed I/O and interrupt driven I/O.
15.Define the terms a)Latency b)Bandwidth c)Memory cycle time.
16.Why do dynamic RAMs need constant refreshing? How is this done?
17.Explain Direct Memory Access. What is burst mode DMA?
1.Differentiate centralized and distributed bus arbitration mechanism used in DMA.(4 marks)
2.Give the structure of a typical static RAM cell and explain its read and write
operations.(5 marks)
3.What are interrupts? List the sequence of steps following an interrupt request.(5 marks)
4.Describe semiconductor RAM memories.(5 marks)
5.With the help of an example, explain the different cache mapping function(6 marks)
6.Differentiate between associative and set associative cache mapping with
examples.(5 marks)
7.Write notes on interrupt nesting. Explain how simultaneous interrupt requests
can be handled.(5 marks).
8.Discuss about the different types of Read only memories.(5 marks)
9 Briefly explain, with diagrams, the different methods for control organization(5 marks)
10.Write notes on microprogrammed CPU organisation.(5 marks)
11.Distinguish between centralized and distributed bus arbitration?(5 marks)
12.Write notes on set associative cache mapping.(5 marks)
13.Distinguish between synchronous and asynchronous DRAMs(5 marks)
14.Discuss about Content addressable memories.
15.Write short notes on memory consideration.
1.Elaborate the various cache mapping techniques with an example for each.(10/14marks)
2.With the help of a diagram examine the internal organisation of bit cells in a
memory chip.(10/14 marks)
3.Differentiate Direct and Associative mapped cache with examples.(9 marks).
4.What do you mean by bus arbitration and explain types of bus arbitration methods in
detail.(10/14 marks)

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Module 1

4 Marks/ 5 Marks Questions

9/10/14 Mark Questions

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