What is instruction set architecture?

Define CPI.

Discover instruction register?

Mention the purpose of program counter register?

Use of MAR and MDR

What are the five classic components of a computer?

Define Execution time/Response time.

What is meant by clock cycle and clock period?

Mention the various addressing modes of MIPS architecture.

Define – Stored Program Concepts

Write the MIPS instructions for the following statements

N1=N2-N3

Write the MIPS instructions for the following statements

C=a+b

Mention the factors that affect the CPU performance.

If a computer X runs a program in 25 ms and computer Y runs the same program in 30ms, how faster X
than Y?

Define Throughput or Bandwidth.

Write the truth table for half adder.

How overflow occur in subtraction?

When the overflow won't happen furthermore.

Mention the advantages of carry look-ahead-adder.

What is the compiled MIPS code for this statement?

g = h + A[8];

Give the format of MIPS R-type/I-type/J type instruction

Add the following decimal numbers using 2s compliment method 26 10 + (-3210)

Perform the following using 2s compliment method 11101100 2 - 101011102

Perform logical shift of the following binary number 11110011.

What is the booth’s recoded multiplier for the given multiplier 11101000?

Draw the diagram of multiplication hardware. And division hardware

Summary about pipeline stall?

Define data hazard.

Analyze Instruction in MIPS single cycle implementation takes longest clock cycle time for execution?

What is the ideal speed-up expected in a pipelined architecture with ‘n’ stages? Justify your answer.

Determine the classifications of data hazards?

Paraphrase about Datapath.

Paraphrase the use of PC register?

Summary about register file.

Guess the two types of datapath element?

What is meant by branch prediction? Why it is needed?

Use of Branch History Table (BHT)?

Mention the purpose of Multiplexors in the datapath.

Categorize the schemes to resolve data hazard?

Define forwarding or Bypassing?

Relate the term ‘flush’ in pipelining.

Define Exception.

Classify the five stages in the instruction pipelining

Summarize the purpose of EPC register?

Summarize the purpose of cause register?

Interpret about Rotational Latency

Utilize the purpose of track and sector.

Discover direct-mapped cache?

Differentiate SRAM from DRAM.

Define the term “block” in cache memory.

Categorize various memory technologies available.

Define Seek Time.

Examine the techniques to improve the cache performance.

Analyze the writing strategies in cache memory.

Summarize the steps to be taken in an instruction cache miss.

Differentiate memory mapped I/O and programmed I/O.

Differentiate maskable interrupt and non- maskable interrupt.

Mention any four features of USB.

Differentiate memory mapped I/O and programmed I/O.

Differentiate maskable interrupt and non- maskable interrupt.

Mention any four features of USB.

Describe about polling.

What is Microprocessor?

Name the 3 main units of the stored program computer

What is the function of Accumulator?

How does the number of general-purpose registers affect the performance of an MPU?

For what reason is ROM and RAM required by a system?

Explain the function of address bus, data bus and control bus.

Define Stack

Define addressing mode.

What are the different types of addressing modes of 8086 instruction set

What are the different types of instructions in 8086 microprocessor

The data bus is bidirectional; why is that?

Differentiate between operand and an opcode

Differentiate between I/O mapping and memory mapping

What are the functional units available in 8086 architecture

Give the various segment registers of 8086

How is the stack top address calculated?

How do macros work?

Differentiate between Loader and Linker

Describe ASSUME & ALIGN.

Explain the various components of computer System with neat diagram.

i) What is the significance of stored program concept? ii) Explain about little-endian and big-endian
memory arrangement.

i) Differentiate Von-neuman architecture and Harvard architecture.

ii) Differentiate RISC and CISC architecture.
Describe the MIPS Instruction set in detail with suitable examples.

Describe the arithmetic operations and control operations of MIPS with suitable example.

Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 3 GHz
clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and
has a CPI of 2.2.
i) Which processor has the highest performance expressed in instructions per second? (6)
ii). If the processors each execute a program in 10 seconds, find the number of cycles and the number of
instructions.

i) Suppose we have two implementations of the same instruction set architecture. Computer A has a clock
cycle time of 250 ps and a CPI of 2.0 for some program, and computer B has a clock cycle time of 500 ps
and a CPI of 1.2 for the same program. Which computer is faster for this program and by how much? (6)
Our favorite program runs in 10 seconds on computer A, which has a 2 GHz clock. ii) We are trying to help
a computer designer build a computer, B, which will run this program in 6 seconds. The designer has
determined that a substantial increase in the clock rate is possible, but this increase will affect the rest of the
CPU design, causing computer B to require 1.2 times as many clock cycles as computer A for this program.
What clock rate should we tell the designer to target?

Translate the following MIPS assembly instruction into machine instruction and also explain the fields of
the instruction format for each instruction
i) sub $t0, $s1, $s2
ii) addi $s1, $s2, 100

Translate the following MIPS assembly instruction into machine instruction and also explain the fields of
the instruction format for each instruction
i) add $t0, $s1, $s2 ii) sll $t2, $s0, 4

Design a full adder circuit.

Design a full subtractor circuit.

Draw and explain the 4-bit binary parallel adder/subtractor circuit.

Draw and explain 2-bit by 2-bit multiplier circuit.

What is the need for carry-look-ahead adder? Explain carry-look-ahead adder with neat diagram.

Design a half adder and half subtractor circuit.

Draw the multiplication hardware diagram and using the sequential multiplication algorithm, multiply 7 10 ×
610

Describe the sequential version of Multiplication algorithm in detail with diagram hardware.

Multiply 1310 × 2010 using sequential multiplication algorithm.

Explain the various instruction formats in MIPS.

Explain the following addressing modes in detail with diagram

i) Immediate addressing ii) Register addressing, iii) Base or displacement addressing, iv) PC-relative
addressing v) Pseudo direct addressing

Divide (12)10 by (3)10 using the Restoring division algorithm with step-by-step intermediate results and explain.

Describe in detail about non-restoring division algorithm with diagram and example.
Divide (12)10 by (3)10 using the Restoring division algorithm with step-by-step intermediate results and explain.

Divide (15)10 by (7)10 using the Non-restoring division algorithm with step by step intermediate results and explain

Show the IEEE 754 binary representation of the number -0.7510 in single precision floating-point format.

Add the numbers 0.5 10 and -0.437510 using binary Floating point Addition algorithm.

Draw the flowchart of floating-point addition algorithm and add the following numbers 0.3 10 and 1.310

Develop the portion of MIPS single cycle datapath which implements the fetching of instructions and
increments the program counter with neat diagram.

Develop the basic MIPS implementation with necessary multiplexors and control lines.

Explain the Main Control signals and ALU control signals with respect to MIPS single cycle datapath.

Explain the basic MIPS implementation with necessary multiplexors and control lines.

Explain datapath and its ALU control and main control signals in detail with neat diagram. (

Show how to build a data path and explain each functional units for the MIPS architecture.

Conclude the steps in constructing the datapath for R-type MIPS instruction with neat diagram.

Conclude the steps in constructing the datapath for I-type MIPS instruction with neat diagram.

Conclude the steps in constructing the datapath for store word MIPS instruction with neat diagram.

Conclude the steps in constructing the datapath for load word MIPS instruction with neat diagram.

Prioritize the three different types of hazards that will occur during the pipelined implementation of MIPS
datapath with examples.

What is Hazard? Order its types with suitable examples

Categorize the different types of pipeline hazards with examples.

Discuss the limitations of pipelining a processor’s datapath. Suggest the methods to overcome them.

Explain how instruction pipeline Works. Devise the various situation where an instruction pipeline stalls?
Illustrate with an example.

Demonstrate how instruction pipeline Works. What are the various situation where an instruction pipeline
stalls? Illustrate with an example.

Explain the steps involved in constructing the pipelined version of the MIPS datapath.

Describe the implementation of pipelined control for pipelined implementation of MIPS datapath with a neat
diagram which includes all identified control signals.

Explain the five stages involved during the load word MIPS instruction execution with respect to pipelined
implementation of the datapath with neat diagram. (
Discover the modified datapath to accommodate pipelined execution with a neat diagram.

What are the various methods for handling control hazards. Discover the concept of “Assume Branch Not
Taken” (Delayed Branch) method in detail.

What are the various methods for handling control hazards. Explain the concept of dynamic branch
prediction method in detail.

Which techniques are available for dealing with data hazards? Learn about reordering instructions in depth
with an example.

What are the various methods for handling data hazards? Determine the concept of bypassing or forwarding
in detail with example.

What exactly are the different approaches to managing control risks? Give a thorough explanation of the
dynamic branch prediction method.

Which techniques are available for dealing with data hazards? Explain in detail what is meant by bypassing
or forwarding, using an example.

Discover the usage of translation-look aside buffer with neat illustration with respect to the implementation
of page table.

Describe the concept of DMA and any one bus arbitration techniques with neat diagram.

Give a thorough explanation of memory technologies

Discover the fundamentals of cache memory and the process for accessing it in detail, using the appropriate
examples.

What are the techniques for handling interrupts from multiple devices? Explain the concept of daisy chaining with
priority.

Which methods are used to handle numerous device interrupts? Give a priority explanation of the daisy
chaining idea.

What techniques are there for managing interruptions from various devices? Learn about single-line (polling)
interrupts, multi-level interrupts, maskable and non-maskable interrupts.

What methods are there for dealing with many device interrupts? Learn about vectored interrupts in depth.

What are the techniques for handling interrupts from multiple devices? Explain the concept of interrupt
nesting.

What are the techniques for handling interrupts from multiple devices? Explain the concept of daisy chaining.

Write short notes on USB, with suitable diagram

Discover the function of a typical interface circuits. Also compare between serial and parallel interface

Discover in detail about the bus arbitration techniques

Draw and explain the timing diagram for Synchronous and Asynchronous Bus data transfer

Explain the internal hardware architecture of 8086 microprocessor with neat diagram?

Explain the bus interface unit and execution unit of 8086 microprocessor
Explain the functions of different flags and segment registers

Briefly explain the architecture of Intel 8086 with neat diagram

Explain the various addressing modes of 8086 microprocessor with examples?

Briefly explain the various Instruction set of 8086

Explain Data transfer, arithmetic and branch instructions?

Write short note about assembler directives?

Discuss about instruction format and different addressing modes of 8086

What is an assembler directive? Explain following assembler directives.

(i) ORG (ii) DT (iii) GROUP (iv) SEGMENT (v) EQU

Discuss how pipelined architecture is implemented in 8086

Describe interrupt structure of 8086 microprocessor in brief

Write an 8086 program to find the sum of 5 numbers

Write an 8086 program to multiply 2 8 bit numbers

Find the status of the CF and ZF flags after the execution of following set of
instructions.
Assume AX=5260H
(i) ADD AX, 4841 H
(ii) CMP AX,5261H
(iii) XOR AL, AL
(iv) MOV AL, 77 H

Define interrupt and their two classes? Write in detail about interrupt service routine?

i. Compare macros and procedures with suitable examples

ii. Give the assembly language implementation of the following:
(a) FOR LOOP (b) REPEAT (c) IF-THEN-ELSE

Draw the internal architecture of 8086 microprocessor and explain its Bus Interface Unit (BIU).

Give an example for the 8086 instructions: AAA, CWD, JNBE, LAHF, MOVS, RCL, ROL and SAHF

Draw and discuss the interrupt structure of 8086

Add the numbers 0.5 10 and -0.437510 using binary Floating point Addition algorithm.

Draw the flowchart of floating-point addition algorithm and add the following numbers 0.3 10 and 1.310

i) Assume that the variables f anf g are assigned to register $s0 and $s1 respectively. Assume that base
address of the array A is in register $s2. Assume f is zero initially
F = g – A[4]
A[5] = f + 100
Translate the above C statement into MIPS code .how many MIPS assembly instructions are needed to
perform the C statements and how many different registers are needed to carry out the C statements?
ii) Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4,
respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively.
C Code:
f = g + A[B[4]-B[3]];
For the C statement above, what is the corresponding MIPS assembly code?

i) Write the equivalent minimal number of MIPS assembly instruction for the following
f=f+g+h+i+j+2;
f=q+(h+5);
Translate the above C statement into MIPS code. How many MIPS assembly instructions are needed to
perform the C statements and how many different registers are needed to carry out the C statements?
ii) Assume that the variables f anf g are assigned to register $s0 and $s1 respectively. Assume that base
address of the array A is in register $s2. Assume f is zero initially
F = g – A[4]
A[5] = f + 100
Translate the above C statement into MIPS code. How many MIPS assembly instructions are needed to
perform the C statements and how many different registers are needed to carry out the C statements?

i) Assume that i and k correspond to registers $s3 and $s5 and the base of the array save is in $s6. What is
the MIPS assembly code corresponding to this C segment?
while (save[i] == k)
i += 1;
ii) In the following code segment, f, g, h, i, and j are variables. If the five variables f through j correspond
to the five registers $s0 through $s4, what is the compiled MIPS code for this C if statement?
if (i == j) f = g + h; else f = g – h;

i) Assume that the variables f anf g are assigned to register $s0 and $s1 respectively. Assume that base
address of the array A is in register $s2. Assume f is zero initially
F = g – A[4]
A[5] = f + 100
Translate the above C statement into MIPS code .how many MIPS assembly instructions are needed to
perform the C statements and how many different registers are needed to carry out the C statements?
ii) Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4,
respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively.
C Code:
f = g + A[B[4]-B[3]];
For the C statement above, what is the corresponding MIPS assembly code?

Explain the steps in designing the floating-point multiplication hardware in detail with the following
example: 1.110×1010 X 9.200×10-5

Using Booth’s bit-pair recoding technique, multiply -710 × -310

Multiply (-1010) and (410) using Booth's algorithm.

Using Booth’s bit-pair recoding technique, multiply -910 × -710

The following sequence of instructions are executed in the basic 5-stage pipelined processor:
or r1,r2,r3
or r2,r1,r4
or r1,r1,r2
i) Indicate dependences and their type.
ii) Assume there is no forwarding in this pipelined processor. Indicate hazards and add NOP instructions to
avoid them.
iii) Assume there is full forwarding in this pipelined processor. Indicate hazards and add NOP instructions
to avoid them.

The following sequence of instructions are executed in the basic 5-stage pipelined processor:
lw $s1,40($s6)
add $s6,$s2,$s2
sw $s6,50($s1)
i) Indicate dependences and their type.
ii) Assume there is no forwarding in this pipelined processor. Indicate hazards and add NOP instructions to
avoid them.

Consider the following sequence of MIPS instructions in pipeline

sub $2, $1, $3
and $12, $2, $5
or $13, $6, $2
add $14, $2, $2
sw $15, 100($2)
i) Classify the dependencies among the instructions.
ii) Provide necessary forwarding mechanism to handle the data hazards in the above sequence through
proper diagram and control parameters.

The following sequence of instructions are executed in the basic 5-stage pipelined processor:
or r1,r2,r3
or r2,r1,r4
or r1,r1,r2
i) Indicate dependences and their type.
ii) Assume there is no forwarding in this pipelined processor. Indicate hazards and add NOP instructions to
avoid them.
iii) Assume there is full forwarding in this pipelined processor. Indicate hazards and add NOP instructions
to avoid them.

Consider the following sequence of MIPS instructions in pipeline

sub $2, $1, $3
and $12, $2, $5
or $13, $6, $2
add $14, $2, $2
sw $15, 100($2)
i) Classify the dependencies among the instructions.
ii) Provide necessary forwarding mechanism to handle the data hazards in the above sequence through proper
diagram and control parameters.

i) Consider a cache with 64 blocks and a block size of 16 bytes. To what block number does byte address
1200 map? ii) How many total bits are required for a direct-mapped cache with 16 KB of data and 4- word
blocks, assuming a 32-bit address?

Caches are important to providing a high-performance memory hierarchy

to processors. Below is a list of 32-bit memory address references, given as word
addresses.
3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253
i) For each of these references, identify the binary address, the tag, and the index given a direct-mapped
cache with two-word blocks and a total size of 8 blocks.

ii) Also list if each reference is a hit or a miss, assuming the cache is initially empty.
i) Consider a cache with 64 blocks and a block size of 16 bytes. To what block number does byte address
1200 map?
ii) How many total bits are required for a direct-mapped cache with 16 KB of data and 4- word blocks,
assuming a 32-bit address?

For the following given example resolve the data hazards.

lw $t1, 0($t0)
lw $t2, 4($t0)
add $t3, $t1,$t2
sw $t3, 12($t0)
lw $t4, 8($t0)
add $t5, $t1,$t4
sw $t5, 16($t0)
Write an 8086 ALP to sort out any given 10 numbers in ascending and descending order.