Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd Logo
Upload

Welcome to Scribd!

  • 6 views

    C0a PDF

    Uploaded by

    sreekuttynandu1311

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    C0a PDF

    Uploaded by

    sreekuttynandu1311
    6 views2 pages

    Original Title

    C0A.pdf

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    6 views2 pages

    C0a PDF

    Uploaded by

    sreekuttynandu1311

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    Module 1

    1. Compare auto increment and auto decrement addressing modes with examples
    2. Outline the steps involved in the execution of an instruction.
    3. Identify the addressing modes that can be used for representing the following higher
    level language constructs in machine level. Illustrate each addressing mode using an
    example.
    1) Arrays
    2) Pointers
    3) Constants
    4) Variables
    4. Illustrate the single bus organization of processor unit with the help of suitable
    diagrams. Explain, listing the control signals, how the following operations are
    handled in this organization.
    i) Transfer contents of register R5 to R1
    ii) ii) Move (R6), R2 (Fetch a word from memory and move it to register R2,
    when the memory address is stored in register R6)
    5. a) Outline the differences in instruction execution during straight line sequencing and
    branching using suitable examples.
    b) Differentiate between big endian and little-endian byte ordering. Consider a
    computer that has a byte addressable memory organized as 32-bit words. A program
    reads ASCII characters entered at a key board and stores them in successive byte
    locations, starting at location 1000. Show the contents of the two memory words at
    locations 1000 and 1004 after the name Johnson has been entered in case: i) Big
    Endian Byte ordering is used ii) Little Endian Byte ordering is used (ASCII
    equivalent of characters in Johnson in hex will be 4A, 6F, 68, 6E, 73,6F, 6E. You can
    indicate unused byte locations using XX.
    6. Describe auto increment and decrement addressing mode with help of example?
    7. Name the registers which are connected to both external and internal bus? What are
    the signal associated with these registers?
    8. Compare and contrast single bus and multi-bus organization of CPU?
    9. Write the three-address, two-address and one-address representations of the operation
    below with relevant assumptions, evaluate following

    (A+B) *(C+D)

    C<-[A]+[B]

    10. With the help of a neat figure, describe the data path inside the processor?
    11. Draw the diagram of single bus organization, write the control sequence for the
    instruction ADD[R2], R3 for the above-mentioned single bus organization.
    12. With a neat diagram explain the internal architecture of CPU?
    13. Enumerate the sequence of actions (control signals) involved in executing an
    unconditional branch instruction?
    14. What you mean by addressing modes, with proper examples explain in detail about
    various address modes?
    15. Write down the sequence of actions needed to fetch and execute instruction: STORE
    R1, [R2]
    16. Draw the diagram of a multi-bus organization with 3 buses, write the control sequence
    for the instruction ADD[R1], R2, R3 for the above-mentioned multi-bus organization.
    17. What are condition codes, list the different condition codes?
    Module 2
    1. How is the two-port memory organization of processor unit better when compared to
    scratch pad memory organization?
    2. Give the block diagram of circuit that implements following statements in register
    transfer logic:
    T1; C ←A
    T5: C ←B
    3. Illustrate and explain the organization of a processor unit where processor registers and
    ALU are connected through common buses. Explain how the micro operation R2 ←
    R3+R4 would be performed using this organization, where R2, R3 and R4 are processor
    registers.

    You might also like