STK672-432A-E: 2-Phase Stepping Motor Driver
STK672-432A-E: 2-Phase Stepping Motor Driver
STK672-432A-E: 2-Phase Stepping Motor Driver
kr
Overview
The STK672-432A-E is a hybrid IC for use as a unipolar, 2-phase stepping motor driver with PWM current control.
Applications
• Office photocopiers, printers, etc.
Features
• Built-in overcurrent detection function (output current OFF).
• Built-in overheat detection function (output current OFF).
• If either over-current or overheat detection function is activated, the FAULT1 signal (active low) is output.
The FAULT2 signal is used to output the result of activation of protection circuit detection at 2 levels.
• Built-in power on reset function.
• A micro-step sine wave-driven driver can be activated merely by inputting an external clock.
• External pins can be used to select 2, 1-2 (including pseudo-micro), W1-2, 2 W1-2, or 4W1-2 excitation.
• The switch timing of the 4-phase distributor can be switched by setting an external pin (MODE3) to detect either the
rise and fall, or rise only, of CLOCK input.
• Phase is maintained even when the excitation mode is switched. Rotational direction switching function.
• Supports schmitt input for 2.5V high level input.
• Incorporating a current detection resistor (0.152Ω: resistor tolerance ±2%), motor current can be set using two
external resistors.
• The ENABLE pin can be used to cut output current while maintaining the excitation mode.
• With a wide current setting range, power consumption can be reduced during standby.
• No motor sound is generated during hold mode due to external excitation current control.
• A external excitation system is used for PWM operations. Fixed current control for shifting the phase of Ach/Bch is
used for the PWM phase.
• Miniature package (provides pin compatibility with STK672-430A-E)
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
STK672-432A-E
Specifications
Absolute Maximum Ratings at Tc = 25°C
Parameter Symbol Conditions Ratings unit
Maximum supply voltage 1 VCC max No signal 52 V
Maximum supply voltage 2 VDD max No signal -0.3 to +6.0 V
Input voltage VIN max Logic input pins -0.3 to +6.0 V
Output current 1 IOP max 10μs, 1 pulse (resistance load) 10 A
Output current 2 IOH max VDD=5V, CLOCK≥200Hz 2.5 A
Allowable power dissipation 1 PdMF max With an arbitrarily large heat sink. Per MOSFET 7.3 W
Allowable power dissipation 2 PdPK max No heat sink 2.8 W
Operating substrate temperature Tc max 105 °C
Junction temperature Tj max 150 °C
Storage temperature Tstg -40 to +125 °C
No.A1586-2/21
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STK672-432A-E
Continued from preceding page.
Parameter Symbol Conditions min typ max unit
Package Dimensions
unit:mm (typ)
24.2
(18.4) 4.5
(R1.47)
14.4
14.4
(11.0)
11.0
1 19
(3.5)
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STK672-432A-E
IOH - Tc
3.0
1.5
1.0
0.5
0
0 10 20 30 40 50 60 70 80 90 100 110
Operating Substrate Temperature, Tc- °C ITF02592
Notes
• The current range given above represents conditions when output voltage is not in the avalanche state.
• If the output voltage is in the avalanche state, see the allowable avalanche energy for STK672-4** series hybrid ICs
given in a separate document.
• The operating substrate temperature, Tc, given above is measured while the motor is operating.
Because Tc varies depending on the ambient temperature, Ta, the value of IOH, and the continuous or intermittent
operation of IOH, always verify this value using an actual set.
• The Tc temperature should be checked in the center of the metal surface of the product package.
No.A1586-4/21
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STK672-432A-E
Block Diagram
VDD MOI FAULT2 Vref A AB B BB
9 7 8 19 4 5 3 1
MODE3 17
Phase
RESETB 14 excitation Overcurrent
Power-on reset
signal detection
generator
ENABLE 15 Overheating
Latch detection
Reference clock -
Oscillator generator PWM +
control
-
FAULT1 16 +
2 P.G1
S.G 18 6 P.G2
SUB
STK672-432A-E
VDD=5V
10 9
11
17 2-phase stepping motor
CLOCK 12
A
4
ENABLE 15 AB
5
CWB 13
VCC=24V
B
MOI 7 3
RESETB BB
14 1 +
C01
100μF
R01
+ Vref
C02 19 P.G2
2
10μF R02
6 P.GND
8 16 18 P.G1
S.G
FAULT1
FAULT2
No.A1586-5/21
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STK672-432A-E
Precautions
[GND wiring]
• To reduce noise on the 5V/24V system, be sure to place the GND of C01 in the circuit given above as close as
possible to Pin 2 and Pin 6 of the hybrid IC.
In addition, in order to set the current accurately, the GND side of RO2 of Vref must be connected to the shared
ground terminal used by the Pin 18 (S.G) GND, P.G1 and P.G2.
[Input pins]
• When VDD is being input, for each input pin, measures must be taken so that a negative voltage less than -0.3V is not
applied to Pin 18. Measures must also be taken so that a voltage equal to or greater than VDD is not input.
• High voltage input other than VDD, MOI, FAULT1, and FAULT2 is 2.5V.
• Pull-up resistors are not connected to input pins. Pull-down resistors are attached. When controlling the input to the
hybrid IC with the open collector type, be sure to connect a pull-up resistor (1 to 20kΩ).
Be sure to use a device (0.8V or less, low level, when IOL=5mA) for the open collector driver at this time that has an
output voltage specification such that voltage is pulled to less than 0.8V at low level.
• When using the power on reset function built into the hybrid IC, be sure to directly connect Pin 14 to VDD.
• We recommend attaching a 1,000pF capacitor to each input to prevent malfunction during high-impedance input. Be
sure to connect the capacitor near the hybrid IC, between Pin 18 (S, G).
When input is fixed low, directly connect to Pin 18. When input is fixed high, directly connect to VDD.
5V 5V
RO1
RO1
Vref
Vref
R3 RO2 R3
RO2
No.A1586-6/21
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STK672-432A-E
• Motor current peak value IOH setting
IOH
Function Table
M2 0 0 1 1
CLOCK Edge Timing for
M1
0 1 0 1 Phase Switching
M3
2-phase excitation 1-2-phase excitation W1-2 phase 2W1-2 phase
1 CLOCK rising edge
selection (IOH=100%) excitation excitation
1-2 phase excitation W1-2 phase 2W1-2 phase 4W1-2 phase
0 CLOCK both edges
(IOH=100%, 71%) excitation excitation excitation
IOH=100% results in the Vref voltage setting, IOH.
During 1-2 phase excitation, the hybrid IC operates at a current setting of IOH=100% when the CLOCK signal rises.
Conversely, pseudo micro current control is performed to control current at IOH=100% or 71% at both edges of the
CLOCK signal.
CWB pin
Forward/CW 0
Reverse/CCW 1
No.A1586-7/21
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STK672-432A-E
Timing Charts
2-phase excitation timing charts (M3=1) 1-2-phase excitation timing charts (M3=1)
1
M1 M1
0 0
M2 0
M2 0
1 1
M3 M3
0 0
RESET RESET
CWB CWB
CLK CLK
MOSFET Gate Signal
A A
B B
B B
MOI MOI
100% 100%
Comparator Reference Voltage
A phase A phase
Vref Vref
100% 100%
71% 71%
B phase B phase
Vref Vref
ITF02580 ITF02581
W1-2-phase excitation timing charts (M3=1) 2W1-2-phase excitation timing charts (M3=1)
1
M1 M1
0 0
1 1
M2 0
M2 0
1 1
M3 M3
0 0
RESET RESET
CWB CWB
CLK CLK
MOSFET Gate Signal
A A
A A
B B
B B
MOI MOI
100% 100%
97%
92% 92%
Comparator Reference Voltage
83%
71% 71%
55%
40% 40%
A phase 20%
Vref A phase
Vref
100% 100%
97%
92% 92%
83%
71% 71%
55%
40% 40%
B phase 20%
Vref B phase
Vref
ITF02582 ITF02583
No.A1586-8/21
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STK672-432A-E
1-2-phase excitation timing charts (M3=0) W1-2-phase excitation timing charts (M3=0)
1
M1 M1
0 0
M2 0
M2 0
M3 M3
0 0
RESET RESET
CWB CWB
CLK CLK
MOSFET Gate Signal
A A
B B
B B
MOI MOI
100% 100%
92%
Comparator Reference Voltage
40%
A phase A phase
Vref Vref
100% 100%
92%
71% 71%
40%
B phase B phase
Vref Vref
ITF02584 ITF02585
2W1-2-phase excitation timing charts (M3=0) 4W1-2-phase excitation timing charts (M3=0)
1
M1 M1
0 0
1 1
M2 0
M2 0
M3 M3
0 0
RESET RESET
CWB CWB
CLK CLK
MOSFET Gate Signal
A A
A A
B B
B B
MOI MOI
100% 100%
97% 97% 95%
92% 92% 88%
Comparator Reference Voltage
No.A1586-9/21
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STK672-432A-E
Usage Notes
1. I/O Pins and Functions of the Control Block
[Pin description]
HIC pin Pin Name Function
7 MOI Output pin for the excitation monitor
19 Vref Current value setting
10 MODE1
11 MODE2 Excitation mode selection
17 MODE3
12 CLOCK External CLOCK (motor rotation instruction)
13 CWB Sets the direction of rotation of the motor axis
14 RESETB System reset
15 ENABLE Motor current OFF
16 FAULT1
Overcurrent/over-heat detection output
8 FAULT2
[ENABLE (Forcible OFF control of excitation drive output A, AB, B, and BB, and selecting operation/hold status
inside the HIC)]
ENABLE=1: Normal operation
When ENABLE=0: Motor current goes OFF, and excitation drive output is forcibly turned OFF.
The system clock inside the HIC stops at this time, with no effect on the HIC even if input pins other than RESET
input vary. In addition, since current does not flow to the motor, the motor shaft becomes free.
If the CLOCK signal used for motor rotation suddenly stops, the motor shaft may advance beyond the control position
due to inertia. A SLOW DOWN setting where the CLOCK cycle gradually decreases is required in order to stop at the
control position.
[MODE1, MODE2, and MODE3 (Selecting the excitation mode, and selecting one edge or both edges of the CLOCK)]
Excitation select mode terminal (See the sample application circuit for excitation mode selection), selecting the
CLOCK input edge(s).
Mode setting active timing
Do not change the mode within 7μs of the input rising or falling edge of the CLOCK signal.
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STK672-432A-E
[Vref (Voltage setting to be used for the current setting reference)]
• Pin type: Analog input configuration, input pull-down resistor 100kΩ
Input voltage is in the voltage range of 0.14V to 1.48V.
[Input timing]
The control IC of the driver is equipped with a power on reset function capable of initializing internal IC operations
when power is supplied. A 4V typ setting is used for power on reset. Because the specification for the MOSFET gate
voltage is 5V±5%, conduction of current to output at the time of power on reset adds electromotive stress to the
MOSFET due to lack of gate voltage. To prevent electromotive stress, be sure to set ENABLE=Low while VDD,
which is outside the operating supply voltage, is less than 4.75V.
In addition, if the RESETB terminal is used to initialize output timing, be sure to allow at least 10μs until CLOCK
input.
4Vtyp 3.8Vtyp
Control IC power (VDD) rising edge
5V 5V
Output pin
Pin 8 50kΩ
10kΩ
50kΩ
The input pins of this driver all use Schmitt input. Typical specifications at Tc=25°C are given below. Hysteresis
voltage is 0.3V (VIHa-VILa).
1.8Vtyp
1.5Vtyp
Input voltage
VIHa VILa
No.A1586-11/21
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STK672-432A-E
Input voltage specifications are as follows.
VIH=2.5Vmin
VIL=0.8Vmax
<Configuration of the Vref input pin> <Configuration of the FAULT1 output pin>
5V
Output pin
Pin 16
Vref/4.9
Overcurrent
-
+
Amplifier
Input pin Thermal shutdown
100kΩ Pin 19
VSS VSS
VSS
FAULT2 output
Output is resistance divided (2 levels) and the type of abnormality detected is converted to the corresponding output
voltage.
• Overcurrent: 2.5V(typ)
• Overheat: 3.3V(typ)
Abnormality detection can be released by a RESETB operation or turning VDD voltage on/off.
[MOI output]
The output frequency of this excitation monitor pin varies depending on the excitation mode. For output operations, see
the timing chart.
No.A1586-12/21
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STK672-432A-E
2. Overcurrent Detection and Overheat Detection Functions
Each detection function operates using a latch system and turns output off. Because a RESET signal is required to
restore output operations, once the power supply, VDD, is turned off, you must either again apply power on reset with
VDDON or apply a RESETB=High→Low→High signal.
[Overcurrent detection]
This hybrid IC is equipped with a function for detecting overcurrent that arises when the motor burns out or when there
is a short between the motor terminals.
Overcurrent detection occurs at 3.4A typ with the STK672-432A-E.
Overcurrent detection begins after an interval of no detection (a dead time of 1.25μs typ) during the initial ringing part
during PWM operations. The no detection interval is a period of time where overcurrent is not detected even if the
current exceeds IOH.
[Overheat detection]
Rather than directly detecting the temperature of the semiconductor device, overheat detection detects the temperature
of the aluminum substrate (144°C typ).
Within the allowed operating range recommended in the specification manual, if a heat sink attached for the purpose of
reducing the operating substrate temperature, Tc, comes loose, the semiconductor can operate without breaking.
However, we cannot guarantee operations without breaking in the case of operations other than those recommended,
such as operations at a current exceeding IOH max that occurs before overcurrent detection is activated.
No.A1586-13/21
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STK672-432A-E
3. Allowable Avalanche Energy Value
VDS
ID
tAVL: Time of avalanche operations
ITF02557
Figure 1 Output Current, ID, and Voltage, VDS, Waveforms 1 of the STK672-4** Series when Driving a 2-
Phase Stepping Motor with Constant Current Chopping
When operations of the MOSFET built into STK672-4** Series ICs is turned off for constant current chopping,
the ID signal falls like the waveform shown in the figure above. At this time, the output voltage, VDS, suddenly
rises due to electromagnetic induction generated by the motor coil.
In the case of voltage that rises suddenly, voltage is restricted by the MOSFET VDSS. Voltage restriction by
VDSS results in a MOSFET avalanche. During avalanche operations, ID flows and the instantaneous energy at
this time, EAVL1, is represented by Equation (3-1).
During STK672-4** Series operations, the waveforms in the figure above repeat due to the constant current
chopping operation. The allowable avalanche energy, EAVL, is therefore represented by Equation (3-2) used to
find the average power loss, PAVL, during avalanche mode multiplied by the chopping frequency in Equation
(3-1).
For VDSS, IAVL, and tAVL, be sure to actually operate the STK672-4** Series and substitute values when
operations are observed using an oscilloscope.
Ex. If VDSS=110V, IAVL=1A, tAVL=0.2μs when using a STK672-432A-E driver, the result is:
PAVL=110×1×0.5×0.2×10-6×50×103=0.55W
VDSS=110V is a value actually measured using an oscilloscope.
The allowable loss range for the allowable avalanche energy value, PAVL, is shown in the graph in Figure 3.
When examining the avalanche energy, be sure to actually drive a motor and observe the ID, VDSS, and tAVL
waveforms during operation, and then check that the result of calculating Equation (3-2) falls within the
allowable range for avalanche operations.
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(2) ID and VDSS Operating Waveforms in Non-avalanche Mode
Although the waveforms during avalanche mode are given in Figure 1, sometimes an avalanche does not result
during actual operations.
Factors causing avalanche are listed below.
• Poor coupling of the motor’s phase coils (electromagnetic coupling of A phase and AB phase, B phase and
BB phase).
• Increase in the lead inductance of the harness caused by the circuit pattern of the P.C. board and motor.
• Increases in VDSS, tAVL, and IAVL in Figure 1 due to an increase in the supply voltage from 24V to 36V.
If the factors above are negligible, the waveforms shown in Figure 1 become waveforms without avalanche as
shown in Figure 2.
Under operations shown in Figure 2, avalanche does not occur and there is no need to consider the allowable loss
range of PAVL shown in Figure 3.
VDS
ID
ITF02558
Figure 2 Output Current, ID, and Voltage, VDS, Waveforms 2 of the STK672-4** Series when Driving
a 2-Phase Stepping Motor with Constant Current Chopping
PAVL - IOH
Average power loss in the avalanche state, PAVL- W
4.0
3.5 Tc=
80°
C
3.0
2.5
105
°C
2.0
1.5
1.0
0.5
0
0 0.5 1.0 1.5 2.0 2.5
Motor current,IOH - A ITF02593
Note:
The operating conditions given above represent a loss when driving a 2-phase stepping motor with constant current
chopping.
Because it is possible to apply 2.6W or more at IOH=0A, be sure to avoid using the MOSFET body diode that is used to
drive the motor as a zener diode.
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STK672-432A-E
4. Calculating HIC Internal Power Loss
The average internal power loss in each excitation mode of the STK672-432A-E can be calculated from the following
formulas. *1
IOH
0A
t1 t2 t3
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Fixed current control time, t2, for each excitation mode
(1) 2-phase excitation t2 = (2÷CLOCK) - (t1 + t3)·······························(4-9)
(2) 1-2 phase excitation t2 = (3÷CLOCK) - t1·········································(4-10)
(3) W1-2 phase excitation t2 = (7÷CLOCK) - t1·········································(4-11)
(4) 2W1-2 phase excitation (and 4W1-2 phase excitation) t2 = (15÷CLOCK) - t1·······································(4-12)
For the values of Vsat and Vdf, be sure to substitute from Vsat vs IOH and Vdf vs IOH at the setting current value IOH.
(See pages to follow)
Then, determine if a heat sink is necessary by comparing with the ΔTc vs Pd graph (see next page) based on the
calculated average output loss, HIC.
For heat sink design, be sure to see STK672-432A-E.
The HIC average power, PdAVex described above, represents loss when not in avalanche mode. To add the loss in
avalanche mode, be sure to add PAVL (4-13, 14) using the formula (3-2) for average power loss , PAVL, for STK672-
4** avalanche mode, described below to PdAVex described above.
When using this IC without a fin, always check for temperature increases in the set, because the HIC substrate
temperature, Tc, varies due to effects of convection around the HIC.
The sum of PAVL values for each excitation mode is multiplied by the constants given below and added to the average
internal HIC loss equation, except in the case of 2-phase excitation.
1-2 excitation mode and higher: PAVL(1)=0.7×PAVL····································································· (4-13)
During 2-phase excitation and motor hold: PAVL(1)=1×PAVL ······················································· (4-14)
No.A1586-17/21
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STK672-432A-E
Vsat - IOH
1.0
°C
05
=1
0.6
Tc
C °
25
0.4
0.2
0
0 0.5 1.0 1.5 2.0 2.5 3.0
Output current, IOH - A ITF02594
Vdf- IOH
1.4
1.2
25°C
Tc=
Forward voltage, Vdf - V
1.0
°C
105
0.8
0.6
0.4
0.2
0
0 0.5 1.0 1.5 2.0 2.5 3.0
Output current, IOH - A ITF02595
Substrate temperature rise, ΔTc (no heat sink) - Internal average power dissipation, PdAV
ΔTc - PdAV
80
70
Substrate temperature rise, ΔTc - °C
60
50
40
30
20
10
0
0 0.5 1.0 1.5 2.0 2.5 3.0
Hybrid IC internal average power dissipation, PdAV - W ITF02717
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5. Thermal design
IO1
Motor phase current
(sink side)
IO2
0A
-IO1
T1 T2 T3
T0
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Figure 2 Substrate temperature rise, ΔTc - Internal average power dissipation, PdAV
ΔTc - PdAV
80
70
50
40
30
20
10
0
0 0.5 1.0 1.5 2.0 2.5 3.0
Hybrid IC internal average power dissipation, PdAV - W ITF02717
θc-a - S
100
Heat sink thermal resistance, θc-a - °C/W
7
5
Wit
10 h no
surf
7 Wit ace
h a fl fi
nish
5 at b
l ack
surf
3 ace
fini
2
sh
1.0
10 2 3 5 7 100 2 3 5 7 1000
Heat sink area, S - cm2 ITF02554
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6. Mitigated Curve of Package Power Loss, PdPK, vs. Ambient Temperature, Ta
Package power loss, PdPK, refers to the average internal power loss, PdAV, allowable without a heat sink.
The figure below represents the allowable power loss, PdPK, vs. fluctuations in the ambient temperature, Ta.
Power loss of up to 2.8W is allowable at Ta=25°C, and of up to 1.5W at Ta=60°C.
PdPK - Ta
3.0
2.0
1.0
1.5
0.5
0
0 20 40 60 80 100 120
Ambient Temperature, Ta - °C ITF02718
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with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of June, 2011. Specifications and information herein are subject
to change without notice.
PS No.A1586-21/21
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