Analog Circuits

PHY 379

Bipolar Junction
Transistor (BJT)
- DC Analysis
OBJECTIVES

To Understand
•Concept of Operating point and stability
•Analyzing various biasing circuits and their
comparison with respect to stability
Operation Region

 Linear (Active) region:

– Base-emitter junction forward-bias
– Base-collector junction reverse-bias
 Cutoff region:
– Base-emitter junction reverse-bias
– Base-collector junction reverse-bias
 Saturation region:
– Base-emitter junction forward-bias
– Base-collector junction forward-bias
 Q-Point (Static Operating Point)

• The values of the

parameters IB, IC and VCE
help in determining
‘Operating point’ or
Quiescent point (Q-point)
of the transistor. Q-point

• The intersection of the dc

bias value of IB with the dc
load line determines the Q-
point.
• It is desirable to have the
Q-point centered on the
load line. Why?

• Midpoint biasing (centered

Q-point) allows for
optimum ac operation of
the amplifier.
 Biasing - Introduction

• The analysis or design of a transistor amplifier requires knowledge

of both the dc and ac response of the system.
• In fact, the amplifier increases the strength of a weak signal by
transferring the energy from the applied DC source to the weak
input ac signal.

The analysis or design of any electronic amplifier therefore has two

components:
• The dc portion and
• The ac portion
During the design stage, the choice of parameters for the required dc
levels that will affect the ac response are made.
 Design and Analysis

Design: Analysis:
 IB, IC, VCE and VCC, or  The circuit values
IC , VCE and β are VCC, RB and RC) are
given, given
 Values of RB, RC are  The values of IB, IC ,
obtained by applying VCE are obtained by
KVL to the input and applying KVL to the
output loops. input and output
* Vcc is supply voltage loops.
 Common-Emitter BJT
Amplifier Configuration

β range from 50 to over 400

+ output
VCE
input +
VBE −
−
 Why use the
Common-Emitter Amplifier?

 The common-emitter amplifier exhibits high

voltage and current gain.

 β range from 50 to over 400

 Common-Emitter configuration will therefore be

used in our BJT amplification discussions
henceforth
 Biasing Circuit

• Once the desired dc current and voltage levels have been

identified, a network must be constructed that will establish the
desired values of IB, IC and VCE.
• Such a network is known as biasing circuit. A biasing network
has to preferably make use of one power supply to bias both
junctions of the transistor.
Purpose of the DC biasing circuit
• To turn the device (transistor) “ON”
• To place it in operation in the region of its characteristic where
the device operates most linearly, i.e. to set up the initial dc
values of IB, IC, and VCE
Recall Important Equations

VBE = 0.7 V ( for npn ) VEB = 0.7 V ( for pnp )

IC ≈ I E
I C = βI B
I E = ( β +1) I B
I E = IC + I B
BJT Biasing Schemes

 There are many types of biasing Schemes

 The subtopic will cover:
– Fixed bias scheme
– Emitter bias scheme
– Voltage-divider bias scheme
Fixed Bias Scheme

 The simplest dc biasing scheme

• For dc analysis, open all the
capacitance (treat Capacitors
as open circuit).
Fixed Bias Scheme

DC equivalent circuit:
 Ignoring the ac input &
output
 Ignoring the capacitor C1
and C2 at ac input &
output terminal
 Emitter is grounded

 So, VE = 0
 Fixed Bias Scheme:
DC Analysis
 Applying KVL to the input loop:
VCC = IBRB + VBE
 From the above equation, deriving IB,
we get, IB = [VCC – VBE] / RB
 The selection of RB sets the level of
base current IB for the operating point.
 Applying KVL to the output loop:
VCC = ICRC + VCE
 Thus, VCE = VCC – ICRC
V E =0
 In circuits where emitter is grounded,
VCE = VE and VBE = VB
Example

 The circuit:

Que: Determine IBQ

Example
 Given the fixed bias circuit with VCC = 12 V,
RB = 240 kΩ, RC = 2.2 kΩ and β = 75.
Determine the values of operating point

 Determine IBQ and ICQ

 Determine VCEQ
 Determine VB and VC
 Determine VBC
Example

 Determine IBQ and ICQ:

 For IBQ: (Input loop) V CC −V B
I B = I B=
Q RB
where as: V BE =0 . 7=V B−V E
∴V B=0 . 7
12−0 .7
so: I B =I B = =47 .08 μA
Q 240 k
 For ICQ: I C = βI BQ =( 50 )( 47 .08 μ )=2. 35 mA
Q
Example

 Determine VCEQ:
V CE =V C −V E =V C
Q

V CC −V C
where as: I C =2. 35m= =
RC
12−V C
=
2 . 2k
∴V C =6 .83
so: V CE =V C =6 .83 V
Q
Example

 Determine VB and VC:

 Taken from Solution :
V B=0 .7 V
V C =6 .83 V
Example

 Determine VBC:

V BC=V B −V C =0 .7−6. 83=−6 .13 V

Transistor Saturation

 Saturation means any system that have

reached their maximum value

 Saturation region is where the base-collector

junction is in forward bias

 When this happens, the output signal will be

distorted
Transistor Saturation

 When the transistor is biased such that IB is

very high so as to make IC very high such that
ICRC drop is almost VCC and VCE is almost 0, the
transistor is said to be in saturation.
Transistor Saturation

Actual Approximate

Notice that in saturation region, VCE = 0

Saturation Level

 For the fixed-bias configuration, to determine

the saturation current, IC(sat), the equivalent
circuit is:
Saturation Level

 The calculation:
V CE =0=V C −V E =V C−0
∴V C =0
 For that, the saturation current becomes:
V CC −V C V CC −0
IC = =
sat RC RC
V CC
∴I C =
sat RC
Saturation Level: Verification

 Whenever a fixed bias circuit is analyzed, the

value of ICQ obtained could be verified with the
value of
ICSat = VCC / RC
to investigate whether the transistor is operating
in the active region or not.

 In the active region, ICQ = ( ICSat /2)

Load-Line Analysis

 A fixed bias circuit with given values of VCC, RC

and RB can also be analyzed ( means,
determining the values of IBQ, ICQ and VCEQ)
using the concept of load line.

 Here the input loop KVL equation is not used

for the purpose of analysis, instead, the output
characteristics of the transistor used in the
given circuit and output loop KVL equation are
made use of.
 Load-Line Analysis
 The method of load line analysis is as below:
1. Consider the equation VCE = VCC – ICRC. This
relates VCE and IC for the given IB and RC

2. Also, we know that, VCE and IC are related through

output characteristics

 We know that the equation, VCE = VCC – ICRC

represents a straight line which can be plotted on
the output characteristics of the transistor.

 Such line drawn as per the above equation is

known as load line, the slope of which is decided
by the value of RC ( the load).
 Load-Line Analysis
 Given the biasing scheme and the device
characteristic as shown below:
 Load-Line Analysis
 A line is drawn from vertical axis to the horizontal axis (recall
Load-Line Analysis for diode)

 The point on the horizontal axis would be IC = 0 (VCC,0)

(notice that the point is in cutoff-region)

 The point on the vertical axis would be VCE = 0 (0, VCC / RC).
(notice that the point is in saturation-region)
 The load line intersects the output characteristics at various
points corresponding to different IBs. The actual operating
point is established for the given IB.
Load-Line Analysis

VCE = VCC – ICRC

 For IC = 0:
𝑉𝑉𝐶𝐶𝐶𝐶 − 𝑉𝑉𝐶𝐶𝐶𝐶
𝐼𝐼𝐶𝐶 = =0
𝑅𝑅𝐶𝐶

 Resulting in:

V CE =V CC (cutoff-region )
Load-Line Analysis

VCE = VCC – ICRC

 For VCE = 0,
V CC
IC =
sat RC
 As a conclusion, the load-line analysis for fixed-bias
circuit results in:
– For IC = 0: V CE =V CC (cutoff-region )

– For VCE = 0:
V CC
IC = (saturation region )
sat RC
Load-Line Analysis

 The characteristic becomes:

Q-point is establish
from the given IB
Q point variation

Q-point
A
Q point variation

 As IB is varied, the Q point shifts accordingly on the load line

either up or down depending on how IB increased or
decreased respectively.

 As RC is varied, the Q point shifts to left or right along the

same IB line since the slope of the line varies. As RC
increases, slope reduces ( slope is -1/RC) which results in
shift of Q point to the left meaning no variation in IC and
reduction in VCE.
 Thus if the output characteristics is known, the analysis of
the given fixed bias circuit or designing a fixed bias circuit is
possible using load line analysis as mentioned above.
 Example
 Given the load-line for fixed-bias scheme
 Determine VCC, RC and RB
Example

 For IC = 0:
V CE =V CC =20

 For VCE = 0:
V CC 20
IC= = =10 m
RC RC
∴ RC =2 k Ω
Example

 From the load-line given, Q-point is approximately at

IB = 25 μA
 For a fixed-bias scheme, IB is defined by the
equation: V CC −V B
I B=
RB
 Since that VE = 0, resulting in VBE = VB = 0.7, RB can
be calculated from the above equation:
20−0 . 7
25 μ=
RB
∴ RB =772 k Ω
Emitter Bias Scheme

 Emitter bias is a biasing

circuit very similar to
fixed bias circuit with an
emitter resistor added
to it

 Added resistor (RE) at

emitter improves
stability
 Emitter Bias Scheme
 Writing KVL around the input loop we get,
VCC = IBRB + VBE + IERE (1)
 We know that, IE = (β+1)IB (2)
 Substituting this in (1), we get,
VCC = IBRB + VBE + (β+1)IBRE
VCC – VBE = IB(RB + (β+1) RE)
 Solving for IB:
IB = (VCC – VBE ) /[(RB + (β+1) RE)]
 The expression for IB in a fixed bias
circuit was, IB = (VCC – VBE ) /RB
 Emitter Bias Scheme:
Equivalent input loop
 REI in the above
circuit is (β+1)RE
which means that, the
emitter resistance that
is common to both
loops appears as
such a high resistance
in the input loop.

 Thus Ri = (β+1)RE
 Emitter Bias Scheme:
Output loop(CE loop)
Applying KVL,
VCC = ICRC + VCE + IERE
IC is almost same as IE
Thus,
VCC = ICRC + VCE + ICRE
= IC (RC + RE) +VCE
VCE = VCC - IC (RC + RE)
Since emitter is not connected directly to
ground, it is at a potential VE, given by,
VE = IERE
VC = VCE + VE OR VC = VCC – ICRC

Also, VB = VCC – IBRB OR VB = VBE + VE

Example
(Refer to Textbook for Solution)

 Determine IB, IC, VCE, VC, VE, VB & VBC for the emitter bias
circuit below:
 Improved bias stability
a) In a fixed bias circuit, IB does not
 The introduction of a vary with β and therefore
resistor RE at the whenever there is an increase in
Emitter makes the dc β, IC increases proportionately,
bias currents and and thus VCE reduces making
voltages remain closer the Q point to drift towards
to their set values even saturation.
with variation in
b) In an emitter bias circuit, as β
– transistor beta
increases, IB reduces,
– temperature maintaining almost same IC and
VCE thus stabilizing the Q point
against β variations.
Saturation Level

 For the emitter-bias

configuration, to
determine the
saturation current,
IC(sat), the equivalent
circuit is:
Saturation Level

 The calculation:
V CE =0=V C −V E
∴V C =V E
 And: I C ≈ I E
 For that, the saturation current becomes:
V CC −V CE −0 V CC −0−0
IC = =
sat RC + R E RC + R E
V CC
∴IC =
sat RC + RE
Load-Line Analysis

 For VCE = 0, the transistor will be in saturation region

 Taking the transistor saturation equation:
V CC
IC =
sat RC + RE
 For IC = 0:
IC≈ IE
V CC −V CE −0
IC= =0
RC + RE
∴V CE =V CC
Load-Line Analysis

 So, the load-line

becomes:
 Voltage-Divider Bias Scheme

 The configuration:
 Added R2 for RB
connected to ground
 Two kind of analysis for
voltage-divider bias:
– Exact Analysis
– Approximate Analysis
 Exact Analysis
This method is always valid
Must be used when R2 > 0.1βRE

 Thevenin equivalent circuit is applied for VCC, ground, R1 and

R2 at base terminal VB
 The circuit at base terminal becomes:
Exact Analysis

 RTH and ETH must be determined for

Thevenin equivalent circuit
– Determining RTH - Determining ETH

Rth = R1| | R2
Rth = R1 R2 / (R1 + R2) Eth = VR2 = VCC.R2 / (R1 + R2)
Exact Analysis

 The Thevenin equivalent circuit at base

terminal becomes:
Exact Analysis

 Applying KVL to the input loop

(Eth – VBE) = IB [ Rth +( β + 1) RE ]

IB = ( Eth – VBE) / [ Rth +( β + 1) RE ]

Exact Analysis

 Applying KVL to the output loop

VCC = ICRC + VCE + IERE

IE ≅ IC
Thus,
VCE = VCC – IC (RC + RE)
Note that this is similar to emitter bias circuit.
Example
(Refer to Textbook for Solution)

 Determine VCE and IC

Saturation Level

 The saturation level for the voltage-divider

bias is the same as for the emitter bias
configuration due to the existence of RC and
RE
𝑉𝑉𝐶𝐶𝐶𝐶
∴ 𝐼𝐼𝐶𝐶𝑠𝑠𝑠𝑠𝑠𝑠 =
𝑅𝑅𝐶𝐶 + 𝑅𝑅𝐸𝐸

𝑤𝑤𝑤𝑤𝑤𝑤𝑤𝑤𝑤 𝑉𝑉𝐶𝐶𝐸𝐸 =0
Load Line Analysis

 As for the load-line analysis, the cutoff region

still resulting in the same result as the fixed
bias and emitter bias configuration:
V CE =V CC ∣I
C =0

 And for the saturation region:

𝑉𝑉𝐶𝐶𝐶𝐶
∴ 𝐼𝐼𝐶𝐶𝑠𝑠𝑠𝑠𝑠𝑠 =
𝑅𝑅𝐶𝐶 + 𝑅𝑅𝐸𝐸
Load-Line Analysis
 So, the load-line becomes:
Bias Stabilization

Fixed-bias
− β dependent
− not stable Emitter-bias Voltage-divider
− stabilization bias
increase − β independent
− still β dependent − stabilize
Example
(Refer to Textbook for Solution)

 Determine the all resistors value in designing a emitter-bias

configuration