Chapter 1 - Introduction To Digital System Design

HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

No.1 Vo Van Ngan Street, Thu Duc Dist., HCMC, VN
DIGITAL IC DESIGN
USING HDL
NGUYEN THANH NGHIA

9/27/2021 11
NGUYEN THANH NGHIA
Administration
1. Instructor: Thanh-Nghia Nguyen.
Mail: nghiant@hcmute.edu.vn
https://sites.google.com/a/hcmute.edu.vn/thanh-nghia-nguyen/
Facebook: BMDTCNYS-DHSPKT
Faculty: http://feee.hcmute.edu.vn
2. Textbook: RTL HARDWARE DESIGN

USING VHDL - PONG P.CHU.
NGUYEN THANH NGHIA 2
Administration
3. Grading:
 Midterm : 50%
o Online
o Paper Test
o Project
o Attending
 Final Exam: 50%
4. Syllabus.
Administration
5. File name: hovaten_TuanX.rar
6. Deadline: .

HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering
No.1 Vo Van Ngan Street, Thu Duc Dist., HCMC, VN
CHAPTER 1:
INTRODUCTION TO
DIGITAL SYSTEM DESIGN
NGUYEN THANH NGHIA

9/27/2021 55
NGUYEN THANH NGHIA
Outline
1. Introduction.
2. Device Technologies.
3. System Representation.
4. Comparison of Technologies
5. Levels Of Abstraction.
6. Development Tasks And Eda Software.

Chapter 1: Introduction to Digital System Design
1. Introduction
 Digital hardware has experienced drastic
expansion and improvement in the past 40 years.
 The number of transistors in a single chip has
grown exponentially.

1. Introduction
 A silicon chip now routinely contains
hundreds of thousands or even hundreds of
millions of transistors.

1. Introduction
 In the past, the major applications of digital
hardware were computational systems.
 However, as the chip became smaller,
faster, cheaper and more capable, many
electronic, control, communication and even
mechanical systems have been “digitized”
internally, using digital circuits to store,
process and transmit information.

1. Introduction
 As applications become larger and more
complex, the task of designing digital circuits
becomes more difficult.
 Developing and producing a digital circuit
is a complicated process, and the design and
synthesis are only two of the tasks.
 The best way to handle the complexity is to
view the circuit at a more abstract level and
utilize software tools to derive the low-level
implementation.
1. Introduction
e.g, digital circuit in a wireless communication
system transmitter
A Error
Data Data
info / correction Modulation
compression encryption
D coding
digital implementation
D Error
Data de- Data De-
info / correction
compression decryption modulation
A de-coding
digital implementation
receiver

1. Introduction
e.g, digital circuit in a control system
Sen
A D sor
actu
/ Controller / Plant
ator output
D A
set point digital

implementation

1. Introduction
Why Digital
• Advantage of digital devices
• Reproducibility of information
• Flexibility and functionality: easier to store, transmit and
manipulate information
• Economy: cheaper device and easier to design
• Moore’s law
• Transistor geometry
• Chips double its density (number of transistor) in every 18
months
• Devices become smaller, faster and cheaper
• Now a chip consists of hundreds of million gates
• And we can have a “wireless-PDA-MP3-player-
camera-GPS-cell-phone” gadget very soon

2. Device Technologies: Fabrication of an IC
 If we want to build a custom digital system,
there are varieties of device technologies to
choose.
 There is no single best technology.
 We have to consider the trade-offs among
various factors, including chip area, speed,
power and cost.

 To better understand the differences between
the device technologies, it is helpful to have a
basic idea of the fabrication process of an
integrated circuit (IC).
 An IC is made from layers of doped silicon,
poly silicon, metal and silicon dioxide, built
on top of one another, on a thin silicon wafer.
 Some of these layers form transistors, and
others form planes of connection wires.

 To better understand the differences between
the device technologies, it is helpful to have a
basic idea of the fabrication process of an
integrated circuit (IC).
 An IC is made from layers of doped silicon,
poly silicon, metal and silicon dioxide, built
on top of one another, on a thin silicon wafer.
 Some of these layers form transistors, and
others form planes of connection wires.

 Transistors and connection are made from many layers
(typical 10 to 15 in CMOS) built on top of one another.
 Each layer has a special pattern defined by a mask
• One important aspect of an IC is the length of a smallest
transistor that can be fabricated
• It is measured in micron (mm, 10-6 meter)

 Each layer has a special pattern defined by a mask
• E.g., we may say an IC is built with 0.50 mm process
• The process continues to improve, as witnessed by
Moore’s law
• The state-of-art process approaches less than
a fraction of 0.1 mm (known as deep sub-micron)


2. Device Technologies: Classification of device technologie
 Where customization is done.
• In a fab (fabrication facility): ASIC (Application
Specific IC)
• In the “field”: non-ASIC
 Classification
• Full-custom ASIC
• Standard cell ASIC
• Gate array ASIC
• Complex field programmable logic device
• Simple field programmable logic device
• Off-the-shelf SSI (Small Scaled IC)/MSI (Medium
Scaled IC) components.
2. Device Technologies: Full-custom ASIC
 All aspects (e.g., size of a transistor) of a
circuit are tailored for a particular application.
 Circuit fully optimized
 Design extremely complex and involved
 Only feasible for small components
 Masks needed for all layers
 http://www.csitsun.pub.ro/resources/asic/CH01.pdf
 We have complete control of the circuit and
can even craft the layout of a transistor to
meet special area or performance needs.
 The resulting circuit is fully optimized and
has the best possible performance.

 Unfortunately, designing a circuit at the
transistor level is extremely complex and
involved, and is only feasible for a small circuit

 It is not practical to use this approach to
design a complete system, which now may
contain tens and even hundreds of millions of
transistors.
 The major application of
full-custom ASIC
technology is to design the
basic logic components that
can be used as building
blocks of a larger system.
 Another application is to design special-
purpose “bit- slice” typed circuits, such as a 1-
bit memory or 1-bit adder.
 These circuits have a regular structured are
constructed through a cascade of identical slices.
The 8 input AND gate

2. Device Technologies: Standard-Cell ASIC
 Circuit made of a set of pre-defined logic,
known as standard cells.
 E.g., basic logic gates, 1-bit adder, D FF etc.
 Layout of a cell is pre-determined, but layout

of the complete circuit is customized.
 Masks needed for all layers.

 In standard-cell ASIC (also simply known as
standard-cell) technology.
 A circuit is
constructed by
using a set of
predefined logic
components,
known as
standard cells.

 These cells are predesigned and their layouts are
validated and tested.
 Standard-cell ASIC technology allows us to work
at the gate level rather than at the transistor level
and thus greatly simplifies the design process.

 The device manufacturer usually provides a
library of standard cells as the basic building
blocks.
 The library normally consists of basic logic gates,
simple combinational components, such as:
 an and-or-inverter.
 2-to-1 multiplexer.
 1-bit full adder.

 The basic memory elements, such as: a D-type
latch and, D-type flip-flop.
 Some libraries
may also contain
more sophisticated
function blocks,
such as an adder,
barrel shifter and
random access
memory (RAM). D Flip Flop Using TRANSMISSION GATES

 In standard-cell technology, a circuit is made of
cells.
 The types of cells and the interconnection depend
on the individual application.
 Whereas the layout of a cell is predetermined, the
layout of the complete circuit is unique for a
particular application and nothing can be constructed
in advance.
 Thus, fabrication of a standard-cell chip is
identical to that of a full-custom ASIC chip, and all
layers have to be custom constructed.
2. Device Technologies: Gate array ASIC
 Circuit is built from an array of a single type
of cell (known as base cell).
 Base cells are pre-arranged and placed in
fixed positions, aligned as one- or two-
dimensional array.
 More sophisticated components (macro cells)
can be constructed from base cells.
 Masks needed only for metal layers
(connection wires).
 In gate array ASIC (also simply known as
gate array) technology, a circuit is built from
an array of predefined cells.
 Unlike standard-cell technology, a gate array
chip consists of only one type of cell, known
as a base cell.
 The base cell is fairly simple, resembling a
logic gate.
 A gate array vendor also provides a library
of predesigned components, known as macro
cells, which are built from base cells.
 The macro cells have a predefined
interconnect and provide the designer with more
sophisticated logic blocks.

 Compared to standard-cell technology.
• The fabrication of a gate array device is
much simpler, due to its fixed array structure.
• Since the array is common to all applications,
the cell can be fabricated in advance.

2. Device Technologies: Complex Field Programmable Device
 Device consists of an array of generic logic
cells and general interconnect structure.
 Logic cells and interconnect can be
“programmed” by utilizing “semiconductor”
fuses or “switches”
 Customization is done “in the filed”
 Two categories:
• CPLD (Complex Programmable Logic Device)
• FPGA (Field Programmable Gate Array)
 No custom mask needed
 The basic structures of gate array ASIC and
complex field programmable devices are somewhat
similar.
 However, the
interconnect structure of
field-programmable
devices is predetermined
and thus imposes more
constraints on signal
routing.

 The programmability
is obtained by utilizing
semiconductor
“fuses” or “switches”,
which can be set as
open- or short-circuit.

 The programmability is obtained by utilizing
semiconductor “fuses” or “switches”, which
can be set as open- or short-circuit.

 The programmability is obtained by utilizing
semiconductor “fuses” or “switches”, which
can be set as open- or short-circuit.


 According to the complexity and structure
of logic cells, complex field-programmable
devices can be divided roughly into two
broad categories:
 Complex
programmable logic
device (CPLD).
 Field programmable
gate array (FPGA).
 CPLD structure
Logic Array Logic Array
I/O block (LAB) block (LAB) I/O
SPLD SPLD

PIA
SPLD SPLD
Programmable
Interconnect
Logic Array array Logic Array
SPLD SPLD

SPLD SPLD

 FPGA structure Programmable
interconnections
IO IO IO IO
block block block block
IO IO
block block
CLB CLB CLB CLB
IO IO
block block
CLB CLB CLB CLB
IO IO
block block
CLB CLB CLB CLB
IO IO
block block
IO IO IO IO
block block block block
FPGA
 Configurable logic block

 FPGA structure

2. Device Technologies: Simple Field Programmable Device
 Programmable device with simple internal
structure
 E.g.,
• PROM (Programmable Read Only Memory)
• PAL (Programmable Array Logic)
 No custom mask needed
 Replaced by CPLD/FPGA

 Simple field-programmable logic devices are
programmable devices with simpler internal
structure.
 These devices are
generically called
programmable logic
devices (PLDs).

 We add the word simple to distinguish them from
FPGA and CPLD devices.
 Simple field-programmable
devices are normally constructed
as a two-level array, with an
AND plane and an OR plane.
 The interconnect of one or both
planes can be programmed to
perform a logic function expressed
in sum-of-product format.
The devices include:
 PROM, in which the OR plane can be programmed;
 Programmable array logic (PAL), AND plane can be
programmed;
 Programmable logic array (PLA), both planes can be
programmed.


 PROM

 PAL

 GAL

Cấu trúc của PAL (Programmable Array Logic)
Cấu trúc của GAL (Generic Array Logic)

 Unlike FPGA and CPLD devices, simple field-
programmable logic devices do not have a general
interconnect structure, and thus their functionality
is severely limited.
 ROM, PAL and PLA are now used as internal
components of an ASIC or CPLD device rather
than as an individual chip.

2. Device Technologies: SSI/MSI components
 Small parts with fixed, limited functionality.
 E.g., 7400 TTL series (more than 100 parts).
 Resource (e.g., power, board area,

manufacturing cost etc.) is consumed by
“package” but not “silicon”.
 No longer a viable option.

 Before the emergence of field-programmable
devices, the only alternative to ASIC was to
utilize the prefabricated off-the-shelf SSI/MSI
components.
 These components are small parts with fixed,
limited functionality.

 As the programmable devices become more
capable and less expensive, designing a large
custom circuit using SSI/MSI components is no
longer a feasible option and should not be
considered.

2. Device Technologies: Summary
 We have reviewed six device technologies used
to implement custom digital systems.
 Among them, off-the-shelf SSI/MSI
components and simple programmable devices
are gradually being phased out and full-custom
ASIC is feasible only for a small, specialized
circuit.
 Thus, for a large digital system, there are only
three viable device technologies: standard-cell
ASIC, gate array ASIC and CPLD/FPGA.
3. Comparison of technologies
 Once deciding to develop custom hardware for an
application, we need to choose from the three
device technologies.
 The major criteria for selection are area, speed,
power and cost.
 Cost concerns the expenditure associated with the
design and production of the circuit as well as the
potential lost profits.
 Each technology has its strengths and
weaknesses, and the “best” technology depends on
the needs of a particular application.
3. Comparison of technologies: area
 Chip area (or size) corresponds to the required
silicon real estate to implement a particular
application.
 A smaller chip needs fewer resources, simplifies
the testing and provides better yield.
 The chip size depends on the architecture of the
circuit and the device technology.
 The same function can frequently be realized by
different architectures, with different areas and
speeds.

 In gate array technology, the circuit has to be
constructed by predefined, prearranged base
cells.
 Since functionality and the placement of the base
cells are not tailored to a specific application,
silicon use is not optimal.
 The area of the resulting circuit is normally larger
than that of a standard-cell chip.
 In FPGA technology, a significant portion of the
silicon is dedicated to achieving programmability.
 Furthermore, the functionalities of logic cells and
the interconnect are fixed in advance and it is
unlikely that an application can be an exact match
for the predetermined structure.
 A certain percentage of the capacity will be left
unutilized.
 The area of the resulting FPGA chip is much
larger than that of an ASIC chip.
 A certain percentage of the capacity will be left
unutilized.
 In general, a gate array chip may need 20% to
100% larger silicon area than that of a standard-
cell chip, but an FPGA chip frequently requires two
to five times the area of an ASIC chip.
 Standard cell is the smallest since the cells and
interconnect are customized.
 FPGA is the largest
• Overhead for “programmability”
• Capacity cannot be completely utilized

3. Comparison of technologies: Speed (Performance)
 Since a standard-cell chip has tailored
interconnect and utilizes a minimal amount of silicon
area, it has the smallest propagation delay and best
speed.
 On the other hand, an FPGA chip has the worst
propagation delay. In addition to its large size, the
programmable interconnect has a relatively large
resistance and capacitance, which introduces even
more delay.
 As with chip area, the speed difference between
standard-cell and gate array technologies is much
less significant than that between FPGA and ASIC.
3. Comparison of technologies: POWER
 If the identical architecture is used, a smaller
chip, which consists of fewer transistors, usually
consumes less power.
 Thus, a standard-cell chip consumes the least
amount of power and an FPGA chip uses the most
power.
 Standard-cell technology is clearly the best choice
from a technical perspective.
 A chip constructed using standard-cell ASIC is
small and fast, and consumes less power.
 Designing and fabricating a standard-cell chip is
more involved and time consuming than for the
other two technologies.

Non recurring engineering (NRE)

4. System representation
 A large digital system is quite complex.
 The same system is frequently described in
different ways and is examined from different
perspectives.
 There are three views:
• Behavioral view
• Structural view
• Physical view

4. System representation: Behavioral view
A behavioral view describes the
functionality (i.e., “behavior”) of a system.
 It treats the system as a black box and
ignores its internal implementation.
 The view focuses on the relationship
between the input and output signals,
defining the output response when a
particular set of input values is applied.

4. System representation: Structural view
 A structural view describes the internal
implementation (i.e., structure) of a system.
 The description is done by explicitly
specifying what components are used and how
these components are connected.
 It is more or less the schematic or the
diagram of a system.

4. System representation: Physical view
 A physical view describes the physical
characteristics of the system and adds
additional information to the structural view.
 It specifies the physical sizes of components,
the physical locations of the components on a
board or a silicon wafer, and the physical path
of each connection line.
 An example of a physical view is the printed
circuit board layout of a system.
4. System representation: Physical view
 Clearly, the physical view of a system
provides the most detailed information.
 It is the final specification for the system
fabrication.
 On the other hand, the behavioral view
imposes fewest constraints and is the most
abstract form of description.

4. System representation:
e.g., structural and physical view

4. System representation:
 Behavioral view:
• Describe functionalities and i/o behavior
• Treat the system as a black box
 Structural view:
• Describe the internal implementation (components and
interconnections)
• Essentially block diagram
 Physical view:
• Add more info to structural view: component size,
component locations, routing wires
• E.g., layout of a print circuit board
5. Levels of Abstraction
 How to manage complexity for a chip with 10
million transistors?
 As chip density reaches hundreds of millions of
transistors, it is impossible for a human being, or
even a computer, to process this amount of data
directly.
 A key method of managing complexity is to
describe a system in several levels of abstraction.
 An abstraction is a simplified model of the system,
showing only the selected features and ignoring the
associated details.
 The purpose of an abstraction is to reduce the
amount of data to a manageable level so that only
the critical information is presented.
 A high-level abstraction is focused and contains
only the most vital data.
 On the other hand, a low-level abstraction is more
detailed and takes account of previously ignored
information.
 Although it is more complex, the low-level
abstraction model is more accurate and is closer to
the real circuit.
 In the development process, we normally start with
a high-level abstraction and concentrate on the
most vital characteristics.
 As the system is better understood, we then
include more details and develop a lower-level
abstraction.
 Four levels of abstraction are considered in digital
system development: Transistor level, Gate level,
Register transfer (RT) level, Processor level.

 Four levels of
abstraction are Processor level
considered in digital
system development: Register transfer
(RT) level
Gate level
Transistor level

 The level of abstraction and the view are two
independent dimensions of a system, and each level
has its own views.
 The levels of abstraction and views can be
combined in a Y-chart, which is shown in next slide.

 In this chart,
each axis
represents a
view and the
levels of
abstraction
increase from
the center to
the outside.

5. Levels of Abstraction: TRANSISTOR-LEVEL ABSTRACTION
 The lowest level of abstraction is the transistor
level.
• At this level, the basic building blocks are
transistors, resistors, capacitors and so on.
• The behavior description is usually done by a
set of differential equations or even by some
type of current-voltage diagram.
• Analog system simulation software, such as
SPICE, can be used to obtain the desired
input-output characteristics.
5. Levels of Abstraction: GATE-LEVEL ABSTRACTION
 Gate level:
• Typical building blocks include simple logic gates,
such as AND, OR, XOR and 1-bit 2-to-1 multiplexer,
and basic memory elements, such as latch and flip-flop.
• Instead of using continuous values, we consider only
whether a signal’s voltage is above or below a
threshold, which is interpreted as logic 1 or logic 0
respectively.
• Since there are only two values, the input-output
behavior is described by Boolean equations.
5. Levels of Abstraction: RT-LEVEL ABSTRACTION
 At the register-transfer (RT) level, the basic
building blocks are modules constructed from
simple gates.
• They include functional units, such as adders and
comparators, storage components, such as registers,
and data routing components, such as multiplexers.
• A reasonable name for this level would be module-
level abstraction.
• However, the term register-transfer is normally
used in digital design and we follow the general
convention.
5. Levels of Abstraction: PROCESSOR-LEVEL ABSTRACTION
 Processor-level abstraction is the highest level of
abstraction.
• The basic building blocks at this level,
frequently known as intellectual properties
(IPs), include processors, memory modules,
bus interfaces and so on.
• The behavioral description of a system is
more like a program coded in a conventional
programming language, including computation
steps and communication processes.
 Level of abstractions
• Transistor level
• Gate level
• Register transfer (RT) level
• Processor level
 Characteristics of each level
• Basic building blocks
• Signal representation
• Time representation
• Behavioral representation
• Physical representation.
Summary

6. Development tasks and eda software
 Developing a custom digital circuit is essentially a
refining and validating process.
 A system is gradually transformed from an
abstract high-level description to final mask layouts.
 Along with each refinement, the system's function
should be validated to ensure that the final product
works correctly and meets the specification and
performance goals.
EDA: electronic design automation

6. Development tasks and eda software
 The major design tasks of developing a digital
system are:
• Synthesis
• Physical design
• Verification
• Testing

6. Development tasks and eda software: SYNTHESIS
 Synthesis is a refinement process that realizes a
description with components from the lower
abstraction level.
 The original description can be in either a
behavioral view or a structural view, and the
resulting description is a structural view (i.e.,
netlist) in the lower abstraction level.

6. Development tasks and eda software: PHYSICAL DESIGN
 Developing a custom digital circuit is essentially a
refining and validating process.
 The first part is the refinement process between
the structural and physical views, which derives a
layout for a netlist.
 The second part involves the analysis and tuning
of a circuit’s electrical characteristics.
 The main tasks in physical design include floor
planning, placement and routing and circuit
extraction.
6. Development tasks and eda software: PHYSICAL DESIGN
 Verification is the process of checking whether a
design meets the specification and performance
goals.
 It concerns the correctness of the initial design as
well as the correctness of refinement processes
during synthesis and physical design.
 Verification is done in different phases of the
design and at different levels of abstraction.
 Verification has two aspects: functionality and
performance.
6. Development tasks and eda software: TESTING
 The meanings of verification and testing are
somewhat similar in a dictionary sense.
 However, they are two very different tasks in
digital system development.
 Verification is the process of determining
whether a design meets the specification and
performance goals. It concerns the correctness of the
initial design as well as the refinement processes.
 On the other hand, testing is the process of
detecting the physical defects of a die or a package
that occurred during manufacturing.

1. Develop the design file and testbench.
2. Use the design file as the circuit description, and
perform a simulation to verify that the design
functions as desired.
3. Perform a synthesis.
4. Use the output netlist file of the synthesizer as the
circuit description, and perform a simulation and
timing analysis to verify the correctness of the
synthesis and to check preliminary timing.
5. Perform placement and routing.
6. Annotate the accurate timing information to the
netlist, and perform a simulation and timing
analysis to verify the correctness of the placement
and routing and to check whether the circuit meets
the timing constraints.
7. Generate the configuration file and program the
device.
8. Verify operation of the physical part.

Additional tasks
 Large design targeting FPGA
• Design partition
• More verification
 Large design targeting ASIC
• Thorough verification
• Testing
• Physical design

The end!

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HCMC University of Technology and Education

Faculty of Electrical & Electronic Engineering

NGUYEN THANH NGHIA

2. Textbook: RTL HARDWARE DESIGN

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set point digital

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The 8 input AND gate

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 E.g., basic logic gates, 1-bit adder, D FF etc.

 Layout of a cell is pre-determined, but layout

 Masks needed for all layers.

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Logic Array Logic Array

Logic Array Logic Array

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CLB CLB CLB CLB

CLB CLB CLB CLB

CLB CLB CLB CLB

 Configurable logic block

NGUYEN THANH NGHIA 45

NGUYEN THANH NGHIA 46

NGUYEN THANH NGHIA 47

NGUYEN THANH NGHIA 49

NGUYEN THANH NGHIA 50

NGUYEN THANH NGHIA 51

NGUYEN THANH NGHIA 52

NGUYEN THANH NGHIA 53

Cấu trúc của GAL (Generic Array Logic)

NGUYEN THANH NGHIA 54

NGUYEN THANH NGHIA 55

 Resource (e.g., power, board area,

 No longer a viable option.