Sic 639
Sic 639
Sic 639
www.vishay.com
Vishay Siliconix
50 A VRPower® Integrated Power Stage
DESCRIPTION FEATURES
The SiC639 are integrated power stage solutions optimized • Thermally enhanced PowerPAK® MLP55-31L
for synchronous buck applications to offer high current, high package
efficiency, and high power density performance. Packaged • Vishay’s Gen IV MOSFET technology and a low
in Vishay’s proprietary 5 mm x 5 mm MLP package, SiC639 side MOSFET with integrated Schottky diode
enables voltage regulator designs to deliver up to 50 A • Delivers up to 50 A continuous current
continuous current per phase.
• High efficiency performance
The internal power MOSFETs utilizes Vishay’s
• High frequency operation up to 1.5 MHz
state-of-the-art Gen IV TrenchFET technology that delivers
industry benchmark performance to significantly reduce • Power MOSFETs optimized for 19 V input stage
switching and conduction losses. • 3.3 V / 5 V PWM logic with tri-state and hold-off
The SiC639 incorporate an advanced MOSFET gate driver • Zero current detect control for light load efficiency
IC that features high current driving capability, adaptive improvement
dead-time control, an integrated bootstrap Schottky diode, • Low PWM propagation delay (< 20 ns)
a thermal warning (THWn) that alerts the system of
• Faster disable
excessive junction temperature, and zero current detection
to improve light load efficiency. The drivers are also • Thermal monitor flag
compatible with a wide range of PWM controllers and • Under voltage lockout for VCIN
supports tri-state PWM, 3.3 V / 5 V PWM logic. • Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Multi-phase VRDs for computing, graphics card and
memory
• Intel IMVP-8/9 VRPower delivery
-VCORE, VGRAPHICS, VSYSTEM AGENT Skylake, Kabylake
platforms
-VCCGI for Apollo Lake platforms
• Up to 24 V rail input DC/DC VR modules
5V Input
VDRV
NC
V IN
BOOT
VCIN PHASE
ZCD_EN# Output
SW
DSBL# Gate
PWM
controller PWM driver
THWn
C GND
GL
PGND
DSBL#
DSBL#
THWn
THWn
PGND
VDRV
PGND
VDRV
SW
SW
SW
SW
SW
SW
GL
GL
33
31 30 29 28 27 26 25 24 GL 24 25 26 27 28 29 30 31
9 10 11 12 13 14 15 15 14 13 12 11 10 9
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
VIN
VIN
VIN
VIN
VIN
VIN
Top view Bottom view
PIN CONFIGURATION
PIN NUMBER NAME FUNCTION
1 PWM PWM input logic
The ZCD_EN# pin enables or disables zero cross detection on inductor current when it detects
PWM = mid.
2 ZCD_EN#
When ZCD_EN# is LOW, GL stays on until ZCD detected when it detects PWM = mid.
When ZCD_EN# is HIGH, GL turns off when it detects PWM = mid.or PWM = 1
3 VCIN Supply voltage for internal logic circuitry
4, 32 CGND Signal ground
5 BOOT High side driver bootstrap voltage
6 N.C. Not connected internally, can be left floating or connected to ground
7 PHASE Return path of high side gate driver
8 to 11, 34 VIN Power stage input voltage. Drain of high side MOSFET
12 to 15, 28, 35 PGND Power ground
16 to 26 VSWH Phase node of the power stage
27, 33 GL Low side MOSFET gate signal
29 VDRV Supply voltage for internal gate driver
30 THWn Thermal warning open drain output
31 DSBL# Disable pin. Active low
ORDERING INFORMATION
PART NUMBER PACKAGE MARKING CODE OPTION
SiC639CD-T1-GE3 PowerPAK MLP55-31L SiC639 5 V PWM optimized
SiC639ACD-T1-GE3 PowerPAK MLP55-31L SiC639A 3.3 V PWM optimized
SiC639DB Reference board
= Pin 1 Indicator
= ESD Symbol
LL
F = Assembly Factory Code
Y = Year Code
FYWW
WW = Week Code
LL = Lot Code
ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C)
LIMITS
PARAMETER SYMBOL TEST CONDITION UNIT
MIN. TYP. MAX.
POWER SUPPLY
VDSBL# = 0 V, no switching, VPWM = FLOAT - 5 -
Control logic supply current IVCIN VDSBL# = 5 V, no switching, VPWM = FLOAT - 300 - μA
VDSBL# = 5 V, fS = 300 kHz, D = 0.1 - 350 -
fS = 300 kHz, D = 0.1 - 9 14
mA
fS = 1 MHz, D = 0.1 - 30 -
Drive supply current IVDRV
VDSBL# = 0 V, no switching - 15 -
μA
VDSBL# = 5 V, no switching - 55 -
BOOTSTRAP SUPPLY
Bootstrap diode forward voltage VF IF = 2 mA 0.4 V
PWM CONTROL INPUT (SiC639)
Rising threshold VTH_PWM_R - - 4.2
Falling threshold VTH_PWM_F 0.72 - -
V
Tri-state voltage VTRI_FLOAT VPWM = FLOAT - 2.3 -
Tri-state window VTRI_WINDOW 1.38 - 3
Tri-state rising threshold hysteresis VHYS_TRI_R - 225 -
mV
Tri-state falling threshold hysteresis VHYS_TRI_F - 325 -
VPWM = 5 V, DSBL# = high - - 350
VPWM = 5 V, DSBL# = low - - 1
PWM input current IPWM μA
VPWM = 0 V, DSBL# = high - - -350
VPWM = 0 V, DSBL# = low - - -1
PWM CONTROL INPUT (SiC639A)
Rising threshold VTH_PWM_R - - 2.7
Falling threshold VTH_PWM_F 0.72 - -
V
Tri-state Voltage VTRI_FLOT VPWM = FLOAT - 1.8 -
Tri-state window VTRI_WINDOW 1.38 - 1.95
Tri-state rising threshold hysteresis VHYS_TRI_R - 250 -
mV
Tri-state falling threshold hysteresis VHYS_TRI_F - 300 -
VPWM = 3.3 V, DSBL# = high - - 225
VPWM = 3.3 V, DSBL# = low - - 1
PWM input current IPWM μA
VPWM = 0 V, DSBL# = high - - -225
VPWM = 0 V, DSBL# = low - - -1
TIMING SPECIFICATIONS
Tri-state to GH/GL rising
tPD_TRI_R - 30 -
propagation delay
Tri-state GH hold-off time tTSHO_GH - 35 -
Tri-state GL hold-off time tTSHO_GL - 130 -
GH - turn off propagation delay tPD_OFF_GH - 15 -
No load, see fig. 4
GH - turn on propagation delay
tPD_ON_GH - 10 -
(dead time rising) ns
GL - turn off propagation delay tPD_OFF_GL - 13 -
GL - turn on propagation delay
tPD_ON_GL - 10 -
(dead time falling)
DSBL# Lo to GH/GL falling
tPD_DSBL#_F Fig. 5 - 15 -
propagation delay
PWM minimum on-time tPWM_ON_MIN 30 - -
ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C)
LIMITS
PARAMETER SYMBOL TEST CONDITION UNIT
MIN. TYP. MAX.
DSBL# ZCD_EN# INPUT
VIH_DSBL# Input logic high 2 - -
DSBL# logic input voltage
VIL_DSBL# Input logic low - - 0.8
V
VIH_ZCD_EN# Input logic high 2 - -
ZCD_EN# logic input voltage
VIL_ZCD_EN# Input logic low - - 0.8
PROTECTION
VCIN rising, on threshold - 3.7 4.1
Under voltage lockout VUVLO V
VCIN falling, off threshold 2.7 3.1 -
Under voltage lockout hysteresis VUVLO_HYST - 575 - mV
THWn flag set (2) TTHWn_SET - 160 -
THWn flag clear (2) TTHWn_CLEAR - 135 - °C
THWn flag hysteresis (2) TTHWn_HYST - 25 -
THWn output low VOL_THWn ITHWn = 2 mA - 0.02 - V
Notes
(1) Typical limits are established by characterization and are not production tested
(2) Guaranteed by design
VDRV
Thermal monitor
& warning
VCIN UVLO
DISB#
VCIN
- 20K
+ PHASE
DISB PWM logic Anti-cross Vref = 1 V
control & conduction GL
state control SW
machine logic -
+
PWM Vref = 1 V
VDRV
DISB
CGND
SW
PGND
ZCD_EN# GL PGND
PWM PWM
GH GH
GL GL
t t
94 55
90 50
86 45
500 kHz
500 kHz
1 MHz
1 MHz
78 35
74 30
70 25
Complete converter efficiency
66 PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)] 20
POUT = VOUT x IOUT, measured at output capacitor
62 15
0 5 10 15 20 25 30 35 40 45 50 0 15 30 45 60 75 90 105 120 135 150
Output Current, IOUT (A) PCB Temperature, TPCB (°C)
Fig. 6 - Efficiency vs. Output Current (VIN = 12.6 V) Fig. 9 - Safe Operating Area
5.0 16.0
IOUT = 25A
4.5 14.0
Power Loss, PL (W)
4.0 12.0
Power Loss, PL (W)
3.5 10.0
1 MHz
3.0 8.0
2.0 4.0
1.0 0.0
200 300 400 500 600 700 800 900 1000 1100 0 5 10 15 20 25 30 35 40 45
Switching Frequency, fs (KHz) Output Current, IOUT (A)
Fig. 7 - Power Loss vs. Switching Frequency (VIN = 12.6 V) Fig. 10 - Power Loss vs. Output Current (VIN = 12.6 V)
98 94
500 kHz
500 kHz
94 90
90
86
Efficiency (%)
86
82
Efficiency (%)
Fig. 8 - Efficiency vs. Output Current (VIN = 9 V) Fig. 11 - Efficiency vs. Output Current (VIN = 19 V)
4.2 0.40
4.0 0.35
IF = 2 mA
3.6 0.25
3.4 0.20
3.2 0.15
2.8 0.05
2.6 0.00
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)
Fig. 12 - UVLO Threshold vs. Temperature Fig. 15 - Boot Diode Forward Voltage vs. Temperature
3.20 3.20
2.85 2.85
Control Logic Supply Voltage, VPWM (V)
VTH_PWM_R
VTH_PWM_R
2.50 2.50
VTRI_TH_F
VTRI_TH_F
2.15 2.15
1.80 1.80
VTRI VTRI
1.45 VTRI_TH_R 1.45
VTRI_TH_R
1.10 1.10
0.40 0.40
-60 -40 -20 0 20 40 60 80 100 120 140 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
Temperature (°C) Driver Supply Voltage, VCIN (V)
Fig. 13 - PWM Threshold vs. Temperature (SiC639A) Fig. 16 - PWM Threshold vs. Driver Supply Voltage (SiC639A)
5.0 5.00
VTH_PWM_R
4.0 4.00
Control Logic Supply Voltage, VPWM (V)
3.5 3.50
VTRI_TH_F
3.0 VTRI_TH_F 3.00
VTRI VTRI
2.5 2.50
2.0 2.00
0.0 0
-60 -40 -20 0 20 40 60 80 100 120 140 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
Temperature (°C) Driver Supply Voltage, VCIN (V)
Fig. 14 - PWM Threshold vs. Temperature (SiC639) Fig. 17 - PWM Threshold vs. Driver Supply Voltage (SiC639)
1.7 2.20
1.3 1.40
1.2 1.20
0.9 0.60
-60 -40 -20 0 20 40 60 80 100 120 140 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
Temperature (°C) Driver Supply Voltage, VCIN (V)
Fig. 18 - DSBL# Threshold vs. Temperature Fig. 21 - ZCD_EN# Threshold vs. Driver Supply Voltage
1.7 8
VDSBL# = 0 V
1.6 VIH_DSBL# 7
Driver Supply Current, IVDVR & IVCIN (V)
DSBL# Threshold Voltage, VDSBL# (V)
1.5 6
1.4 5
1.3 4
1.2 3
1.1 2
VIL_DSBL#
1.0 1
0.9 0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 -60 -40 -20 0 20 40 60 80 100 120 140
Driver Supply Voltage, VCIN (V) Temperature (°C)
Fig. 19 - DSBL# vs. Driver Input Voltage Fig. 22 - Driver Shutdown Current vs. Temperature
10.8 340
Driver Supply Current, IVDVR & IVCIN (V)
10.7 330
DSBL# Pull-Down Current, IDSBL# (uA)
VPWM = FLOAT
10.6 320
10.5 310
10.4 300
10.3 290
10.2 280
10.1 270
10.0 260
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)
Fig. 20 - DSBL# Pull-Down Current vs. Temperature Fig. 23 - Driver Supply Current vs. Temperature
VSWH
CVDRV
P
G
N
D
PGND
VIN CVCIN
CGND
VIN plane
PGND plane
1. Layout VIN and PGND planes as shown above 1. The VCIN/VDRV input filter ceramic cap should be placed
2. Ceramic capacitors should be placed right between VIN very close to IC. It is recommended to connect two caps
and PGND, and very close to the device for best separately.
decoupling effect 2. CVCIN cap should be placed between pin 3 and pin 4
3. Difference values / packages of ceramic capacitors (CGND of driver IC) to achieve best noise filtering.
should be used to cover entire decoupling spectrum e.g. 3. CVDRV cap should be placed between pin 28 (PGND of
1210, 0805, 0603 and 0402 driver IC) and pin 29 to provide maximum instantaneous
4. Smaller capacitance value, closer to device VIN pin(s) driver current for low side MOSFET during switching
- better high frequency noise absorbing cycle
Step 2: VSWH Plane 4. For connecting CVCIN analog ground, it is recommended
to use large plane to reduce parasitic inductance.
Step 4: BOOT Resistor and Capacitor Placement
VVSWH
SWH
Snubber
Cboot
Rboot
PPGND
GND plane
Plane
VSWH
Step 6: Adding Thermal Relief Vias 1. It is recommended to make single connection between
CGND and PGND and this connection can be done on top
layer.
2. It is recommended to make the whole inner 1 layer (next
to top layer) ground plane and separate them into CGND
and PGND plane.
VSWH 3. These ground planes provide shielding between noise
source on top layer and signal trace on bottom layer.
CGND
PGND
VIN
PGND
plane
VIN plane
VIN
PGND
VOUT
VIN
PGND
VOUT
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?76585.
F2
2x D2-4
F1
A2
K8
0.10 C B 24 31
E2-4
K11
23 1
K5 E2- 1
0.10 m C A B
K6
K3
K10
(Nd-1) xe
MLP55-31L
ref.
(5 mm x 5 mm)
E
E2- 3
E2- 2
e
4
16 8
b
B
L
15 K2 9
C D2- 3 D2- 2
K9
(Nd-1) x e
ref.
Top view Side view Bottom view
MILLIMETERS INCHES
DIM.
MIN. NOM. MAX. MIN. NOM. MAX.
A (8) 0.70 0.75 0.80 0.027 0.029 0.031
A1 0.00 - 0.05 0.000 - 0.002
A2 0.20 ref. 0.008 ref.
b (4) 0.20 0.25 0.30 0.008 0.010 0.012
D 4.90 5.00 5.10 0.193 0.196 0.200
e 0.50 BSC 0.019 BSC
E 4.90 5.00 5.10 0.193 0.196 0.200
L 0.35 0.40 0.45 0.013 0.015 0.017
N (3) 32 32
Nd (3) 8 8
Ne (3) 8 8
D2-1 0.98 1.03 1.08 0.039 0.041 0.043
D2-2 0.98 1.03 1.08 0.039 0.041 0.043
D2-3 1.87 1.92 1.97 0.074 0.076 0.078
D2-4 0.30 BSC 0.012 BSC
D2-5 1.00 1.05 1.10 0.039 0.041 0.043
E2-1 1.27 1.32 1.37 0.050 0.052 0.054
E2-2 1.93 1.98 2.03 0.076 0.078 0.080
E2-3 3.75 3.80 3.82 0.148 0.150 0.152
E2-4 0.45 BSC 0.018 BSC
F1 0.20 BSC 0.008 BSC
F2 0.20 BSC 0.008 BSC
K1 0.67 BSC 0.026 BSC
K2 0.22 BSC 0.008 BSC
K3 1.25 BSC 0.049 BSC
K4 0.05 BSC 0.002 BSC
K5 0.38 BSC 0.015 BSC
K6 0.12 BSC 0.005 BSC
Notes
1. Use millimeters as the primary measurement
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
3. N is the number of terminals,
Nd is the number of terminals in X-direction, and
Ne is the number of terminals in Y-direction
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
6. Exact shape and size of this feature is optional
7. Package warpage max. 0.08 mm
8. Applied only for terminals
0.75
1.35 0.57
0.3
0.33
3.4
(D2-1) (D2-5) 31 0.5 1 24
31 1.03 1.05 24
0.75
1 (D3) 0.3
23 1.13
1 23
1.6
0.45
(E3)
0.85
0.3
0.5 (e)
0.35
(E2-2)
1.15
1.42
1.32
0.15
0.33
(K2) 0.22 2.02
1.75 0.3
(E2-1)
0.4
4.2
(K1) 0.67
3.5
5
3.05
0.07
0.25
2.15
(E2-3)
(b)
2.08
1.98
0.5
8 16 8 0.35 0.18 16
0.58
0.65
(L) 9 15 (L) 0.3
0.4 (D2-2) (D2-3) 0.4 9 15
0.35
0.3
1.03 1.92 0.35 0.5 0.75
0.5 0.65
31 24
1 23
33
Component for MLP55-31L
32
8 16
9 15
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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particular product with the properties described in the product specification is suitable for use in a particular application.
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