Green Mode Power Switch

for Valley Switching

Converter - Low EMI and
High Efficiency

FSQ0365, FSQ0265,
www.onsemi.com
FSQ0165, FSQ321
Description
A Valley Switching Converter generally shows lower EMI and
higher power conversion efficiency than a conventional
hard−switched converter with a fixed switching frequency. The
FSQ−series is an integrated Pulse−Width Modulation (PWM)
controller and SENSEFET® specifically designed for valley switching PDIP−8 PDIP8 GW
CASE 626−05 CASE 709AJ
operation with minimal external components. The PWM controller
includes an integrated fixed−frequency oscillator, under−voltage
lockout, Leading−Edge Blanking (LEB), optimized gate driver, MARKING DIAGRAM
internal soft−start, temperature−compensated precise current sources
for loop compensation, and self−protection circuitry.
$Y&E&Z&2&K
Compared with discrete MOSFET and PWM controller solutions, FSQxxxx
the FSQ−series reduces total cost, component count, size and weight;
while simultaneously increasing efficiency, productivity, and system
reliability. This device provides a basic platform for cost−effective
designs of valley switching fly−back converters. $Y = ON Semiconductor Logo
&E = Designated Space
Features &Z = Assembly Plant Code
• Optimized for Valley Switching Converter (VSC) &2 = 2−Digit Date code format
&K = 2−Digits Lot Run Traceability Code
• Low EMI through Variable Frequency Control and Inherent FSQxxxx = Specific Device Code Data
Frequency Modulation
• High Efficiency through Minimum Voltage Switching
• Narrow Frequency Variation Range Over Wide Load and Input ORDERING INFORMATION
Voltage Variation See detailed ordering and shipping information on page 2 of
this data sheet.
• Advanced Burst−Mode Operation for Low Standby Power
Consumption
• Pulse−by−Pulse Current Limit Applications
• Protection Functions: Overload Protection (OLP), Over−Voltage • Power Supplies for DVD Player,
Protection (OVP), Abnormal Over−Current Protection (AOCP), DVD Recorder, Set−Top Box
Internal Thermal Shutdown (TSD) • Adapter
• Under−Voltage Lockout (UVLO) with Hysteresis • Auxiliary Power Supply for PC, LCD TV,
• Internal Startup Circuit and PDP TV
• Internal High−Voltage SENSEFET: 650 V
• Built−in Soft−Start: 15 ms

Related Application Notes

• http://www.onsemi.com/pub/Collateral/AN−4137.pdf.pdf
• http://www.onsemi.com/pub/Collateral/AN−4141.pdf.pdf
• http://www.onsemi.com/pub/Collateral/AN−4150.pdf.pdf
• https://www.onsemi.com/pub/Collateral/AN−4134.PDF

© Semiconductor Components Industries, LLC, 2017 1 Publication Order Number:

December, 2020 − Rev. 3 FSQ0365/D
 FSQ0365, FSQ0265, FSQ0165, FSQ321

Table 1. ORDERING INFORMATION

Maximum Output Table(1)
230 VAC +15%(2) 85 − 265 VAC
Operating Current RDS(ON) Open Open
Part Number Package Shipping† Temperature Limit (Max.) Adapter(3) Frame(4) Adapter(3) Frame(4)
FSQ321 PDIP−8 3000 / Tube −40 to +85°C 0.6 A 19 W 8W 12W 7W 10W
FSQ321LX PDIP8 GW 1000 / Tape & Reel
FSQ0165RN PDIP−8 3000 / Tube −40 to +85°C 0.9 A 10 W 10W 15W 9W 13W
FSQ0165RLX PDIP8 GW 1000 / Tape & Reel
FSQ0265RN PDIP−8 3000 / Tube −40 to +85°C 1.2 A 6W 14W 20W 11W 16W
FSQ0265RLX PDIP8 GW 1000 / Tape & Reel
FSQ0365RN PDIP−8 3000 / Tube −40 to +85°C 1.5 A 4.5 W 17.5W 25W 13W 19W
FSQ0365RLX PDIP8 GW 1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1. The junction temperature can limit the maximum output power.
2. 230 VAC or 100/115 VAC with voltage doubler. The maximum power with CCM operation.
3. Typical continuous power in a non−ventilated, enclosed adapter measured at 50°C ambient temperature.
4. Maximum practical continuous power in an open−frame design at 50°C ambient temperature.

www.onsemi.com
2
 FSQ0365, FSQ0265, FSQ0165, FSQ321

Application Circuit
Vo

AC
IN

V str
Drain

PWM
Sync GND

V fb V cc

Figure 1. Typical Flyback Application

Internal Block Diagram

Sync Vstr Vcc Drain
4 5 2 6 7 8
+
OSC
0.7V/0.2V
−
+
+
V ref
0.35/0. 55 VCC Good −
VCC V ref VBurst −
8V/12V

Idelay IFB
Vfb 3R PWM
S Q
3
Gate
Soft− LEB Driver
R R Q
Start 200ns

AOCP
1
6V TSD S Q VOCP
VSD
GND
(1.1V)
2.5ms Time R Q
Sync Delay
6V
V ovp
VCC Good

FSQ0365RN Rev.00

Figure 2. Internal Block Diagram

www.onsemi.com
3
 FSQ0365, FSQ0265, FSQ0165, FSQ321

Pin Assignments

GND Drain

VCC 8−DIP Drain

VFB
8−LSOP Drain

Sync VSTR

Figure 3. Pin Configuration (Top View)

Table 2. PIN DEFINITIONS

Pin# Name Description
1 GND SENSEFET source terminal on primary side and internal control ground.

2 VCC Positive supply voltage input. Although connected to an auxiliary transformer winding, current is supplied
from pin 5 (Vstr) via an internal switch during startup (see Figure 2).
It is not until VCC reaches the UVLO upper threshold (12 V) that the internal startup switch opens and de-
vice power is supplied via the auxiliary transformer winding.

3 Vfb The feedback voltage pin is the non−inverting input to the PWM comparator. It has a 0.9 mA current source
connected internally while a capacitor and opto-coupler are typically connected externally. There is a time
delay while charging external capacitor Cfb from 3 V to 6 V using an internal 5 μA current source. This delay
prevents false triggering under transient conditions, but still allows the protection mechanism to operate
under true overload conditions.

4 Sync This pin is internally connected to the sync−detect comparator for valley switching. Typically the voltage of
the auxiliary winding is used as Sync input voltage and external resistors and capacitor are needed to make
delay to match valley point. The threshold of the internal sync comparator is 0.7 V / 0.2 V.

5 Vstr This pin is connected to the rectified AC line voltage source. At startup, the internal switch supplies internal
bias and charges an external storage capacitor placed between the Vcc pin and ground. Once the VCC
reaches 12 V, the internal switch is opened.

6, 7, 8 Drain The drain pins are designed to connect directly to the primary lead of the transformer and are capable of
switching a maximum of 650 V. Minimizing the length of the trace connecting these pins to the transformer
decreases leakage inductance.

www.onsemi.com
4
 FSQ0365, FSQ0265, FSQ0165, FSQ321

Table 3. ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise specified)

Symbol Parameter Min. Max. Unit

VSTR Vstr Pin Voltage 500 V

VDS Drain Pin Voltage 650 V

VCC Supply Voltage 20 V

VFB Feedback Voltage Range −0.3 9.0 V

VSync Sync Pin Voltage −0.3 9.0 V

IDM Drain Current Pulsed (Note 5) FSQ0365 12.0 A

FSQ0265 8.0

FSQ0165 4.0

FSQ321 1.5

EAS Single Pulsed Avalanche Energy (Note 6) FSQ0365 230 mJ

FSQ0265 140

FSQ0165 50

FSQ321 10

PD Total Power Dissipation 1.5 W

TJ Recommended Operating Junction Temperature −40 Internally Limited °C

TA Operating Ambient Temperature −40 +85 °C

TSTG Storage Temperature −55 +150 °C

ESD Human Body Model; JESD22−A114 CLASS 1C

Machine Model; JESD22−A115 CLASS B

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
5. Repetitive rating: pulse width limited by maximum junction temperature.
6. L = 51 mH, starting TJ = 25°C.

Table 4. THERMAL IMPEDANCE

Symbol Parameter Value Unit
8−DIP (Note 7)
qJA Junction−to−Ambient Thermal Resistance (Note 8) 80 °C/W

qJC Junction−to−Case Thermal Resistance (Note 9) 20

qJT Junction−to−Top Thermal Resistance (Note 10) 35

7. All items are tested with the standards JESD 51−2 and 51−10 (DIP)
8. Free−standing with no heat−sink, under natural convection
9. Infinite cooling condition − refer to the SEMI G30−88
10. Measured on the package top surface.

www.onsemi.com
5
 FSQ0365, FSQ0265, FSQ0165, FSQ321

Table 5. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)

Symbol Parameter Condition Min. Typ. Max. Unit

SENSEFET Section

BVDSS Drain−Source Breakdown Voltage VCC = 0 V, ID = 100 mA 650 V

IDSS Zero−Gate−Voltage Drain Current VDS = 650 V 100 A

RDS(ON) Drain−Source On− FSQ0365 TJ = 25°C, ID = 0.5 A 3.5 4.5 W

State Resistance
(Note 11) FSQ0265 5.0 6.0

FSQ0165 8.0 10.0

FSQ321 14.0 19.0

CISS Input Capacitance FSQ0365 VGS = 0 V, VDS = 25 V, f = 1 MHz 315 pF

FSQ0265 550

FSQ0165 250

FSQ321 162

COSS Output Capacitance FSQ0365 VGS = 0 V, VDS = 25 V, f = 1 MHz 47 pF

FSQ0265 38

FSQ0165 25

FSQ321 18

CRSS Reverse Transfer FSQ0365 VGS = 0 V, VDS = 25 V, f = 1 MHz 9.0 pF

Capacitance
FSQ0265 17.0

FSQ0165 10.0

FSQ321 3.8

td(on) Turn−On Delay FSQ0365 VDD = 350 V, ID = 25 mA 11.2 ns

FSQ0265 20.0

FSQ0165 12.0

FSQ321 9.5

tr Rise Time FSQ0365 VDD = 350 V, ID = 25 mA 34 ns

FSQ0265 15

FSQ0165 4

FSQ321 19

td(off) Turn−Off Delay FSQ0365 VDD = 350 V, ID = 25 mA 28.2 ns

FSQ0265 55.0

FSQ0165 30.0

FSQ321 33.0

tf Fall Time FSQ0365 VDD = 350 V, ID = 25 mA 32 ns

FSQ0265 25

FSQ0165 10

FSQ321 42
Burst−Mode Section

VBURH Burst−Mode Voltage TJ = 25°C, tPD = 200 ns (Note 12) 0.45 0.55 0.65 V
VBURL 0.25 0.35 0.45 V

VBUR(HYS) 200 mV

www.onsemi.com
6
 FSQ0365, FSQ0265, FSQ0165, FSQ321

Table 5. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) (continued)

Symbol Parameter Conditions Min. Typ. Max. Unit
Control Section
tON.MAX1 Maximum On Time1 All but FSQ321 TJ = 25°C 10.5 12.0 13.5 ms

tON.MAX2 Maximum On Time2 FSQ321 TJ = 25°C 6.35 7.06 7.77 ms

tB1 Blanking Time1 All but FSQ321 13.2 15.0 16.8 ms

tB2 Blanking Time2 FSQ321 7.5 8.2 ms

tW Detection Time Window TJ = 25°C, Vsync = 0 V 3.0 ms

DfS Switching Frequency Variation (Note 14) −25°C < TJ < 85°C ±5 ±10 %

IFB Feedback Source Current VFB = 0 V 700 900 1100 mA

DMIN Minimum Duty Cycle VFB = 0 V 0 %

VSTART UVLO Threshold Voltage After Turn−on 11 12 13 V

VSTOP 7 8 9 V
tS/S1 Internal Soft−Start Time 1 All but FSQ321 With Free−Running Frequency 15 ms

tS/S2 Internal Soft−Start Time 2 FSQ321 With Free−Running Frequency 10 ms

Protection Section
ILIM Peak Current Limit FSQ0365 TJ = 25°C, di/dt = 240 mA/ms 1.32 1.50 1.68 A

FSQ0265 TJ = 25°C, di/dt = 200 mA/ms 1.06 1.20 1.34

FSQ0165 TJ = 25°C, di/dt = 175 mA/ms 0.8 0.9 1.0

FSQ321 TJ = 25°C, di/dt = 125 mA/ms 0.53 0.60 0.67

VSD Shutdown Feedback Voltage VCC = 15 V 5.5 6.0 6.5 V

IDELAY Shutdown Delay Current VFB = 5 V 4.0 5.0 6.0 mA

tLEB Leading−Edge Blanking Time(13) 200 ns

VOVP Over−Voltage Protection VCC = 15 V, VFB = 2 V 5.5 6.0 6.5 V

tOVP Over−Voltage Protection Blanking Time 2 3 4 ms

TSD Thermal Shutdown Temperature (Note 13) 125 140 155 °C

Sync Section
VSH Sync Threshold Voltage 0.55 0.70 0.85 V

VSL 0.14 0.20 0.26 V

tSync Sync Delay Time (Notes 13, 14) 300 ns

Total Device Section

IOP Operating Supply Current VCC = 15 V 1 3 5 mA
(Control Part Only)

ISTART Start Current VCC = VSTART − 0.1 V 270 360 450 mA

(Before VCC Reaches VSTART)

ICH Startup Charging Current VCC = 0 V, VSTR = Minimum 40 V 0.65 0.85 1.00 mA

VSTR Minimum VSTR Supply Voltage 26 V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Pulse test: Pulse−Width = 300 ms, duty = 2%
12. Propagation delay in the control IC.
13. Though guaranteed, it is not 100% tested in production.
14. Includes gate turn−on time.

www.onsemi.com
7
 FSQ0365, FSQ0265, FSQ0165, FSQ321

TYPICAL PERFORMANCE CHARACTERISTICS

(Characteristics graphs are normalized at TA = 25°C)

1.2 1.2

1.0 1.0
Normalized

Normalized
0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0.0 0.0
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
Temperature [ °C] Temperature [ °C]

Figure 4. Operating Supply Current (IOP) vs. TA Figure 5. UVLO Start Threshold Voltage (VSTART)
vs. TA

1.2 1.2

1.0 1.0
Normalized

Normalized
0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0.0 0.0
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
Temperature [ °C] Temperature [ °C]

Figure 6. UVLO Stop Threshold Voltage (VSTOP) Figure 7. Startup Charging Current (ICH) vs. TA
vs. TA

1.2 1.2

1.0 1.0
Normalized
Normalized

0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0.0 0.0
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
Temperature [ °C] Temperature [ °C]

Figure 8. Initial Switching Frequency (fS) vs. TA Figure 9. Maximum On Time (tON.MAX) vs. TA

www.onsemi.com
8
 FSQ0365, FSQ0265, FSQ0165, FSQ321

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

(Characteristics graphs are normalized at TA = 25°C)

1.2 1.2

1.0 1.0
Normalized

Normalized
0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0.0 0.0
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
Temperature [ °C] Temperature [ °C]

Figure 10. Blanking Time (tB) vs. TA Figure 11. Feedback Source Current (IFB) vs. TA

1.2 1.2

1.0 1.0
Normalized

Normalized
0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0.0 0.0
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
Temperature [ °C] Temperature [ °C]

Figure 12. Shutdown Delay Current (IDELAY) vs. TA Figure 13. Burst Mode High Threshold Voltage
(Vburh) vs. TA

1.2 1.2

1.0 1.0
Normalized

Normalized

0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0.0 0.0
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
Temperature [ °C] Temperature [ °C]

Figure 14. Burst Mode Low Threshold Voltage Figure 15. Peak Current Limit (ILIM) vs. TA
(Vburl) vs. TA

www.onsemi.com
9
 FSQ0365, FSQ0265, FSQ0165, FSQ321

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

(Characteristics graphs are normalized at TA = 25°C)

1.2 1.2

1.0 1.0
Normalized

Normalized
0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0.0 0.0
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
Temperature [ °C] Temperature [ °C]

Figure 16. Sync High Threshold (VSH) vs. TA Figure 17. Sync Low Threshold (VSL) vs. TA

1.2 1.2

1.0 1.0
Normalized

Normalized
0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0.0 0.0
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
Temperature [ °C] Temperature [ °C]

Figure 18. Shutdown Feedback Voltage (VSD) Figure 19. Over−Voltage Protection (VOP) vs. TA
vs. TA

www.onsemi.com
10
 FSQ0365, FSQ0265, FSQ0165, FSQ321

FUNCTIONAL DESCRIPTION Rsense resistor would lead to incorrect feedback operation in

the Current Mode PWM control. To counter this effect, the
Startup power switch employs a leading−edge blanking (LEB)
At startup, an internal high−voltage current source circuit. This circuit inhibits the PWM comparator for a short
supplies the internal bias and charges the external capacitor time (tLEB) after the SENSEFET is turned on.
(Ca) connected to the VCC pin, as illustrated in Figure 20.
When VCC reaches 12 V, the power switch begins switching
VCC Vref
and the internal high−voltage current source is disabled. The Idelay IFB
power switch continues its normal switching operation and
VO VFB SENSEFET
the power is supplied from the auxiliary transformer FOD817A
3 OSC
D1 D2
winding unless VCC goes below the stop voltage of 8 V. CB 3R

+ Gate
VDC VFB* driver
R
KA431 −

Ca
OLP Rsense
VSD

FSQ0365RN Rev. 00
VCC Vstr
2 5
Figure 21. Pulse−Width−Modulation Circuit
ICH
Synchronization
Vref The FSQ−series employs a valley switching technique to
8V/12V VCC good
minimize the switching noise and loss. The basic waveforms
Internal
of the valley switching converter are shown in Figure 22. To
Bias minimize the MOSFET’s switching loss, the MOSFET
FSQ0365RN Rev.00
should be turned on when the drain voltage reaches its
Figure 20. Startup Circuit minimum value, as shown in Figure 22. The minimum drain
voltage is indirectly detected by monitoring the VCC
Feedback Control winding voltage, as shown in Figure 22.
Power Switch employs Current Mode control, as shown
Vds
in Figure 21. An opto−coupler (such as FOD817A) and
shunt regulator (such as KA431) are often used to
VRO
implement the feedback network. Comparing the feedback
voltage with the voltage across the RSENSE resistor makes it VRO
VDC
possible to control the switching duty cycle. When the
reference pin voltage of the shunt regulator exceeds the
internal reference voltage of 2.5 V, the opto−coupler LED Vsync tF
current increases, pulling down the feedback voltage and Vovp (6V)
reducing the duty cycle. This event typically occurs when
input voltage is increased or output load is decreased.
Pulse−by−Pulse Current Limit 0.7V

Because Current Mode control is employed, the peak 0.2V

current through the SENSEFET is limited by the inverting 300ns Delay
input of PWM comparator (VFB*), as shown in Figure 21. MOSFET Gate
Assuming that the 0.9mA current source flows only through
the internal resistor (3R + R = 2.8 kW), the cathode voltage
ON ON
of diode D2 is about 2.5 V. Since D1 is blocked when the
feedback voltage (VFB) exceeds 2.5V, the maximum voltage
FSQ0365RN Rev.00
of the cathode of D2 is clamped at this voltage, clamping
VFB*. Therefore, the peak value of the current through the Figure 22. Valley Resonant Switching Waveforms
SENSEFET is limited.
Leading−Edge Blanking (LEB) Protection Circuits
At the instant the internal SENSEFET is turned on, a The FSQ−series has several self−protective functions,
high−current spike usually occurs through the SENSEFET, such as Overload Protection (OLP), Abnormal
caused by primary−side capacitance and secondary−side Over−Current protection (AOCP), Over−Voltage Protection
rectifier reverse recovery. Excessive voltage across the (OVP), and Thermal Shutdown (TSD). All the protections

www.onsemi.com
11
 FSQ0365, FSQ0265, FSQ0165, FSQ321

are implemented as Auto−Restart Mode. Once the fault shutdown is the time required to charge CB from 2.8 V to
condition is detected, switching is terminated and the 6 V with 5 mA. A 20 ~ 50 ms delay is typical for most
SENSEFET remains off. This causes VCC to fall. When VCC applications.
falls down to the Under−Voltage Lockout (UVLO) stop
voltage of 8 V, the protection is reset and the startup circuit VFB FSQ0365RN Rev.00

charges the VCC capacitor. When the VCC reaches the start Overload protection
voltage of 12 V, the FSQ−series resumes normal operation. 6.0V
If the fault condition is not removed, the SENSEFET
remains off and VCC drops to stop voltage again. In this
manner, the auto−restart can alternately enable and disable
the switching of the power SENSEFET until the fault 2.8V
condition is eliminated. Because these protection circuits
are fully integrated into the IC without external components, t12= CFB*(6.0−2.8)/Idelay
the reliability is improved without increasing cost.
t1 t2 t
Fault
occurs Fault Figure 24. Overload Protection
VDS Power
removed
on
Abnormal Over−Current Protection (AOCP)
When the secondary rectifier diodes or the transformer
pins are shorted, a steep current with extremely high−di/dt
can flow through the SENSEFET during the LEB time.
Even though the FSQ−series has Overload Protection
(OLP), it is not enough to protect the FSQ−series in that
VCC abnormal case, since severe current stress is imposed on the
SENSEFET until OLP triggers. The FSQ−series has an
12V
internal Abnormal Over−Current Protection (AOCP) circuit
as shown in Figure 25. When the gate turn−on signal is
8V applied to the power SENSEFET, the AOCP block is
enabled and monitors the current through the sensing
t resistor. The voltage across the resistor is compared with a
preset AOCP level. If the sensing resistor voltage is greater
Normal Fault Normal
FSQ0365RN Rev. 00 operation situation operation
than the AOCP level, the set signal is applied to the latch,
resulting in the shutdown of the SMPS.
Figure 23. Auto−Restart Protection Waveforms

Overload Protection (OLP) 3R

Overload is defined as the load current exceeding its OSC
S Q
normal level due to an unexpected abnormal event. In this PWM
Gate
LEB
situation, the protection circuit should trigger to protect the 200ns
R Q driver

SMPS. However, even when the SMPS is in the normal R

operation, the overload protection circuit can be triggered
during load transition. To avoid this undesired operation, the
Rsense
overload protection circuit is designed to trigger only after +
1
AOCP GND
a specified time to determine whether it is a transient −
VOCP
situation or a true overload situation. Because of the FSQ0365RN Rev.00

pulse−by−pulse current limit capability, the maximum peak

current through the SENSEFET is limited, and therefore the Figure 25. Abnormal Over−Current Protection
maximum input power is restricted with a given input Over−Voltage Protection (OVP)
voltage. If the output consumes more than this maximum If the secondary−side feedback circuit malfunctions or a
power, the output voltage (VO) decreases below the set solder defect causes an opening in the feedback path, the
voltage. This reduces the current through the opto−coupler current through the opto−coupler transistor becomes almost
LED, which also reduces the opto−coupler transistor zero. Then VFB climbs up in a similar manner to the overload
current, thus increasing the feedback voltage (VFB). If VFB situation, forcing the preset maximum current to be supplied
exceeds 2.8 V, D1 is blocked and the 5 mA current source to the SMPS until the overload protection triggers. Because
starts to charge CB slowly up to VCC. In this condition, VFB more energy than required is provided to the output, the
continues increasing until it reaches 6 V, when the switching output voltage may exceed the rated voltage before the
operation is terminated, as shown in Figure 24. The delay for

www.onsemi.com
12
 FSQ0365, FSQ0265, FSQ0165, FSQ321

overload protection triggers, resulting in the breakdown of VO

the devices in the secondary side. To prevent this situation, VOset
an OVP circuit is employed. In general, the peak voltage of
the sync signal is proportional to the output voltage and the
FSQ−series uses a sync signal instead of directly monitoring VFB
the output voltage. If the sync signal exceeds 6 V, an OVP
is triggered, shutting down the SMPS. To avoid undesired 0.55V

triggering of OVP during normal operation, the peak voltage 0.35V

of the sync signal should be designed below 6 V.

IDS
Thermal Shutdown (TSD)
The SENSEFET and the control IC are built in one
package. This makes it easy for the control IC to detect the
abnormal over temperature of the SENSEFET. If the
temperature exceeds ~150°C, the thermal shutdown
triggers. VDS

Soft−Start
An internal soft−start circuit increases PWM comparator
inverting input voltage with the SENSEFET current slowly time
after it starts up. The typical soft−start time is 15 ms. The Switching Switching
disabled disabled
pulsewidth to the power switching device is progressively FSQ0365RN Rev.00 t1 t2 t3 t4
increased to establish the correct working conditions for
transformers, inductors, and capacitors. The voltage on the Figure 26. Waveforms of Burst Operation
output capacitors is progressively increased with the
Switching Frequency Limit
intention of smoothly establishing the required output
To minimize switching loss and Electromagnetic
voltage. This helps prevent transformer saturation and
Interference (EMI), the MOSFET turns on when the drain
reduces stress on the secondary diode during startup.
voltage reaches its minimum value in valley switching
Burst Operation operation. However, this causes switching frequency to
To minimize power dissipation in Standby Mode, the increases at light load conditions. As the load decreases, the
power switch enters Burst−Mode operation. As the load peak drain current diminishes and the switching frequency
decreases, the feedback voltage decreases. As shown in increases. This results in severe switching losses at
Figure 26, the device automatically enters Burst Mode when light−load condition, as well as intermittent switching and
the feedback voltage drops below VBURL (350 mV). At this audible noise. Because of these problems, the valley
point, switching stops and the output voltages start to drop switching converter topology has limitations in a wide range
at a rate dependent on standby current load. This causes the of applications.
feedback voltage to rise. Once it passes VBURH (550 mV), To overcome this problem, FSQ−series employs a
switching resumes. The feedback voltage then falls and the frequency−limit function, as shown in Figure 27 and
process repeats. Burst Mode alternately enables and disables Figure 28. Once the SENSEFET is turned on, the next
switching of the power SENSEFET, reducing switching loss turn−on is prohibited during the blanking time (tB). After the
in Standby Mode. blanking time, the controller finds the valley within the
detection time window (tW) and turns on the MOSFET, as
shown in Figure 27 and Figure 28 (cases A, B, and C). If no
valley is found during tW, the internal SENSEFET is forced
to turn on at the end of tW (case D). Therefore, FSQ devices
have a minimum switching frequency of 55kHz and a
maximum switching frequency of 67kHz, as shown in
Figure 28.

www.onsemi.com
13
 FSQ0365, FSQ0265, FSQ0165, FSQ321

tsmax=18ms When the resonant period is 2 ms

67kHz
IDS IDS A C Constant
B
frequency
59kHz
55kHz
A D
tB=15ms
Burst
mode
ts

IDS IDS

B PO
FSQ0365RN Rev. 00

tB=15ms
Figure 28. Switching Frequency Range

ts

IDS IDS

tB=15ms

ts

IDS IDS

tB=15ms
D
tW=3ms

tsmax=18ms FSQ0365RN Rev. 00

Figure 27. Valley Switching with Limited Frequency

www.onsemi.com
14
 FSQ0365, FSQ0265, FSQ0165, FSQ321

Typical Application Circuit of FSQ0365RN

Output Voltage
Application Power Switch Device Input Voltage Range Rated Output Power (Maximum Current)
DVD Player FSQ0365RN 85−265 VAC 19 W 5.1 V (1.0 A)
Power Supply 3.4 V (1.0 A)
12 V (0.4 A)
16 V (0.3 A)

Features Key Design Notes

• High efficiency ( > 77% at universal input) • The delay time for overload protection is designed to be
• Low standby mode power consumption (< 1 W at about 30 ms with C107 of 47nF. If faster/slower
230 VAC input and 0.5 W load) triggering of OLP is required, C107 can be changed to
• Reduce EMI noise through Valley Switching operation a smaller/larger value (eg. 100 nF for 60 ms).
• Enhanced system reliability through various protection • The input voltage of Vsync must be higher than −0.3 V.
functions By proper voltage sharing by R106 & R107 resistors,
the input voltage can be adjusted.
• Internal soft−start: 15 ms
• The SMD−type 100 nF capacitor must be placed as
close as possible to VCC pin to avoid malfunction by
abrupt pulsating noises and to improved surge
immunity.

Schematic
C209
47pF
T101
L201
EER2828
16V, 0.3A
RT101 11
1 D201 C201 C202
5D−9 UF4003 470mF
470mF
R105 C104 C210 35V 35V
R102 2
100kΩ 56kΩ 10nF 47pF
630V L202
C103 D101
R108 1N 4007 12V, 0.4A
33mF
62Ω 3
400V 10 D202 C203 C204
2 UF4003 470mF 470mF
IC101 35V 35V
FSQ0365RN 12
BD101 5 8
1 3 Vstr Drain
Bridge 7
Drain L203
Diode 4 6
Drain C106 C107
Sync 6 5.1V, 1A
100nF 22mF R103
3 Vcc 2 SMD 50V 5Ω C205 C206
4 FB D203
GND 4 1000mF 1000mF
C102 C105 D102 SB360
1 10V 10V
100nF,275V AC 47nF 1N 4004 R104
50V 12kΩ 5 L204
9
ZD101 3.4V, 1A
1N4746A D204 C207 C208
C110
6.2kΩ 6.2kΩ

1000mF
R106 R107

33pF SB360 1000mF

1N4148

50V 10V 10V

D103

LF101
40mH

8
C302
3.3nF R201
C101 510Ω
100nF R203
275VAC 6.2kΩ
R202
1kΩ R204 C209
20kΩ 100nF
IC202
TNR FOD817A
10D471K F101
FUSE IC201 R205
KA431 6kΩ

AC IN FSQ0365RN Rev:00

Figure 29. Demo Circuit of FSQ0365RN

www.onsemi.com
15
 FSQ0365, FSQ0265, FSQ0165, FSQ321

Transformer
EER2828
12
1 Np/2
Np/2 11
N16V N16V
Np/2 2 10
N12V N12V
3
9 N Na
3.4V

Na 4 8 N5.1V
6mm 3mm
5 N3.4V
7
Np/2
6 N
5.1V

FSQ0365RN Rev: 00

Figure 30. Transformer Schematic Diagram of FSQ0365RN

Table 6. WINDING SPECIFICATION

No. Pin (s " f) Wire Turns Winding Method
Np/2 3→2 0.25φ x1 50 Center Solenoid Winding
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
N3.4V 9→8 0.33φ x 2 4 Center Solenoid Winding
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
N5V 6→9 0.33φ x 1 2 Center Solenoid Winding
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
Na 4→5 0.25φ x 1 16 Center Solenoid Winding
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
N12V 10 →  12 0.33φ x 3 14 Center Solenoid Winding
Insulation: Polyester Tape t = 0.050 mm, 3−Layer
N16V 11 →  12 0.33φ x 3 18 Center Solenoid Winding
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
Np/2 2→1 0.25φ x 1 50 Center Solenoid Winding
Insulation: Polyester Tape t = 0.050 mm, 2−Layer

Table 7. TRANSFORMER ELECTRICAL CHARACTERISTICS

Pin Specification Remarks
Inductance 1−3 1.4 mH ± 10% 100 kHz, 1 V
Leakage 1−3 25 mH Maximum Short All Other Pins

Core & Bobbin

Core: EER2828 (Ae = 86.66 mm2)
Bobbin: EER2828

www.onsemi.com
16
 FSQ0365, FSQ0265, FSQ0165, FSQ321

Table 8. EVALUATION BOARD PART LIST

Part Value Note Part Value Note
Resistor Inductor
R102 56 kW 1W L201 10 mH
R103 5W 1/2 W L202 10 mH
R104 12 kW 1/4 W L203 4.9 mH
R105 100 kW 1/4 W L204 4.9 mH
R106 6.2 kW 1/4 W Diode

R107 6.2 kW 1/4 W D101 IN4007

R108 62 W 1W D102 IN4004
R201 510 W 1/4 W ZD101 1N4746A
R202 1 kW 1/4 W D103 1N4148
R203 6.2 kW 1/4 W D201 UF4003
R204 20 kW 1/4 W D202 UF4003
R205 6 kW 1/4 W D203 SB360

Capacitor D204 SB360

C101 100 nF / 275 VAC Box Capacitor
C102 100 nF / 275 VAC Box Capacitor IC
C103 33 mF / 400 V Electrolytic Capacitor IC101 FSQ0365RN Power Switch
C104 10 nF / 630 V Film Capacitor IC201 KA431 (TL431) Voltage reference
C105 47 nF / 50 V Mono Capacitor IC202 FOD817A Opto−coupler
C106 100 nF / 50 V SMD (1206) Fuse
C107 22 mF / 50 V Electrolytic Capacitor Fuse 2A/250V
C110 33 pF / 50 V Ceramic Capacitor NTC
C201 470 mF / 35 V Electrolytic Capacitor RT101 5D−9
C202 470 mF / 35 V Electrolytic Capacitor Bridge Diode

C203 470 mF / 35 V Electrolytic Capacitor BD101 2KBP06M2N257 Bridge Diode

C204 470 mF / 35 V Electrolytic Capacitor Line Filter

C205 1000 mF / 10 V Electrolytic Capacitor LF101 40 mH

C206 1000 mF / 10 V Electrolytic Capacitor Transformer

C207 1000 mF / 10 V Electrolytic Capacitor T101

C208 1000 mF / 10 V Electrolytic Capacitor Varistor

C209 100 nF / 50 V Ceramic Capacitor TNR 10D471K

SENSEFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

www.onsemi.com
17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
NOTES:
D A 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
E 2. CONTROLLING DIMENSION: INCHES.
H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
8 5
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
E1 NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
1 4
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
NOTE 8 LEADS UNCONSTRAINED.
c 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
b2 B END VIEW LEADS, WHERE THE LEADS EXIT THE BODY.
TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
NOTE 5
INCHES MILLIMETERS
A2 DIM MIN MAX MIN MAX
e/2 A −−−− 0.210 −−− 5.33
A NOTE 3 A1 0.015 −−−− 0.38 −−−
A2 0.115 0.195 2.92 4.95
L b 0.014 0.022 0.35 0.56
b2 0.060 TYP 1.52 TYP
C 0.008 0.014 0.20 0.36
D 0.355 0.400 9.02 10.16
SEATING
PLANE D1 0.005 −−−− 0.13 −−−
A1 E 0.300 0.325 7.62 8.26
C M E1 0.240 0.280 6.10 7.11
D1 e 0.100 BSC 2.54 BSC
eB −−−− 0.430 −−− 10.92
e eB L 0.115 0.150 2.92 3.81
8X b END VIEW M −−−− 10 ° −−− 10 °
0.010 M C A M B M NOTE 6
SIDE VIEW
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN XXXXXXXXX
3. DC − IN AWL
4. AC IN
5. GROUND YYWWG
6. OUTPUT
7. AUXILIARY
8. VCC
XXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42420B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: PDIP−8 PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

PDIP8 GW
CASE 709AJ
ISSUE O
DATE 31 JAN 2017

DOCUMENT NUMBER: 98AON13756G Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed
STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number:
October, DESCRIPTION:
2002 − Rev. 0 PDIP8 GW 1 PAGE 1 OFXXX2
 DOCUMENT NUMBER:
98AON13756G

PAGE 2 OF 2

ISSUE REVISION DATE

O RELEASED FOR PRODUCTION FROM FAIRCHILD MKT−MLSOP08A TO ON 31 JAN 2017
SEMICONDUCTOR. REQ. BY D. TRUHITTE.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

© Semiconductor Components Industries, LLC, 2017 Case Outline Number:

January, 2017 − Rev. O 709AJ
 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT: TECHNICAL SUPPORT
Email Requests to: orderlit@onsemi.com North American Technical Support: Europe, Middle East and Africa Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 00421 33 790 2910
ON Semiconductor Website: www.onsemi.com Phone: 011 421 33 790 2910 For additional information, please contact your local Sales Representative

◊ www.onsemi.com
1
Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

ON Semiconductor:
FSQ0265RN FSQ0365RN FSQ0365RLX FSQ321LX FSQ0265RLX FSQ0165RLX FSQ0365RL FSQ0265RL
FSQ0165RL FSQ321L FSQ321 FSQ0165RN