DAC1020,DAC1021,DAC1022,DAC1220,DAC1222

DAC1020/DAC1021/DAC1022 10-Bit Binary Multiplying D/A Converter

DAC1220/DAC1222 12-Bit Binary Multiplying D/A Converter

Literature Number: SNAS541

 DAC1220/DAC1222 12-Bit Binary Multiplying D/A Converter
DAC1020/DAC1021/DAC1022 10-Bit Binary Multiplying D/A Converter
May 1996

DAC1020/DAC1021/DAC1022
10-Bit Binary Multiplying D/A Converter
DAC1220/DAC1222
12-Bit Binary Multiplying D/A Converter
General Description
The DAC1020 and the DAC1220 are, respectively, 10 and (note 1 of electrical characteristics). The DAC1020,
12-bit binary multiplying digital-to-analog converters. A de- DAC1021 and DAC1022 are direct replacements for the 10-
posited thin film R-2R resistor ladder divides the reference bit resolution AD7520 and AD7530 and equivalent to the
current and provides the circuit with excellent temperature AD7533 family. The DAC1220 and DAC1222 are direct re-
tracking characteristics (0.0002%/§ C linearity error temper- placements for the 12-bit resolution AD7521 and AD7531
ature coefficient maximum). The circuit uses CMOS current family.
switches and drive circuitry to achieve low power consump-
tion (30 mW max) and low output leakages (200 nA max). Features
The digital inputs are compatible with DTL/TTL logic levels Y Linearity specified with zero and full-scale adjust only
as well as full CMOS logic level swings. This part, combined Y Non-linearity guaranteed over temperature
with an external amplifier and voltage reference, can be Y Integrated thin film on CMOS structure
used as a standard D/A converter; however, it is also very
attractive for multiplying applications (such as digitally con-
Y 10-bit or 12-bit resolution
trolled gain blocks) since its linearity error is essentially in- Y Low power dissipation 10 mW @ 15V typ
dependent of the voltage reference. All inputs are protected Y Accepts variable or fixed reference b25VsVREFs25V
from damage due to static discharge by diode clamps to V a Y 4-quadrant multiplying capability
and ground. Y Interfaces directly with DTL, TTL and CMOS
This part is available with 10-bit (0.05%), 9-bit (0.10%), and Y Fast settling timeÐ500 ns typ
8-bit (0.20%) non-linearity guaranteed over temperature Y Low feedthrough errorÐ(/2 LSB @ 100 kHz typ

Equivalent Circuit Note. Switches shown in digital high state

TL/H/5689 – 1

Ordering Information 10-BIT D/A CONVERTERS

Temperature Range 0§ C to 70§ C b 40§ C to 85§ C
0.05% DAC1020LCN AD7520LN,AD7530LN DAC1020LCV DAC1020LIV
Non-
0.10% DAC1021LCN AD7520KN,AD7530KN
Linearity
0.20% DAC1022LCN AD7520JN,AD7530JN
Package Outline N16A V20A
12-BIT D/A CONVERTERS
Temperature Range 0§ C to 70§ C b 40§ C to a 85§ C
Non- 0.05% DAC1220LCN AD7521LN,AD7531LN DAC1220LCJ AD7521LD,AD7531LD
Linearity 0.20% DAC1222LCN AD7521JN,AD7531JN DAC1222LCJ AD7521JD,AD7531JD
Package Outline N18A J18A
Note. Devices may be ordered by either part number.

C1996 National Semiconductor Corporation TL/H/5689 RRD-B30M96/Printed in U. S. A. http://www.national.com

 Absolute Maximum Ratings (Note 5) Operating Ratings
If Military/Aerospace specified devices are required, Min Max Units
please contact the National Semiconductor Sales Temperature (TA)
Office/Distributors for availability and specifications. DAC1020LIV, DAC1220LCJ,
V a to Gnd 17V DAC1222LCJ b 40 a 85 §C
VREF to Gnd g 25V DAC1020LCN, DAC1020LCV,
Digital Input Voltage Range V a to Gnd DAC1021LCN 0 a 70 §C
DC Voltage at Pin 1 or Pin 2 (Note 3) b 100 mV to V a DAC1022LCN, DAC1220LCN 0 a 70 §C
DAC1222LCN 0 a 70 §C
Storage Temperature Range b 65§ C to a 150§ C
Lead Temperature (Soldering, 10 sec.)
Dual-In-Line Package (plastic) 260§ C
Dual-In-Line Package (ceramic) 300§ C
ESD Susceptibility (Note 4) 800V

Electrical Characteristics (V a e 15V, VREF e 10.000V, TA e 25§ C unless otherwise specified)

DAC1020, DAC1021,
DAC1220, DAC1222
Parameter Conditions DAC1022 Units
Min Typ Max Min Typ Max
Resolution 10 12 Bits
Linearity Error TMINkTAkTMAX,
b 10V k VREF k a 10V,
(Note 1) End Point Adjustment Only
(See Linearity Error in Definition of Terms)
10-Bit Parts DAC1020, DAC1220 0.05 0.05 % FSR
9-Bit Parts DAC1021 0.10 0.10 % FSR
8-Bit Parts DAC1022, DAC1222 0.20 0.20 % FSR
Linearity Error Tempco b 10V s VREF s a 10V, 0.0002 0.0002 % FS/§ C
(Notes 1 and 2)
Full-Scale Error b 10V s VREF s a 10V, 0.3 1.0 0.3 1.0 % FS
(Notes 1 and 2)
Full-Scale Error Tempco TMINkTAkTMAX, 0.001 0.001 % FS/§ C
(Note 2)
Output Leakage Current TMINsTAsTMAX
IOUT 1 All Digital Inputs Low 200 200 nA
IOUT 2 All Digital Inputs High 200 200 nA
Power Supply Sensitivity All Digital Inputs High, 0.005 0.005 % FS/V
14VsV a s16V, (Note 2),
(Figure 2)
VREF Input Resistance 10 15 20 10 15 20 kX
Full-Scale Current Settling RL e 100X from 0 to 99. 95%
Time FS
All Digital Inputs Switched 500 500 ns
Simultaneously
VREF Feedthrough All Digital Inputs Low, 10 10 mVp-p
VREF e 20 Vp-p @ 100 kHz
J Package (Note 4) 6 9 6 9 mVp-p
N Package 2 5 2 5 mVp-p
Output Capacitance
IOUT 1 All Digital Inputs Low 40 40 pF
All Digital Inputs High 200 200 pF
IOUT 2 All Digital Inputs Low 200 200 pF
All Digital Inputs High 40 40 pF

http://www.national.com 2
Electrical Characteristics (V a e 15V, VREF e 10.000V, TA e 25§ C unless otherwise specified) (Continued)

DAC1020, DAC1021,
DAC1220, DAC1222
Parameter Conditions DAC1022 Units
Min Typ Max Min Typ Max
Digital Input (Figure 1)
Low Threshold TMINkTAkTMAX 0.8 0.8 V
High Threshold TMINkTAkTMAX 2.4 2.4 V
Digital Input Current TMINsTAsTMAX
Digital Input High 1 100 1 100 mA
Digital Input Low b 50 b 200 b 50 b 200 mA
Supply Current All Digital Inputs High 0.2 1.6 0.2 1.6 mA
All Digital Inputs Low 0.6 2 0.6 2 mA
Operating Power Supply (Figures 1 and 2) 5 15 5 15 V
Range
Note 1: VREF e g 10V and VREF e g 1V. A linearity error temperature coefficient of 0.0002% FS for a 45§ C rise only guarantees 0.009% maximum change in
linearity error. For instance, if the linearity error at 25§ C is 0.045% FS it could increase to 0.054% at 70§ C and the DAC will be no longer a 10-bit part. Note,
however, that the linearity error is specified over the device full temperature range which is a more stringent specification since it includes the linearity error
temperature coefficient.
Note 2: Using internal feedback resistor as shown in Figure 3 .
Note 3: Both IOUT 1 and IOUT 2 must go to ground or the virtual ground of an operational amplifier. If VREF e 10V, every millivolt offset between IOUT 1 or IOUT 2,
0.005% linearity error will be introduced.
Note 4: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 5: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 6: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, iJA, and the ambient temepature, TA. The maximum
allowable power dissipation at any temperature is PD e (TJMAX b TA)/iJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this
device, TJMAX e 125§ C, and the typical junction-to-ambient thermal resistance of the J18 package when board mounted is 85§ C/W. For the N18 package, iJA is
120§ C/W, for the N16 this number is 125§ C/W, and for the V20 this number is 95§ C/W.

Typical Performance Characteristics

TL/H/5689 – 2
FIGURE 1. Digital Input Threshold vs FIGURE 2. Gain Error Variation vs V a
Ambient Temperature

3 http://www.national.com
 Typical Applications
The following applications are also valid for 12-bit systems Operational Amplifier VOS Adjust (Figure 3 )
using the DAC1220 and 2 additional digital inputs. Connect all digital inputs, A1 – A10, to ground and adjust the
Operational Amplifier Bias Current (Figure 3 ) potentiometer to bring the op amp VOUT pin to within g 1
mV from ground potential. If VREF is less than 10V, a finer
The op amp bias current, Ib, flows through the 15k internal
VOS adjustment is required. It is helpful to increase the reso-
feedback resistor. BI-FET op amps have low Ib and, there-
lution of the VOS adjust procedure by connecting a 1 kX
fore, the 15k c Ib error they introduce is negligible; they are
resistor between the inverting input of the op amp to
strongly recommended for the DAC1020 applications.
ground. After VOS has been adjusted, remove the 1 kX.
VOS Considerations
Full-Scale Adjust (Figure 4 )
The output impedance, ROUT, of the DAC is modulated by
Switch high all the digital inputs, A1 – A10, and measure the
the digital input code which causes a modulation of the op-
op amp output voltage. Use a 500X potentiometer, as
erational amplifier output offset. It is therefore recommend-
shown, to bring ll VOUT ll to a voltage equal to VREF c
ed to adjust the op amp VOS. ROUT is E 15k if more than 4
1023/1024.
digital inputs are high; ROUT is E 45k if a single digital input
is high, and ROUT approaches infinity if all inputs are low.

SELECTING AND COMPENSATING THE OPERATIONAL AMPLIFIER

Circuit Settling Circuit Small

Op Amp Family CF Ri P VW
Time, ts Signal BW
LF357 10 pF 2.4k 25k Va 1.5 ms 1M
LF356 22 pF % 25k Va 3 ms 0.5M
LF351 24 pF % 10k Vb 4 ms 0.5M
LM741 0 % 10k Vb 40 ms 200 kHz

TL/H/5689 – 3

# J
A1 A2 A3 A10
VOUT e b VREF a a a###
2 4 8 1024
b 10V s VREF s 10V
1023
0 s VOUT s b VREF
1024
where AN e 1 if the AN digital input is high
AN e 0 if the AN digital input is low

FIGURE 3. Basic Connection: Unipolar or 2-Quadrant Multiplying

Configuration (Digital Attenuator)

http://www.national.com 4
Typical Applications (Continued)

FIGURE 4. Full-Scale Adjust

FIGURE 5. Alternate Full-Scale Adjust: (Allows Increasing or Decreasing the Gain)

#2 J
A1 A2 A3 A10 TL/H/5689 – 4
VOUT 1 e b VREF a a a###
4 8 1024

#2 J #2 J
A1 A2 A3 A10 B1 B2 B3 B10
VOUT2 e VREF a a a### c a a a###
4 8 1024 4 8 1024
where VREF can be an AC signal

FIGURE 6. Precision Analog-to-Digital Multiplier

5 http://www.national.com
 Typical Applications (Continued)
COMPLEMENTARY OFFSET BINARY
(BIPOLAR) OPERATION
DIGITAL INPUT VOUT
0 0 0 0 0 0 0 0 0 0 a VREF
0 0 0 0 0 0 0 0 0 1 VREF c 1022/1024
0 1 1 1 1 1 1 1 1 1 VREF c 2/1024
1 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1 bVREF c 2/1024
1 1 1 1 1 1 1 1 1 1 bVREF (1022/1024)
Note that:

# J
VREF 1023
# IOUT 1 a IOUT 2 e c
RLADDER 1024
# By doubling the output range we get half the
TL/H/5689–5
resolution
# J
A1 A2 A10 1
VOUT e b VREF a a###a b # The 10M resistor, adds a 1 LSB ‘‘thump’’, to
2 4 1024 1024
where: AN e a 1 if AN input is high
allow full offset binary operation where the out-
put reaches zero for the half-scale code. If
AN e b 1 if AN input is low
symmetrical output excursions are required,
omit the 10M resistor.

FIGURE 7. Bipolar 4-Quadrant Multiplying Configuration

Operational Amplifiers VOS Adjust (Figure 7 ) Gain Adjust (Full-Scale Adjust)

a) Switch all the digital inputs high; adjust the VOS potenti- Assuming that the external 10k resistors are matched to
ometer of op amp B to bring its output to a value equal better than 0.1%, the gain adjust of the circuit is the same
tob(VREF/1024) (V). with the one previously discussed.
b) Switch the MSB high and the remaining digital inputs
low. Adjust the VOS potentiometer of op amp A, to bring
its output value to within a 1 mV from ground potential.
For VREF k 10V, a finer adjust is necessary, as already
mentioned in the previous application.

TL/H/5689 – 6
TRUE OFFSET BINARY OPERATION R2 AV b
# R4 e (2AVb b 1) R, e ,
R1 AV b b 1
DIGITAL INPUT VOUT VOUT(PEAK)
R3 a R1 ll R2 e R; AVb e , R e 20k
1 1 1 1 1 1 1 1 1 1 VREF c 1022/1024 VREF

1 0 0 0 0 0 0 0 0 0 0 # Example: VREF e 2V, VOUT (swing) j g 10V: AVb e 5V

Then R4 e 9R, R1 e 0.8 R2. If R1 e 0.2R then R2 e 0.25R,
0 0 0 0 0 0 0 0 0 0 b VREF
R3 e 0.64R
ts e 1.8 ms
use LM336 for a voltage reference FIGURE 9. Bipolar Configuration with
Increased Output Swing
FIGURE 8. Bipolar Configuration with a Single Op Amp

http://www.national.com 6
Typical Applications (Continued)

b VREF
VOUT e

# J
A1 A2 A3 A10
a a a...
2 4 8 1024
where: VREF can be an AC signal
# By connecting the DAC in the feedback loop of an opera-
tional amplifier a linear digitally control gain block can be
realized
# Note that with all digital inputs low, the gain of the amplifier
is infinity, that is, the op amp will saturate. In other words, we
cannot divide the VREF by zero!
FIGURE 10. Analog-to-Digital Divider (or Digitally Gain Controlled Amplifier)

TL/H/5689 – 7

A1 A2 A10
a a...a

# J
2 4 1024 1023 b N
VOUT e VREF or VOUT e VREF
A1 A2 A10 N
% –
a a...a
2 4 1024
where: 0 s N s 1023
N e 0 for AN e all zeros
N e 1 for A10 e 1, A1–A9 e 0
.
.
.
N e 1023 for AN e all 1’s
FIGURE 11. Digitally controlled Amplifier-Attenuator

7 http://www.national.com
 Typical Applications (Continued)

TL/H/5689 – 8

f
# Output frequency e CLK; fMAX j 2 kHz
512
# Output voltage range e 0V b 10V peak
# THD k 0.2%
# Excellent amplitude and frequency stability with temperature
# Low pass filter shown has a 1 kHz corner (for output frequencies below 10 Hz,
filter corner should be reduced)
# Any periodic function can be implemented by modifying the contents of the look
up table ROM
# No start up problems
FIGURE 12. Precision Low Frequency Sine Wave Oscillator Using Sine Look-Up ROM

http://www.national.com 8
Typical Applications (Continued)

MM74C00 Ð NAND gates

MM74C32 Ð OR gates
MM74C74 Ð D flip-flop
MM74C193 Ð Binary up/
down counters

TL/H/5689 – 9

# Binary up/down counter digitally ‘‘ramps’’ the DAC

output
# Can stop counting at any desired 10-bit input code
# Senses up or down count overflow and automatically
reverses direction of count

FIGURE 13. A Useful Digital Input Code Generator for DAC Attenuator or Amplifier Circuits

9 http://www.national.com
 Definition of Terms
Resolution: Resolution is defined as the reciprocal of the Power Supply Sensitivity: Power supply sensitivity is a
number of discrete steps in the D/A output. It is directly measure of the effect of power supply changes on the D/A
related to the number of switches or bits within the D/A. For full-scale output.
example, the DAC1020 has 210 or 1024 steps while the Settling Time: Full-scale settling time requires a zero to full-
DAC1220 has 212 or 4096 steps. Therefore, the DAC1020 scale or full-scale to zero output change. Settling time is the
has 10-bit resolution, while the DAC1220 has 12-bit resolu- time required from a code transition until the D/A output
tion. reaches within g (/2 LSB of final output value.
Linearity Error: Linearity error is the maximum deviation Full-Scale Error: Full-scale error is a measure of the output
from a straight line passing through the endpoints of the error between an ideal D/A and the actual device output.
D/A transfer characteristic. It is measured after calibrating Ideally, for the DAC1020 full-scale is VREFb1 LSB. For
for zero (see VOS adjust in typical applications) and full- VREF e 10V and unipolar operation, VFULL-SCA-
scale. Linearity error is a design parameter intrinsic to the LE e 10.0000VÐ9.8 mV e 9.9902V. Full-scale error is ad-
device and cannot be externally adjusted. justable to zero as shown in Figure 5 .

TL/H/5689 – 10
a b1 b2
(a) End point test after zero and full-scale adjust. (b) By shifting the full-scale calibration on of the DAC of
The DAC has 1 LSB linearity error. Figure (b1) we could pass the ‘‘best straight line’’ (b2)
test and meet the g (/2 linearity error specification.

Note. (a), (b1) and (b2) above illustrate the difference between ‘‘end point’’ National’s linearity test (a) and ‘‘best straight line’’ test. Note that both devices in (a) and
(b2) meet the g (/2 LSB linearity error specification but the end point test is a more ‘‘real life’’ way of characterizing the DAC.

Connection Diagrams
DAC102X DAC1020 DAC122X
Dual-In-Line Package PLCC Package Dual-In-Line Package

TL/H/5689 – 12

TL/H/5689–13

TL/H/5689 – 11

http://www.national.com 10
11 http://www.national.com
 Physical Dimensions inches (millimeters) unless otherwise noted

Cavity Dual-In-Line Package (J)

Order Number DAC1220LCJ or DAC1222LCJ
NS Package Number J18A

Molded Dual-In-Line Package (N)

Order Number DAC1020LCN, DAC1021LCN or DAC1022LCN
NS Package Number N16A

http://www.national.com 12
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N)

Order Number DAC1220LCN, DAC1221LCN or DAC1222LCN
NS Package Number N18A

13 http://www.national.com
DAC1020/DAC1021/DAC1022 10-Bit Binary Multiplying D/A Converter
DAC1220/DAC1222 12-Bit Binary Multiplying D/A Converter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Plastic Leaded Chip Carrier (V)

Order Number DAC1020LCV or DAC1020LIV
NS Package Number V20A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

National Semiconductor National Semiconductor National Semiconductor National Semiconductor

Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: a49 (0) 180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2308
Arlington, TX 76017 Email: europe.support @ nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel: a49 (0) 180-530 85 85 Tsimshatsui, Kowloon
Fax: 1(800) 737-7018 English Tel: a49 (0) 180-532 78 32 Hong Kong
Fran3ais Tel: a49 (0) 180-532 93 58 Tel: (852) 2737-1600
http://www.national.com Italiano Tel: a49 (0) 180-534 16 80 Fax: (852) 2736-9960

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
 IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Audio www.ti.com/audio Communications and Telecom www.ti.com/communications
Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers
Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps
DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy
DSP dsp.ti.com Industrial www.ti.com/industrial
Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical
Interface interface.ti.com Security www.ti.com/security
Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated