Com20020i3v HT

COM20020I 3.
3V
5Mbps ARCNET (ANSI
878.1) Controller with
2K x 8 On-Chip RAM
Datasheet
Product Features
New Features: Eight, 256 Byte Pages Allow Four Pages TX and
RX Plus Scratch-Pad Memory
- Data Rates up to 5 Mbps
Next ID Readable
- Programmable Reconfiguration Times
Internal Clock Scaler and Clock Multiplier for
28 Pin PLCC and 48 Pin TQFP Packages; Adjusting Network Speed
Lead-free RoHS Compliant Packages also o o
Operating Temperature Range of -40 C to +85 C
available
Self-Reconfiguration Protocol
Ideal for Industrial/Factory/Building Automation
and Transportation Applications Supports up to 255 Nodes
Deterministic, (ANSI 878.1), Token Passing Supports Various Network Topologies (Star, Tree,
ARCNET Protocol Bus...)
Minimal Microcontroller and Media Interface CMOS, Single +3.3V Supply
Logic Required
Duplicate Node ID Detection
Flexible Interface For Use With All
Powerful Diagnostics
Microcontrollers or Microprocessors
Receive All Packets Mode
Automatically Detects Type of Microcontroller
Interface Flexible Media Interface:
2Kx8 On-Chip Dual Port RAM - Traditional Hybrid Interface For Long
Distances up to Four Miles at 2.5Mbps
Command Chaining for Packet Queuing
- RS485 Differential Driver Interface For Low
Sequential Access to Internal RAM
Cost, Low Power, High Reliability
Software Programmable Node ID
SMSC COM20020I 3.3V 1 Revision 12-06-06
DATASHEET
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
ORDERING INFORMATION
Order Numbers:
COM20020I3VLJP for 28 pin PLCC package

COM20020I3V-DZD for 28 pin PLCC package lead-free RoHS compliant package
COM20020I3V-HD for 48 pin TQFP package
COM20020I3V-HT for 48 pin TQFP lead-free RoHS compliant package
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Copyright © 2006 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
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Revision 12-06-06 2 SMSC COM20020I 3.3V
DATASHEET
TABLE OF CONTENTS
2.0 GENERAL DESCRIPTION..............................................................................................................................5
3.0 PIN CONFIGURATIONS .................................................................................................................................6
4.0 DESCRIPTION OF PIN FUNCTIONS FOR TQFP ..........................................................................................8
5.0 PROTOCOL DESCRIPTION .........................................................................................................................11

5.1 NETWORK PROTOCOL ..................................................................................................................................11
5.2 DATA RATES ...............................................................................................................................................11
5.3 NETWORK RECONFIGURATION.......................................................................................................................12
5.4 BROADCAST MESSAGES ...............................................................................................................................12
5.5 EXTENDED TIMEOUT FUNCTION .....................................................................................................................12
5.6 LINE PROTOCOL ..........................................................................................................................................13
6.0 SYSTEM DESCRIPTION...............................................................................................................................15
6.1 MICROCONTROLLER INTERFACE ....................................................................................................................15
6.2 TRANSMISSION MEDIA INTERFACE .................................................................................................................19
7.0 FUNCTIONAL DESCRIPTION ......................................................................................................................24
7.1 MICROSEQUENCER ......................................................................................................................................24
7.2 INTERNAL REGISTERS...........................................................................................................................25
7.3 INTERNAL RAM ............................................................................................................................................35
7.4 COMMAND CHAINING ....................................................................................................................................40
7.5 INITIALIZATION SEQUENCE ............................................................................................................................42
7.6 IMPROVED DIAGNOSTICS ..............................................................................................................................42
8.0 OPERATIONAL DESCRIPTION ...................................................................................................................45
8.1 MAXIMUM GUARANTEED RATINGS* ................................................................................................................45
8.2 DC ELECTRICAL CHARACTERISTICS ...............................................................................................................45
9.0 TIMING DIAGRAMS......................................................................................................................................48
10.0 PACKAGE OUTLINES..................................................................................................................................60
11.0 APPENDIX A.................................................................................................................................................62
12.0 APPENDIX B.................................................................................................................................................65

12.1 SOFTWARE IDENTIFICATION OF THE COM20020I REV B, REV C AND REV D .....................................................65
LIST OF FIGURES
Figure 1 - COM20020I OPERATION ...........................................................................................................................10

Figure 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE ...............................................16
Figure 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE......................................17
Figure 4 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE...............................................................................18
Figure 5 - COM20020I NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS................................................20
Figure 6 - DIPULSE WAVEFORM FOR DATA OF 1-1-0 .............................................................................................20
Figure 7 - INTERNAL BLOCK DIAGRAM ....................................................................................................................22
Figure 8 – SEQUENTIAL ACCESS OPERATION........................................................................................................35
Figure 9 – RAM BUFFER PACKET CONFIGURATION ..............................................................................................38
Figure 10 - COMMAND CHAINING STATUS REGISTER QUEUE ...............................................................................40
Figure 11 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE ..................................................48
Figure 12 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE ..................................................49
Figure 13 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE.................................................50
SMSC COM20020I 3.3V Page 3 Revision 12-06-06
DATASHEET
Figure 14 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE.................................................51

Figure 15 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE .........................................52
Figure 19 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE .......................................56
Figure 20 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE .......................................57
Figure 21 – NORMAL MODE TRANSMIT OR RECEIVE TIMING ...............................................................................58
Figure 22 – BACKPLANE MODE TRANSMIT OR RECEIVE TIMING .........................................................................58
Figure 23 – TTL INPUT TIMING ON XTAL1 PIN .........................................................................................................59
Figure 24 – RESET AND INTERRUPT TIMING...........................................................................................................59
Figure 25 - 28 PIN PLCC PACKAGE DIMENSIONS ...................................................................................................60
Figure 26 - 48 PIN TQFP PACKAGE OUTLINE...........................................................................................................61
Figure 27 - EFFECT OF THE EF BIT ON THE TA/RI BIT ...........................................................................................63
LIST OF TABLES
Table 1 - Typical Media ................................................................................................................................................23

Table 2 - Read Register Summary...............................................................................................................................24
Table 3 - Write Register Summary ...............................................................................................................................25
Table 4 - Status Register ..............................................................................................................................................28
Table 5 - Diagnostic Status Register.............................................................................................................................29
Table 6 - Command Register........................................................................................................................................30
Table 7 - Address Pointer High Register .......................................................................................................................31
Table 8 - Address Pointer Low Register........................................................................................................................31
Table 9 - Sub Address Register ...................................................................................................................................31
Table 10 - Configuration Register ................................................................................................................................31
Table 11 - Setup 1 Register ..........................................................................................................................................33
Table 12 - Setup 2 Register ..........................................................................................................................................34
DATASHEET
2.0 General Description

SMSC's COM20020I is a member of the family of Embedded ARCNET Controllers from Standard Microsystems
Corporation. The device is a general purpose communications controller for networking microcontrollers and intelligent
peripherals in industrial, automotive, and embedded control environments using an ARCNET protocol engine. The
flexible microcontroller and media interfaces, eight-page message support, and extended temperature range of the
COM20020I make it the only true network controller optimized for use in industrial, embedded, and automotive
applications. Using an ARCNET protocol engine is the ideal solution for embedded control applications because it
provides a deterministic token-passing protocol, a highly reliable and proven networking scheme, and a data rate of up
to 5 Mbps when using the COM20020I.
A token-passing protocol provides predictable response times because each network event occurs within a
predetermined time interval, based upon the number of nodes on the network. The deterministic nature of ARCNET is
essential in real time applications. The integration of the 2Kx8 RAM buffer on-chip, the Command Chaining feature, the
5 Mbps maximum data rate, and the internal diagnostics make the COM20020I the highest performance embedded
communications device available. With only one COM20020I and one microcontroller, a complete communications node
may be implemented.
For more details on the ARCNET protocol engine and traditional dipulse signaling schemes, please refer
to the ARCNET Local Area Network Standard, available from Standard Microsystems Corporation or the
ARCNET Designer's Handbook, available from Datapoint Corporation.
For more detailed information on cabling options including RS485, transformer-coupled RS-485 and Fiber
Optic interfaces, please refer to the following technical note which is available from Standard
Microsystems Corporation: Technical Note 7-5 - Cabling Guidelines for the COM20020I ULANC.
DATASHEET
3.0 PIN CONFIGURATIONS
nRESET IN
nPULSE2
nTXEN
nINTR
RXIN
24
VSS
nCS
A0/nMUX 1 VDD
A1 2 23 nRD/nDS
A2/ALE 3 22 nWR/DIR 25 24 23 22 21 20 19
nWR/DIR 26 18 nPULSE 1
AD0 4 21 nCS
nRD/nDS 27 17 XTAL2
AD1 5 20 nINTR
AD2 19 VDD 28 16 XTAL1

6 nRESET IN
D3 7 18 nTXEN A0/nMUX 1 15 VDD
D4 8 17 RXIN A1 2 14 VSS
D5 9 16 nPULSE2
A2/ALE 3 13 N/C
D6 10 15 nPULSE1
AD0 4 12 D7
D7 11 14 XTAL2 5 6 7 8 9 10 11
VSS 12 13 XTAL1
D3
D4
D5
D6
AD1
AD2
VSS
Package: 28-Pin PLCC
Packages: 24-Pin DIP or 28-Pin PLCC
Ordering Information:
Ordering Information:
COM20020 I P
COM20019 I P
PACKAGE TYPE: P = Plastic, LJP = PLCC
PACKAGE TYPE: P = Plastic, LJP = PLCC
TEMP
TEMPRANGE:
RANGE: (Blank) = Commercial:
1 = Industrial: -40° C to0°C
75°toC+70°C
I = Industrial: -40°C to +85°C
DEVICETYPE:
DEVICE TYPE: 20019
20020==Universal
UniversalLocal
LocalArea
Area Network
Network Controller
(with 2K x 8 RAM)
(with 2K x 8 RAM)
DATASHEET
A0/nMUX
nRD/nDS
nWR/DIR
A2/ALE
VDD
VDD
VSS
N/C
N/C
N/C
N/C
A1
48
47
46
45
44
43
42
41
40
39
38
37
AD0 1 36 nCS
AD1 2 35 VDD
N/C 3 34 nINTR
AD2 4 33 N/C
COM20020I
N/C 5 32 VDD
VSS 6 48 PIN TQFP 31 nRESET
D3 7 30 VSS
VDD 8 29 nTXEN
D4 9 28 RXIN
D5 10 27 N/C
VSS 11 26 BUSTMG
D6 12 25 nPULSE2
13
14
15
16
17
18
19
20
21
22
23
24
XTAL1
XTAL2
N/C
N/C
N/C
N/C
N/C
VDD
nPULSE1
D7
VSS
VSS
DATASHEET
4.0 DESCRIPTION OF PIN FUNCTIONS FOR TQFP

PIN NO NAME SYMBOL I/O DESCRIPTION
MICROCONTROLLER INTERFACE
44, 45, Address A0/nMUX IN On a non-multiplexed mode, A0-A2 are address
46 0-2 A1 IN input bits. (A0 is the LSB) On a multiplexed
address/data bus, nMUX tied Low, A1 is left open,
and ALE is tied to the Address Latch Enable signal.
A2/ALE IN A1 is connected to an internal pull-up resistor.
1, 2, 4, Data 0-7 AD0-AD2, I/O On a non-multiplexed bus, these signals are used as
7, 9, 10, D3-D7 the lower byte data bus lines. On a multiplexed
12, 13 address/data bus, AD0-AD2 act as the address lines
(latched by ALE) and as the low data lines. D3-D7
are always used for data only. These signals are
connected to internal pull-up resistors.
47, 48, N/C N/C I/O Non-connection
3, 5,
14-17
37 nWrite/ nWR/DIR IN nWR is for 80xx CPU, nWR is Write signal input.
Direction Active Low.
DIR is for 68xx CPU, DIR is Bus Direction signal
input. (Low: Write, High: Read.)
39 nRead/ nRD/nDS IN nRD is for 80xx CPU, nRD is Read signal input.
nData Active Low.
Strobe nDS is for 68xx CPU, nDS is Data Strobe signal
input. Active Low.
31 nReset In nRESET IN Hardware reset signal. Active Low.
34 nInterrupt nINTR OUT Interrupt signal output. Active Low.
36 nChip nCS IN Chip Select input. Active Low.
Select
42 N/C N/C OUT Non-connection
26 Read/Write BUSTMG IN Read and Write Bus Access Timing mode selecting
Bus Timing signal. Status of this signal effects CPU and DMA
Select Timing.
L: High speed timing mode (only for non-multiplexed
bus)
H: Normal timing mode
This signal is connected to internal pull-up registers.
33 N/C N/C OUT
35 Power VDD PWR
Supply
38 Power VDD PWR +3.3 volts power supply pins.
Supply
40 N/C N/C Non-connection
DATASHEET
PIN NO NAME SYMBOL I/O DESCRIPTION

TRANSMISSION MEDIA INTERFACE
24 nPulse 1 nPULSE1 OUT In Normal Mode, these active low signals carry the
transmit data information, encoded in pulse format as
DIPULSE waveform. In Backplane Mode, the
nPULSE1 signal driver is programmable (push/pull or
25 nPulse 2 nPULSE2 I/O open-drain), while the nPULSE2 signal provides a
clock with frequency of doubled data rate. nPULSE1
is connected to a weak internal pull-up resistor on
the open/drain driver in backplane mode.
28 Receive In RXIN IN This signal carries the receive data information from
the line transceiver.
29 nTransmit nTXEN OUT Transmission Enable signal. Active polarity is
Enable programmable through the nPULSE2 pin.
nPULSE2 floating before power-up;
nTXEN active low
nPULSE2 grounded before power-up;
nTXEN active high (this option is only available in
Back Plane mode)
21 Crystal XTAL1 IN An external crystal should be connected to these
22 Oscillator XTAL2 OUT pins. Oscillation frequency range is from 10 MHz to
20 MHz. If an external TTL clock is used instead, it
must be connected to XTAL1 with a 390ohm pull-up
resistor, and XTAL2 should be left floating.
8, 20, Power VDD PWR +5 Volt power supply pins.
32, 35, Supply
38, 43
6, 11, Ground VSS PWR Ground pins.
18, 23,
30, 41
3, 5, N/C N/C Non-connection
14-17,
19, 27,
33, 40,
42, 48
DATASHEET
Power On
Reconfigure Send
Timer has Reconfigure
Timed Out Burst
Read Node ID
Write ID to
RAM Buffer
1
Set NID=ID
Start Y Invitation N
Reconfiguration to Transmit to
Timer (420 mS)* this ID?
N Y
TA? Y Free Buffer N
Enquiry to
this ID? Y N
Transmit Y N SOH?
NAK RI?
Y N
RI?
Transmit
ACK Write SID N
Broadcast? to Buffer No Activity
N Transmit for 41
Y Free Buffer uS?
Enquiry DID Y
Send No Y Y
Activity =0?
Packet
N for 37.4 Set NID=ID
us? N N
Y N Broadcast
ACK? Enabled?
DID Start Timer:
Y =ID?
Was Packet Y N N Y T=(255-ID)
NAK? Set TA Y x 73 us
Broadcast?
1 Write Buffer
N with Packet Activity Y
On Line?
No Y
Activity Set TA Pass the
for 37.4 Token N
us?
N N
N CRC T=0?
No OK?
Increment Y Activity N Y
NID for 37.4 Y
N Y
ACK? Set TMA us?
LENGTH N
OK?
Y
Y
DID Set RI
- ID refers to the identification number of the ID assigned to this node. =0?
- NID refers to the next identification number that receives the token N
after this ID passes it.
- SID refers to the source identification. DID N
- DID refers to the destination identification. =ID?
- SOH refers to the start of header character; preceeds all data packets. Y
* Reconfig timer is programmable via setup2 register bits 1, 0. SEND ACK
Note - All time values are valid for 5 Mbps.
FIGURE 1 - COM20020I OPERATION
DATASHEET
5.0 PROTOCOL DESCRIPTION

5.1 Network Protocol
Communication on the network is based on a token passing protocol. Establishment of the network configuration and
management of the network protocol are handled entirely by the COM20020I's internal microcoded sequencer. A
processor or intelligent peripheral transmits data by simply loading a data packet and its destination ID into the
COM20020I's internal RAM buffer, and issuing a command to enable the transmitter. When the COM20020I next
receives the token, it verifies that the receiving node is ready by first transmitting a FREE BUFFER ENQUIRY message.
If the receiving node transmits an ACKnowledge message, the data packet is transmitted followed by a 16-bit CRC. If
the receiving node cannot accept the packet (typically its receiver is inhibited), it transmits a Negative AcKnowledge
message and the transmitter passes the token. Once it has been established that the receiving node can accept the
packet and transmission is complete, the receiving node verifies the packet. If the packet is received successfully, the
receiving node transmits an ACKnowledge message (or nothing if it is not received successfully) allowing the transmitter
to set the appropriate status bits to indicate successful or unsuccessful delivery of the packet. An interrupt mask permits
the COM20020I to generate an interrupt to the processor when selected status bits become true. Figure 1 is a flow
chart illustrating the internal operation of the COM20020I connected to a 20 MHz crystal oscillator.
5.2 Data Rates

The COM20020I is capable of supporting data rates from 156.25 Kbps to 5 Mbps. The following protocol description
assumes a 5 Mbps data rate. To attain the faster data rates, the clock frequency may be doubled by the internal clock
multiplier (see next section). For slower data rates, an internal clock divider scales down the clock frequency. Thus all
timeout values are scaled as shown in the following table:
Example: IDLE LINE Timeout @ 5 Mbps = 41 μs. IDLE LINE Timeout for 156.2 Kbps is 41 μs * 32 = 1.3 ms
INTERNAL
CLOCK CLOCK TIMEOUT SCALING
FREQUENCY PRESCALER DATA RATE FACTOR (MULTIPLY BY)
40 MHz Div. by 8 5 Mbps 1
20 MHz Div. by 8 2.5 Mbps 2
Div. by 16 1.25 Mbps 4
Div. by 32 625 Kbps 8
Div. by 64 312.5 Kbps 16
Div. by 128 156.25 Kbps 32
Selecting Clock Frequencies Above 2.5 Mbps

To realize a 5 Mbps network, an external 40 MHz clock must be input. However, since 40 MHz is near the frequency
of FM radio band, it is not practical for use for noise emission reasons. Therefore, higher frequency clocks are
generated from the 20 MHz crystal as selected through two bits in the Setup2 register, CKUP[1,0] as shown below.
The selected clock is supplied to the ARCNET controller.
CKUP1 CKUP0 CLOCK FREQUENCY (DATA RATE)

0 0 20 MHz (Up to 2.5Mbps) Default (Bypass)
0 1 40 MHz (Up to 5Mbps)
1 0 Reserved
1 1 Reserved
This clock multiplier is powered-down (bypassed) on default. After changing the CKUP1 and CKUP0 bits, the
ARCNET core operation is stopped and the internal PLL in the clock generator is awakened and it starts to generate
the 40 MHz. The lock out time of the internal PLL is 8uSec typically. After more than 8 μsec (this wait time is defined
as 1 msec in this data sheet), it is necessary to write command data '18H' to the command register to re-start the
ARCNET core operation. This clock generator is called “clock multiplier”.
Changing the CKUP1 and CKUP0 bits must be one time or less after releasing hardware reset.
DATASHEET
The EF bit in the SETUP2 register must be set when the data rate is over 5 Mbps.
5.3 Network Reconfiguration

A significant advantage of the COM20020I is its ability to adapt to changes on the network. Whenever a new node is
activated or deactivated, a NETWORK RECONFIGURATION is performed. When a new COM20020I is turned on
(creating a new active node on the network), or if the COM20020I has not received an INVITATION TO TRANSMIT
for 420mS, or if a software reset occurs, the COM20020I causes a NETWORK RECONFIGURATION by sending a
RECONFIGURE BURST consisting of eight marks and one space repeated 765 times. The purpose of this burst is to
terminate all activity on the network. Since this burst is longer than any other type of transmission, the burst will
interfere with the next INVITATION TO TRANSMIT, destroy the token and keep any other node from assuming
control of the line.
When any COM20020I senses an idle line for greater than 41μS, which occurs only when the token Is lost, each
COM20020I starts an internal timeout equal to 73μs times the quantity 255 minus its own ID. The COM20020I starts
network reconfiguration by sending an invitation to transmit first to itself and then to all other nodes by decrementing
the destination Node ID. If the timeout expires with no line activity, the COM20020I starts sending INVITATION TO
TRANSMIT with the Destination ID (DID) equal to the currently stored NID. Within a given network, only one
COM20020I will timeout (the one with the highest ID number). After sending the INVITATION TO TRANSMIT, the
COM20020I waits for activity on the line. If there is no activity for 37.4μS, the COM20020I increments the NID value
and transmits another INVITATION TO TRANSMIT using the NID equal to the DID. If activity appears before the
37.4μS timeout expires, the COM20020I releases control of the line. During NETWORK RECONFIGURATION,
INVITATIONS TO TRANSMIT are sent to all NIDs (1-255).
Each COM20020I on the network will finally have saved a NID value equal to the ID of the COM20020I that it
released control to. At this point, control is passed directly from one node to the next with no wasted INVITATIONS
TO TRANSMIT being sent to ID's not on the network, until the next NETWORK RECONFIGURATION occurs. When
a node is powered off, the previous node attempts to pass the token to it by issuing an INVITATION TO TRANSMIT.
Since this node does not respond, the previous node times out and transmits another INVITATION TO TRANSMIT to
an incremented ID and eventually a response will be received.
The NETWORK RECONFIGURATION time depends on the number of nodes in the network, the propagation delay
between nodes, and the highest ID number on the network, but is typically within the range of 12 to 30.5 mS.
5.4 Broadcast Messages

Broadcasting gives a particular node the ability to transmit a data packet to all nodes on the network simultaneously.
ID zero is reserved for this feature and no node on the network can be assigned ID zero. To broadcast a message,
the transmitting node's processor simply loads the RAM buffer with the data packet and sets the DID equal to zero.
Figure 4 illustrates the position of each byte in the packet with the DID residing at address 0X01 or
Hex of the current page selected in the "Enable Transmit from Page fnn" command. Each individual node has the
ability to ignore broadcast messages by setting the most significant bit of the "Enable Receive to Page fnn" command
to a logic "0".
5.5 Extended Timeout Function

There are three timeouts associated with the COM20020I operation. The values of these timeouts are
controlled by bits 3 and 4 of the Configuration Register and bit 5 of the Setup 1 Register.
Response Time
The Response Time determines the maximum propagation delay allowed between any two nodes, and should be
chosen to be larger than the round trip propagation delay between the two furthest nodes on the network plus the
maximum turn around time (the time it takes a particular COM20020I to start sending a message in response to a
received message) which is approximately 6.4 μS. The round trip propagation delay is a function of the transmission
media and network topology. For a typical system using RG62 coax in a baseband system, a one way cable
propagation delay of 15.5 μS translates to a distance of about 2 miles. The flow chart in Figure 1 uses a value of 37.4
S (15.5 + 15.5 + 6.4) to determine if any node will respond.
DATASHEET
Idle Time
The Idle Time is associated with a NETWORK RECONFIGURATION. Figure 1 illustrates that during a NETWORK
RECONFIGURATION one node will continually transmit INVITATIONS TO TRANSMIT until it encounters an active
node. All other nodes on the network must distinguish between this operation and an entirely idle line. During
NETWORK RECONFIGURATION, activity will appear on the line every 41 μS. This 41 μS is equal to the Response
Time of 37.4 μS plus the time it takes the COM20020I to start retransmitting another message (usually another
INVITATION TO TRANSMIT).
Reconfiguration Time
If any node does not receive the token within the Reconfiguration Time, the node will initiate a NETWORK
RECONFIGURATION. The ET2 and ET1 bits of the Configuration Register allow the network to operate over longer
distances than the 2 miles stated earlier. The logic levels on these bits control the maximum distances over which the
COM20020I can operate by controlling the three timeout values described above. For proper network operation, all
COM20020I's connected to the same network must have the same Response Time, Idle Time, and Reconfiguration
Time.
5.6 Line Protocol

The ARCNET line protocol is considered isochronous because each byte is preceded by a start interval and ended with
a stop interval. Unlike asynchronous protocols, there is a constant amount of time separating each data byte. On a 5
Mbps network, each byte takes exactly 11 clock intervals of 200ns each. As a result, one byte is transmitted every 2.2
S and the time to transmit a message can be precisely determined. The line idles in a spacing (logic "0") condition. A
logic "0" is defined as no line activity and a logic "1" is defined as a negative pulse of 100nS duration. A transmission
starts with an ALERT BURST consisting of 6 unit intervals of mark (logic "1"). Eight bit data characters are then sent,
with each character preceded by 2 unit intervals of mark and one unit interval of space. Five types of transmission can
be performed as described below:
Invitations To Transmit
An Invitation To Transmit is used to pass the token from one node to another and is sent by the following sequence:
An ALERT BURST
An EOT (End Of Transmission: ASCII code 04H)
Two (repeated) DID (Destination ID) characters
ALERT EOT DID DID

BURST
Free Buffer Enquiries

A Free Buffer Enquiry is used to ask another node if it is able to accept a packet of data. It is sent by the following
sequence:
An ALERT BURST
An ENQ (ENQuiry: ASCII code 85H)
ALERT ENQ DID DID

BURST
Data Packets
A Data Packet consists of the actual data being sent to another node. It is sent by the following sequence:
An ALERT BURST
An SOH (Start Of Header--ASCII code 01H)
An SID (Source ID) character
A single COUNT character which is the 2's complement of the number of data bytes to follow if a short packet is
sent, or 00H followed by a COUNT character if a long packet is sent.
N data bytes where COUNT = 256-N (or 512-N for a long packet)
DATASHEET
Two CRC (Cyclic Redundancy Check) characters. The CRC polynomial used is: X16 + X15 + X2 + 1.
Acknowledgements
An Acknowledgement is used to acknowledge reception of a packet or as an affirmative response to FREE BUFFER
ENQUIRIES and is sent by the following sequence:
An ALERT BURST
An ACK (ACKnowledgement--ASCII code 86H) character
ALERT BURST ACK
Negative Acknowledgements
A Negative Acknowledgement is used as a negative response to FREE BUFFER ENQUIRIES and is sent by the
following sequence:
An ALERT BURST
A NAK (Negative Acknowledgement--ASCII code 15H) character
ALERT BURST NAK
DATASHEET
6.0 SYSTEM DESCRIPTION

6.1 Microcontroller Interface
The top halves of Figure 2 and Figure 3 illustrate typical COM20020I interfaces to the microcontrollers. The interfaces
consist of a 8-bit data bus, an address bus and a control bus. In order to support a wide range of microcontrollers without
requiring glue logic and without increasing the number of pins, the COM20020I automatically detects and adapts to the
type of microcontroller being used. Upon hardware reset, the COM20020I first determines whether the read and write
control signals are separate READ and WRITE signals (like the 80XX) or DIRECTION and DATA STROBE (like the
68XX). To determine the type of control signals, the device requires the software to execute at least one write access to
external memory before attempting to access the COM20020I. The device defaults to 80XX-like signals. Once the type
of control signals are determined, the COM20020I remains in this interface mode until the next hardware reset occurs.
The second determination the COM20020I makes is whether the bus is multiplexed or non-multiplexed. To determine
the type of bus, the device requires the software to write to an odd memory location followed by a read from an odd
location before attempting to access the COM20020I. The signal on the A0 pin during the odd location access tells the
COM20020I the type of bus. Since multiplexed operation requires A0 to be active low, activity on the A0 line tells the
COM20020I that the bus is non-multiplexed. The device defaults to multiplexed operation. Both determinations may be
made simultaneously by performing a WRITE followed by a READ operation to an odd location within the COM20020I
Address space 20020D registers. Once the type of bus is determined, the COM20020I remains in this interface mode
until hardware reset occurs.
Whenever nCS and nRD are activated, the preset determinations are assumed as final and will not be changed until
hardware reset. Refer to DESCRIPTION OF PIN FUNCTIONS FOR TQFP section for details on the related signals. All
accesses to the internal RAM and the internal registers are controlled by the COM20020I. The internal RAM is accessed
via a pointer-based scheme (refer to the Sequential Access Memory section), and the internal registers are accessed via
direct addressing. Many peripherals are not fast enough to take advantage of high-speed microcontrollers. Since
microcontrollers do not typically have READY inputs, standard peripherals cannot extend cycles to extend the access
time. The access time of the COM20020I, on the other hand, is so fast that it does not need to limit the speed of the
microcontroller. The COM20020I is designed to be flexible so that it is independent of the microcontroller speed.
The COM20020I provides for no wait state arbitration via direct addressing to its internal registers and a pointer based
addressing scheme to access its internal RAM. The pointer may be used in auto-increment mode for typical sequential
buffer emptying or loading, or it can be taken out of auto-increment mode to perform random accesses to the RAM. The
data within the RAM is accessed through the data register. Data being read is prefetched from memory and placed into
the data register for the microcontroller to read. It is important to notice that only by writing a new address pointer
(writing to an address pointer low), one obtains the contents of COM20020I internal RAM. Performing only read from the
Data Register does not load new data from the internal RAM. During a write operation, the data is stored in the data
register and then written into memory. Whenever the pointer is loaded for reads with a new value, data is immediately
prefetched to prepare for the first read operation.
DATASHEET
XTAL1 COM20020I
XTAL2
AD0- AD0-AD2, D3-
ALE A2/BAL RXIN

A15 nCS
LTC1480 or
RESET nRESET nTXEN Equiv.
nPULSE
nRD nRD/nD nPULSE
nWR nWR/DI GND
nINT1 nINTR
Differential
Configuratio
8051
XTAL1 * Media
A0/nMU XTAL2 may be
with Figure A, B or
27 pF 27 pF
20 MHz
XTAL
+5V
RXIN +3.3V 2
Receive
6 HFD3212-
RXIN
3.3V-5V Converter
100 7
TXEN
nPULSE Transmitte
3 HFE4211-
nPULSE nPULSE
+5V
GND 2
6
7
2 Fiber
(ST
BACKPLANE NOTE: COM20020 must be in backplane mode
FIGURE A FIGURE B
FIGURE 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE
DATASHEET
XTAL1
COM2002
XTAL2
D0-D7 D0-D7
A0 A0/nMUX
RXIN
A1 A1
A2 A2/BALE LTC1480 or
TXEN Equiv.
A7 nCS
nPULSE1
nRES nRESET
nPULSE2
nIOS nRD/nDS
GND
R/nW nWR/nDIR
nIRQ1 nINTR Differential Driver
Configuration
6801
* Media Interface
may be replaced
XTAL1 XTAL2 with Figure A, B or C.
27 pF 20MHz 27 pF
XTAL
+5V
HYC9068 or
10 + 0.47
HYC9088 uF
3.3V-5V Converter uF
RXIN RXIN 6
12
nTXEN N/C
11 0.01 uF
5.6K
nPULSE1 nPULSE1 1KV
1/2W
nPULSE2 nPULSE2 5.6K
1/2W
GND 17, 19,
4, 13, 14
3
Traditional Hybrid
0.47
uF -5V Configuration
+ 10
*Valid for 2.5 Mbps only.
uF
FIGURE C
FIGURE 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE
DATASHEET
High Speed CPU Bus Timing Support

High speed CPU bus support was added to the COM20020I. The reasoning behind this is as follows: With the Host
interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be stable before the read signal is
active and remain after the read signal is inactive. But the High Speed CPU bus timing doesn't adhere to these
timings. For example, a RISC type single chip microcontroller (like the HITACHI SuperH series) changes I/O address
at the same time as the read signal. Therefore, several external logic ICs would be required to connect to this
microcontroller.
In addition, the Diagnostic Status (DIAG) register is cleared automatically by reading itself. The internal DIAG register
read signal is generated by decoding the Address (A2-A0), Chip Select (nCS) and Read (nRD) signals. The decoder
will generate a noise spike at the above tight timing. The DIAG register is cleared by the spike signal without reading
itself. This is unexpected operation. Reading the internal RAM and Next Id Register have the same mechanism as
reading the DIAG register.
Therefore, the address decode and host interface mode blocks were modified to fit the above CPU interface to
support high speed CPU bus timing. In Intel CPU mode (nRD, nWR mode), 3 bit I/O address (A2-A0) and Chip
Select (nCS) are sampled internally by Flip-Flops on the falling edge of the internal delayed nRD signal. The internal
real read signal is the more delayed nRD signal. But the rising edge of nRD doesn't delay. By this modification, the
internal real address and Chip Select are stable while the internal real read signal is active. Refer to Figure 4 below.
A2-A0, nCS VALID
nRD
Delayed nRD
(nRD1)
Sampled A2-A0, nCS VALID
More delayed nRD

(nRD2)
FIGURE 4 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE
The I/O address and Chip Select signals, which are supplied to the data output logic, are not sampled. Also, the nRD
signal is not delayed, because the above sampling and delaying paths decrease the data access time of the read
cycle.
The above sampling and delaying signals are supplied to the Read Pulse Generation logic which generates the
clearing pulse for the Diagnostic register and generates the starting pulse of the RAM Arbitration. Typical delay time
between nRD and nRD1 is around 15nS and between nRD1 and nRD2 is around 10nS.
Longer pulse widths are needed due to these delays on nRD signal. However, the CPU can insert some wait cycles
to extend the width without any impact on performance.
The RBUSTMG bit was added to Disable/Enable the High Speed CPU Read function. It is defined as: RBUSTMG=0,
Disabled (Default); RBUSTMG=1, Enabled.
DATASHEET
In the MOTOROLA CPU mode (DIR, nDS mode), the same modifications apply.
RBUSTMG BIT BUS TIMING MODE

0 Normal Speed CPU Read and Write
1 High Speed CPU Read and Normal Speed CPU Write
6.2 Transmission Media Interface

The bottom halves of Figure 2 and Figure 3 illustrate the COM20020I interface to the transmission media used to
connect the node to the network. TABLE 1 - TYPICAL MEDIA lists different types of cable which are suitable for
ARCNET applications. The user may interface to the cable of choice in one of three ways:
Traditional Hybrid Interface

The Traditional Hybrid Interface is that which is used with previous ARCNET devices. The Hybrid Interface is
recommended if the node is to be placed in a network with other Hybrid-Interfaced nodes. The Traditional Hybrid
Interface is for use with nodes operating at 2.5 Mbps only. The transformer coupling of the Hybrid offers isolation for the
safety of the system and offers high Common Mode Rejection. The Traditional Hybrid Interface uses circuits like
SMSC's HYC9068 or HYC9088 to transfer the pulse-encoded data between the cable and the COM20020I. The
COM20020I transmits a logic "1" by generating two 100nS non-overlapping negative pulses, nPULSE1 and nPULSE2.
Lack of pulses indicates a logic "0". The nPULSE1 and nPULSE2 signals are sent to the Hybrid, which creates a 200nS
dipulse signal on the media.
A logic "0" is transmitted by the absence of the dipulse. During reception, the 200nS dipulse appearing on the media is
coupled through the RF transformer of the LAN Driver, which produces a positive pulse at the RXIN pin of the
COM20020I. The pulse on the RXIN pin represents a logic "1". Lack of pulse represents a logic "0". Typically, RXIN
pulses occur at multiples of 400nS. The COM20020I can tolerate distortion of plus or minus 100nS and still correctly
capture and convert the RXIN pulses to NRZ format. Figure 5 illustrates the events which occur in transmission or
reception of data consisting of 1, 1, 0.
Please refer to TN7-5 – Cabling Guidelines for the COM20020I ULANC, available from SMSC, for recommended
cabling distance, termination, and node count for ARCNET nodes.
Backplane Configuration
The Backplane Open Drain Configuration is recommended for cost-sensitive, short-distance applications like backplanes
and instrumentation. This mode is advantageous because it saves components, cost, and power.
Since the Backplane Configuration encodes data differently than the traditional Hybrid Configuration, nodes utilizing the
Backplane Configuration cannot communicate directly with nodes utilizing the Traditional Hybrid Configuration. The
Backplane Configuration does not isolate the node from the media nor protects it from Common Mode noise, but
Common Mode Noise is less of a problem in short distances.
The COM20020I supplies a programmable output driver for Backplane Mode operation. A push/pull or open drain driver
can be selected by programming the P1MODE bit of the Setup 1 Register (see register descriptions for details). The
COM20020I defaults to an open drain output.
The Backplane Configuration provides for direct connection between the COM20020I and the media. Only one pull-up
resistor (in open drain configuration of the output driver) is required somewhere on the media (not on each individual
node). The nPULSE1 signal, in this mode, is an open drain or push/pull driver and is used to directly drive the media. It
issues a 200nS negative pulse to transmit a logic "1". Note that when used in the open-drain mode, the COM20020I
does not have a fail/safe input on the RXIN pin. The nPULSE1 signal actually contains a weak pull-up resistor. This
pull-up should not take the place of the resistor required on the media for open drain mode.
DATASHEET
RT +3.3V RT
+3.3V +3.3V
RBIAS RBIAS
LTC1480 or RBIAS
Equiv.
COM2002 COM2002 COM2002
FIGURE 5 - COM20020I NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS
1 1 0
20MHZ
CLOCK
(FOR REF.
ONLY)
100ns
nPULSE1
100ns
nPULSE2
200ns
DIPULSE
400ns
RXIN
FIGURE 6 - DIPULSE WAVEFORM FOR DATA OF 1-1-0
DATASHEET
In typical applications, the serial backplane is terminated at both ends and a bias is provided by the external pull-up
resistor.
The RXIN signal is directly connected to the cable via an internal Schmitt trigger. A negative pulse on this input
indicates a logic "1". Lack of pulse indicates a logic "0". For typical single-ended backplane applications, RXIN is
connected to nPULSE1 to make the serial backplane data line. A ground line (from the coax or twisted pair) should run
in parallel with the signal. For applications requiring different treatment of the receive signal (like filtering or squelching),
nPULSE1 and RXIN remain as independent pins. External differential drivers/receivers for increased range and common
mode noise rejection, for example, would require the signals to be independent of one another.
When the device is in Backplane Mode, the clock provided by the nPULSE2 signal may be used for encoding the data
into a different encoding scheme or other synchronous operations needed on the serial data stream.
Differential Driver Configuration

The Differential Driver Configuration is a special case of the Backplane Mode. It is a dc coupled configuration
recommended for applications like car-area networks or other cost-sensitive applications which do not require direct
compatibility with existing ARCNET nodes and do not require isolation.
The Differential Driver Configuration cannot communicate directly with nodes utilizing the Traditional Hybrid
Configuration. Like the Backplane Configuration, the Differential Driver Configuration does not isolate the node from the
media.
The Differential Driver interface includes a RS485 Driver/Receiver to transfer the data between the cable and the
COM20020I. The nPULSE1 signal transmits the data, provided the Transmit Enable signal is active. The nPULSE1
signal issues a 200nS (at 2.5Mbps) negative pulse to transmit a logic "1". Lack of pulse indicates a logic "0". The RXIN
signal receives the data, the transmitter portion of the COM20020I is disabled during reset and the nPULSE1, nPULSE2
and nTXEN pins are inactive.
Programmable TXEN Polarity

To accommodate transceivers with active high ENABLE pins, the COM20020I contains a programmable TXEN output.
To program the TXEN pin for an active high pulse, the nPULSE2 pin should be connected to ground. To retain the
normal active low polarity, nPULSE2 should be left open. The polarity determination is made at power on reset and is
valid only for Backplane Mode operation. The nPULSE2 pin should remain grounded at all times if an active high
polarity is desired.
DATASHEET
A0/nMUX
A1
A2/BALE ADDRESS
DECODING 2K x 8
CIRCUITRY
RAM
ADDITIONAL
REGISTERS
AD0-AD2,
D3-D7
STATUS/
nINTR COMMAND nPULSE1
REGISTER nPULSE2
MICRO- TX/RX
nTXEN
SEQUENCER LOGIC RXIN
AND
WORKING
RESET
nRESET REGISTERS
LOGIC
XTAL1
OSCILLATOR XTAL2
nRD/nDS
nWR/DIR BUS
nCS ARBITRATION
CIRCUITRY RECONFIGURATION NODE ID
TIMER LOGIC
FIGURE 7 - INTERNAL BLOCK DIAGRAM
DATASHEET
Table 1 - Typical Media

NOMINAL ATTENUATION PER 1000 FT.
CABLE TYPE IMPEDANCE AT 5 MHz
RG-62 Belden #86262 93Ω 5.5dB
RG-59/U Belden #89108 75Ω 7.0dB
RG-11/U Belden #89108 75Ω 5.5dB
IBM Type 1* Belden #89688 150Ω 7.0dB
IBM Type 3* Telephone Twisted
Pair Belden #1155A 100Ω 17.9dB
COMCODE 26 AWG Twisted
Pair Part #105-064-703 105Ω 16.0dB
*Non-plenum-rated cables of this type are also available.
Note: For more detailed information on Cabling options including RS-485, transformer-coupled RS-485 and Fiber Optic
interfaces, please refer to TN7-5 – Cabling Guidelines for the COM20020I ULANC, available from Standard
Microsystems Corporation.
DATASHEET
7.0 FUNCTIONAL DESCRIPTION

7.1 Microsequencer
The COM20020I contains an internal microsequencer which performs all of the control operations necessary to carry
out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program counter, two instruction
registers, an instruction decoder, a no-op generator, jump logic, and reconfiguration logic.
The COM20020I derives a 10 MHz and a 5 MHz clock from the output clock of the Clock Multiplier. These clocks
provide the rate at which the instructions are executed within the COM20020I. The 10 MHz clock is the rate at which
the program counter operates, while the 5 MHz clock is the rate at which the instructions are executed. The
microprogram is stored in the ROM and the instructions are fetched and then placed into the instruction registers.
One register holds the opcode, while the other holds the immediate data. Once the instruction is fetched, it is
decoded by the internal instruction decoder, at which point the COM20020I proceeds to execute the instruction.
When a no-op instruction is encountered, the microsequencer enters a timed loop and the program counter is
temporarily stopped until the loop is complete. When a jump instruction is encountered, the program counter is
loaded with the jump address from the ROM. The COM20020I contains an internal reconfiguration timer which
interrupts the microsequencer if it has timed out. At this point the program counter is cleared and the MYRECON bit
of the Diagnostic Status Register is set.
Table 2 - Read Register Summary
READ
REGISTER MSB LSB ADDR
STATUS RI/TRI X/RI X/TA POR TEST RECON TMA TA/ 00
TTA
DIAG. MY-RECON DUPID RCV- TOKEN EXC- TENTID NEW X 01
STATUS ACT NAK NEXT
ID
ADDRESS RD-DATA AUTO- X X X A10 A9 A8 02
PTR HIGH INC
ADDRESS A7 A6 A5 A4 A3 A2 A1 A0 03
PTR LOW
DATA D7 D6 D5 D4 D3 D2 D1 D0 04
SUB ADR (R/W)* 0 0 0 (R/W)* SUB- SUB- SUB- 05
AD2 AD1 AD0
CONFIG- RESET CCHE TXEN ET1 ET2 BACK- SUB- SUB- 06
URATION N PLANE AD1 AD0
TENTID TID7 TID6 TID5 TID4 TID3 TID2 TID1 TID0 07-0
NODE ID NID7 NID6 NID5 NID4 NID3 NID2 NID1 NID0 07-1
SETUP1 P1 MODE FOUR X RCV- CKP3 CKP2 CKP1 SLOW- 07-2
NAKS ALL ARB
NEXT ID NXT ID7 NXT NXT NXT NXT NXT NXT NXT 07-3
ID6 ID5 ID4 ID3 ID2 ID1 ID0
SETUP2 RBUS-TMG X CKU CKUP0 EF NO- RCN- RCM- 07-4
P1 SYNC TM1 TM2
Note*: (R/W) This bit can be Written or Read. For more information see Appendix B.
DATASHEET
Table 3 - Write Register Summary
WRITE
ADDR MSB LSB REGISTER
00 RI/TR1 0 0 0 EXCNAK RECO NEW TA/ INTERRUPT
N NEXTID TTA MASK
01 C7 C6 C5 C4 C3 C2 C1 C0 COMMAND
02 RD- AUTO- 0 0 0 A10 A9 A8 ADDRESS
DATA INC PTR HIGH
03 A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS
PTR LOW
04 D7 D6 D5 D4 D3 D2 D1 D0 DATA
05 (R/W)* 0 0 0 (R/W)* SUB- SUB- SUB- SUBADR
AD2 AD1 AD0
06 RESE CCHEN TXEN ET1 ET2 BACK- SUB- SUB- CONFIG-
T PLANE AD1 AD0 URATION
07-0 TID7 TID6 TID5 TID4 TID3 TID2 TID1 TID0 TENTID
07-1 NID7 NID6 NID5 NID4 NID3 NID2 NID1 NID0 NODEID
07-2 P1- FOUR 0 RCV- CKP3 CKP2 CKP1 SLOW- SETUP1
MODE NAKS ALL ARB
07-3 0 0 0 0 0 0 0 0 TEST
07-4 RBUS- 0 CKUP CKUP0 EF NO- RCN- RCN- SETUP2
TMG 1 SYNC TM1 TM0
Note*:(R/W) This bit can be Written or Read. For more information see Appendix B.
7.2 INTERNAL REGISTERS

The COM20020I contains 14 internal registers. TABLE 2 and TABLE 3 illustrate the COM20020I register map. All
undefined bits are read as undefined and must be written as logic "0".
Interrupt Mask Register (IMR)

The COM20020I is capable of generating an interrupt signal when certain status bits become true. A write to the IMR
specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR are in the same position
as their corresponding status bits in the Status Register and Diagnostic Status Register. A logic "1" in a particular
position enables the corresponding interrupt. The Status bits capable of generating an interrupt include the Receiver
Inhibited bit, New Next ID bit, Excessive NAK bit, Reconfiguration Timer bit, and Transmitter Available bit. No other
Status or Diagnostic Status bits can generate an interrupt.
The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to produce the
interrupt signal. An RI or TA interrupt is masked when the corresponding mask bit is reset to logic "0", but will reappear
when the corresponding mask bit is set to logic "1" again, unless the interrupt status condition has been cleared by this
time. A RECON interrupt is cleared when the "Clear Flags" command is issued. An EXCNAK interrupt is cleared when
the "POR Clear Flags" command is issued. A New Next ID interrupt is cleared by reading the Next ID Register. The
Interrupt Mask Register defaults to the value 0000 0000 upon hardware reset.
Data Register
This read/write 8-bit register is used as the channel through which the data to and from the RAM passes. The data is
placed in or retrieved from the address location presently specified by the address pointer. The contents of the Data
Register are undefined upon hardware reset. In case of READ operation, the Data Register is loaded with the contents
of COM20020I Internal Memory upon writing Address Pointer low only once.
Tentative ID Register
The Tentative ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly
(please refer to the Configuration Register and SUB ADR Register). The Tentative ID Register can be used while the
DATASHEET
node is on-line to build a network map of those nodes existing on the network. It minimizes the need for operator
interaction with the network. The node determines the existence of other nodes by placing a Node ID value in the
Tentative ID Register and waiting to see if the Tentative ID bit of the Diagnostic Status Register gets set. The network
map developed by this method is only valid for a short period of time, since nodes may join or depart from the network at
any time. When using the Tentative ID feature, a node cannot detect the existence of the next logical node to which it
passes the token. The Next ID Register will hold the ID value of that node. The Tentative ID Register defaults to the
value 0000 0000 upon hardware reset only.
Node ID Register
The Node ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly (please
refer to the Configuration Register and SUB ADR Register). The Node ID Register contains the unique value which
identifies this particular node. Each node on the network must have a unique Node ID value at all times. The Duplicate
ID bit of the Diagnostic Status Register helps the user find a unique Node ID. Refer to the Initialization Sequence section
for further detail on the use of the DUPID bit. The core of the COM20020I does not wake up until a Node ID other than
zero is written into the Node ID Register. During this time, no microcode is executed, no tokens are passed by this node,
and no reconfigurations are caused by this node. Once a non-zero NodeID is placed into the Node ID Register, the core
wakes up but will not join the network until the TXEN bit of the Configuration Register is set. While the Transmitter is
disabled, the Receiver portion of the device is still functional and will provide the user with useful information about the
network. The Node ID Register defaults to the value 0000 0000 upon hardware reset only.
Next ID Register
The Next ID Register is an 8-bit, read-only register, accessed when the sub-address bits are set up accordingly (please
refer to the Configuration Register and SUB ADR Register). The Next ID Register holds the value of the Node ID to
which the COM20020I will pass the token. When used in conjunction with the Tentative ID Register, the Next ID
Register can provide a complete network map. The Next ID Register is updated each time a node enters/leaves the
network or when a network reconfiguration occurs. Each time the microsequencer updates the Next ID Register, a New
Next ID interrupt is generated. This bit is cleared by reading the Next ID Register. Default value is 0000 0000 upon
hardware or software reset.
Status Register
The COM20020I Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6, are software
compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the Extended Timeout status
was provided in bits 5 and 6 of the Status Register. In the COM20020I, the COM20020I, the COM90C66, and the
COM90C165, COM20020I-5, COM20051 and COM20051+ these bits exist in and are controlled by the Configuration
Register. The Status Register contents are defined as in TABLE 4, but are defined differently during the Command
Chaining operation. Please refer to the Command Chaining section for the definition of the Status Register during
Command Chaining operation. The Status Register defaults to the value 1XX1 0001 upon either hardware or software
reset.
Diagnostic Status Register

The Diagnostic Status Register contains seven read-only bits which help the user troubleshoot the network or node
operation. Various combinations of these bits and the TXEN bit of the Configuration Register represent different
situations. All of these bits, except the Excessive NAcK bit and the New Next ID bit, are reset to logic "0" upon reading
the Diagnostic Status Register or upon software or hardware reset. The EXCNAK bit is reset by the "POR Clear Flags"
command or upon software or hardware reset. The Diagnostic Status Register defaults to the value 0000 000X upon
either hardware or software reset.
Command Register
Execution of commands are initiated by performing microcontroller writes to this register. Any combinations of written
data other than those listed in TABLE 5 are not permitted and may result in incorrect chip and/or network operation.
Address Pointer Registers

These read/write registers are each 8-bits wide and are used for addressing the internal RAM. New pointer addresses
should be written by first writing to the High Register and then writing to the Low Register because writing to the Low
Register loads the address. The contents of the Address Pointer High and Low Registers are undefined upon hardware
reset. Writing to Address Pointer low loads the address.
Configuration Register
The Configuration Register is a read/write register which is used to configure the different modes of the COM20020I.
The Configuration Register defaults to the value 0001 1000 upon hardware reset only. SUBAD0 and SUBAD1 point to
the selection in Register 7.
DATASHEET
Sub-Address Register
The sub-address register is new to the COM20020I, previously a reserved register. Bits 2, 1 and 0 are used to select
one of the registers assigned to address 7h. SUBAD1 and SUBAD0 already exist in the Configuration register on the
COM20020IB. They are exactly same as those in the Sub-Address register. If the SUBAD1 and SUBAD0 bits in the
Configuration register are changed, the SUBAD1and SUBAD0 in the Sub-Address register are also changed.
SUBAD2 is a new sub-address bit. It Is used to access the 1 new Set Up register, SETUP2. This register is selected
by setting SUBAD2=1. The SUBAD2 bit is cleared automatically by writing the Configuration register.
Setup 1 Register
The Setup 1 Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly (see the
bit definitions of the Configuration Register). The Setup 1 Register allows the user to change the network speed (data
rate) or the arbitration speed independently, invoke the Receive All feature and change the nPULSE1 driver type. The
data rate may be slowed to 156.25Kbps and/or the arbitration speed may be slowed by a factor of two. The Setup 1
Register defaults to the value 0000 0000 upon hardware reset only.
Setup 2 Register
The Setup 2 Register is new to the COM20020I. It is an 8-bit read/write register accessed when the Sub Address Bits
SUBAD[2:0] are set up accordingly (see the bit definitions of the Sub Address Register). This register contains bits for
various functions. The CKUP1,0 bits select the clock to be generated from the 20 MHz crystal. The RBUSTMG bit is
used to Disable/Enable Fast Read function for High Speed CPU bus support. The EF bit is used to enable the new
timing for certain functions in the COM20020I (if EF = 0, the timing is the same as in the COM20020I Rev. B). See
Appendix “A”. The NOSYNC bit is used to enable the NOSYNC function during initialization. If this bit is reset, the
line has to be idle for the RAM initialization sequence to be written. If set, the line does not have to be idle for the
initialization sequence to be written. See Appendix “A”.
The RCNTM[1,0] bits are used to set the time-out period of the recon timer. Programming this timer for shorter time
periods has the benefit of shortened network reconfiguration periods. The time periods shown in the table on the
following page are limited by a maximum number of nodes in the network. These time-out period values are for
5Mbps. For other data rates, scale the time-out period time values accordingly; the maximum node count remains the
same.
TIME-OUT MAX NODE

RCNTM1 RCNTM0 PERIOD COUNT
0 0 420 mS Up to 255 nodes
1 0 52.5 mS Up to 32 nodes
1 1 26.25 mS* Up to 16 nodes*
Note*: The node ID value 255 must exist in the network for the 26.25 mS time-out to be valid.
DATASHEET
Table 4 - Status Register

BIT BIT NAME SYMBOL DESCRIPTION
7 Receiver RI This bit, if high, indicates that the receiver is not enabled because
Inhibited either an "Enable Receive to Page fnn" command was never
issued, or a packet has been deposited into the RAM buffer page
fnn as specified by the last "Enable Receive to Page fnn"
command. No messages will be received until this command is
issued, and once the message has been received, the RI bit is set,
thereby inhibiting the receiver. The RI bit is cleared by issuing an
"Enable Receive to Page fnn" command. This bit, when set, will
cause an interrupt if the corresponding bit of the Interrupt Mask
Register (IMR) is also set. When this bit is set and another station
attempts to send a packet to this station, this station will send a
NAK.
6,5 (Reserved) These bits are undefined.
4 Power On Reset POR This bit, if high, indicates that the COM20020I has been reset by
either a software reset, a hardware reset, or writing 00H to the
Node ID Register. The POR bit is cleared by the "Clear Flags"
command.
3 Test TEST This bit is intended for test and diagnostic purposes. It is a logic
"0" under normal operating conditions.
2 Reconfiguration RECON This bit, if high, indicates that the Line Idle Timer has timed out
because the RXIN pin was idle for 41μS. The RECON bit is
cleared during a "Clear Flags" command. This bit, when set, will
cause an interrupt if the corresponding bit in the IMR is also set.
The interrupt service routine should consist of examining the
MYRECON bit of the Diagnostic Status Register to determine
whether there are consecutive reconfigurations caused by this
node.
1 Transmitter TMA This bit, if high, indicates that the packet transmitted as a result of
Message an "Enable Transmit from Page fnn" command has been
Acknowledged acknowledged. This bit should only be considered valid after the
TA bit (bit 0) is set. Broadcast messages are never acknowledged.
The TMA bit is cleared by issuing the "Enable Transmit from Page
fnn" command.
0 Transmitter TA This bit, if high, indicates that the transmitter is available for
Available transmitting. This bit is set when the last byte of scheduled packet
has been transmitted out, or upon execution of a "Disable
Transmitter" command. The TA bit is cleared by issuing the
"Enable Transmit from Page fnn" command after the node next
receives the token. This bit, when set, will cause an interrupt if the
corresponding bit in the IMR is also set.
DATASHEET
Table 5 - Diagnostic Status Register

7 My MY- This bit, if high, indicates that a past reconfiguration was caused by
Reconfiguration RECON this node. It is set when the Lost Token Timer times out, and
should be typically read following an interrupt caused by RECON.
Refer to the Improved Diagnostics section for further detail.
6 Duplicate ID DUPID This bit, if high, indicates that the value in the Node ID Register
matches both Destination ID characters of the token and a
response to this token has occurred. Trailing zero's are also
verified. A logic "1" on this bit indicates a duplicate Node ID, thus
the user should write a new value into the Node ID Register. This
bit is only useful for duplicate ID detection when the device is off
line, that is, when the transmitter is disabled. When the device is
on line this bit will be set every time the device gets the token. This
bit is reset automatically upon reading the Diagnostic Status
Register. Refer to the Improved Diagnostics section for further
detail.
5 Receive RCVACT This bit, if high, indicates that data activity (logic "1") was detected
Activity on the RXIN pin of the device. Refer to the Improved Diagnostics
section for further detail.
4 Token Seen TOKEN This bit, if high, indicates that a token has been seen on the
network, sent by a node other than this one. Refer to the Improved
Diagnostic section for further detail.
3 Excessive NAK EXCNAK This bit, if high, indicates that either 128 or 4 Negative
Acknowledgements have occurred in response to the Free Buffer
Enquiry. This bit is cleared upon the "POR Clear Flags" command.
Reading the Diagnostic Status Register does not clear this bit.
This bit, when set, will cause an interrupt if the corresponding bit in
the IMR is also set. Refer to the Improved Diagnostics section for
further detail.
2 Tentative ID TENTID This bit, if high, indicates that a response to a token whose DID
matches the value in the Tentative ID Register has occurred. The
second DID and the trailing zero's are not checked. Since each
node sees every token passed around the network, this feature
can be used with the device on-line in order to build and update a
network map. Refer to the Improved Diagnostics section for further
detail.
1 New Next ID NEW This bit, if high, indicates that the Next ID Register has been
NXTID updated and that a node has either joined or left the network.
Reading the Diagnostic Status Register does not clear this bit. This
bit, when set, will cause an interrupt if the corresponding bit in the
IMR is also set. The bit is cleared by reading the Next ID Register.
1,0 (Reserved) These bits are undefined.
DATASHEET
Table 6 - Command Register

DATA COMMAND DESCRIPTION
0000 0000 Clear This command is used only in the Command Chaining operation.
Transmit Please refer to the Command Chaining section for definition of
Interrupt this command.
0000 0001 Disable This command will cancel any pending transmit command
Transmitter (transmission that has not yet started) and will set the TA
(Transmitter Available) status bit to logic "1" when the
COM20020I next receives the token.
0000 0010 Disable This command will cancel any pending receive command. If the
Receiver COM20020I is not yet receiving a packet, the RI (Receiver
Inhibited) bit will be set to logic "1" the next time the token is
received. If packet reception is already underway, reception will
run to its normal conclusion.
b0fn n100 Enable This command allows the COM20020I to receive data packets
Receive to into RAM buffer page fnn and resets the RI status bit to logic "0".
Page fnn The values placed in the "nn" bits indicate the page that the data
will be received into (page 0, 1, 2, or 3). If the value of "f" is a
logic "1", an offset of 256 bytes will be added to that page
specified in "nn", allowing a finer resolution of the buffer. Refer to
the Selecting RAM Page Size section for further detail. If the
value of "b" is logic "1", the device will also receive broadcasts
(transmissions to ID zero). The RI status bit is set to logic "1"
upon successful reception of a message.
00fn n011 Enable This command prepares the COM20020I to begin a transmit
Transmit from sequence from RAM buffer page fnn the next time it receives the
Page fnn token. The values of the "nn" bits indicate which page to transmit
from (0, 1, 2, or 3). If "f" is logic "1", an offset of 256 bytes is the
start of the page specified in "nn", allowing a finer resolution of the
buffer. Refer to the Selecting RAM Page Size section for further
detail. When this command is loaded, the TA and TMA bits are
reset to logic "0". The TA bit is set to logic "1" upon completion of
the transmit sequence. The TMA bit will have been set by this
time if the device has received an ACK from the destination node.
The ACK is strictly hardware level, sent by the receiving node
before its microcontroller is even aware of message reception.
Refer to Figure 1 for details of the transmit sequence and its
relation to the TA and TMA status bits.
0000 c101 Define This command defines the maximum length of packets that may
Configuration be handled by the device. If "c" is a logic "1", the device handles
both long and short packets. If "c" is a logic "0", the device
handles only short packets.
000r p110 Clear Flags This command resets certain status bits of the COM20020I. A
logic "1" on "p" resets the POR status bit and the EXCNAK
Diagnostic status bit. A logic "1" on "r" resets the RECON status
bit.
0000 1000 Clear This command is used only in the Command Chaining operation.
Receive Please refer to the Command Chaining section for definition of
Interrupt this command.
0001 1000 Start Internal This command restarts the stopped internal operation after
Operation changing CKUP1 or CKUP0 bit.
DATASHEET
Table 7 - Address Pointer High Register

7 Read Data RDDATA This bit tells the COM20020I whether the following access
will be a read or write. A logic "1" prepares the device for a
read, a logic "0" prepares it for a write.
6 Auto Increment AUTOINC This bit controls whether the address pointer will increment
automatically. A logic "1" on this bit allows automatic
increment of the pointer after each access, while a logic "0"
disables this function. Please refer to the Sequential
Access Memory section for further detail.
5-3 (Reserved) These bits are undefined.
2-0 Address 10-8 A10-A8 These bits hold the upper three address bits which provide
addresses to RAM.
Table 8 - Address Pointer Low Register

7-0 Address 7-0 A7-A0 These bits hold the lower 8 address bits which provide the
addresses to RAM.
Table 9 - Sub Address Register

7-3 Reserved These bits are undefined.
2,1,0 Sub Address 2,1,0 SUBAD These bits determine which register at address 07 may be
2,1,0 accessed. The combinations are as follows:
SUBAD2 SUBAD1 SUBAD0 Register

0 0 0 Tentative ID \ (Same
0 0 1 Node ID \ as in
0 1 0 Setup 1 / Config
0 1 1 Next ID / Register)
1 0 0 Setup 2
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Register. SUBAD2 is cleared automatically by
writing the Configuration Register.
Table 10 - Configuration Register

7 Reset RESET A software reset of the COM20020I is executed by writing a
logic "1" to this bit. A software reset does not reset the
microcontroller interface mode, nor does it affect the
Configuration Register. The only registers that the software
reset affect are the Status Register, the Next ID Register, and
the Diagnostic Status Register. This bit must be brought
back to logic "0" to release the reset.
DATASHEET

6 Command CCHEN This bit, if high, enables the Command Chaining operation of
Chaining Enable the device. Please refer to the Command Chaining section
for further details. A low level on this bit ensures software
compatibility with previous SMSC ARCNET devices.
5 Transmit Enable TXEN When low, this bit disables transmissions by keeping
nPULSE1, nPULSE2 if in non-Backplane Mode, and nTXEN
pin inactive. When high, it enables the above signals to be
activated during transmissions. This bit defaults low upon
reset. This bit is typically enabled once the Node ID is
determined, and never disabled during normal operation.
Please refer to the Improved Diagnostics section for details
on evaluating network activity.
4,3 Extended ET1, ET2 These bits allow the network to operate over longer distances
Timeout 1,2 than the default maximum 2 miles by controlling the
Response, Idle, and Reconfiguration Times. All nodes should
be configured with the same timeout values for proper
network operation. For the COM20020I with a 20 MHz
crystal oscillator, the bit combinations follow:
Reconfig
Response Idle Time Time
ET2 ET1 Time (μS) (μS) (mS)
0 0 596.6 656 840
0 1 298.4 328 840
1 0 149.2 164 840
1 1 37.4 41 420
Note: These values are for 5Mbps and RCNTMR[1,0]=00.
Reconfiguration time is changed by the RCNTMR1 and
RCNTMR0 bits.
2 Backplane BACK- A logic "1" on this bit puts the device into Backplane Mode
PLANE signaling which is used for Open Drain and Differential Driver
interfaces.
1,0 Sub Address 1,0 SUBAD These bits determine which register at address 07 may be
1,0 accessed. The combinations are as follows:
SUBAD1 SUBAD0 Register

0 0 Tentative ID
0 1 Node ID
1 0 Setup 1
1 1 Next ID
See also the Sub Address Register.
DATASHEET
Table 11 - Setup 1 Register

7 Pulse1 Mode P1MODE This bit determines the type of PULSE1 output driver used
in Backplane Mode. When high, a push/pull output is used.
When low, an open drain output is used. The default is
open drain.
6 Four NACKS FOUR This bit, when set, will cause the EXNACK bit in the
NACKS Diagnostic Status Register to set after four NACKs to Free
Buffer Enquiry are detected by the COM20020I. This bit,
when reset, will set the EXNACK bit after 128 NACKs to
Free Buffer Enquiry. The default is 128.
5 Reserved Do not set.
4 Receive All RCVALL This bit, when set, allows the COM20020I to receive all
valid data packets on the network, regardless of their
destination ID. This mode can be used to implement a
network monitor with the transmitter on- or off-line. Note
that ACKs are only sent for packets received with a
destination ID equal to the COM20020I's programmed node
ID. This feature can be used to put the COM20020I in a
'listen-only' mode, where the transmitter is disabled and the
COM20020I is not passing tokens. Defaults low.
3,2,1 Clock Prescaler Bits CKP3,2,1 These bits are used to determine the data rate of the
3,2,1 COM20020I. The following table is for a 20 MHz crystal:
(Clock Multiplier is bypassed)
CKP3 CKP2 CKP1 DIVISOR SPEED
0 0 0 8 2.5Mbs
0 0 1 16 1.25Mbs
0 1 0 32 625Kbs
0 1 1 64 312.5Kbs
1 0 0 128 156.25Kbs
NOTE: The lowest data rate achievable by the COM20020I
is 156.25Kbs. Defaults to 000 or 2.5Mbs. For Clock
Multiplier output clock speed greater than 20 MHz, CKP3,
CKP2 and CKP1 must all be zero.
0 Slow Arbitration SLOWARB This bit, when set, will divide the arbitration clock by 2.
Select Memory cycle times will increase when slow arbitration is
selected.
NOTE: For clock multiplier output clock speeds greater
than 40 MHz, SLOWARB must be set. Defaults to low.
DATASHEET
Table 12 - Setup 2 Register

7 Read Bus Timing RBUSTMG This bit is used to Disable/Enable the High Speed CPU
Select Read function for High Speed CPU bus support.
RBUSTMG=0: Disable (Default), RBUSTMG=1: Enable. It
does not influence write operation. High speed CPU Read
operation is only for non-multiplexed bus.
6 Reserved This bit is undefined.
5,4 Clock Multiplier CKUP1, 0 Higher frequency clocks are generated from the 20 MHz
crystal through the selection of these two bits as shown.
This clock multiplier is powered-down on default. After
changing the CKUP1 and CKUP0 bits, the ARCNET core
operation is stopped and the internal PLL in the clock
multiplier is awakened and it starts to generate the 40 MHz.
The lock out time of the internal PLL is 8μSec typically.
After 1 mS it is necessary to write command data '18H' to
command register for re-starting the ARCNET core
operation. EF bit must be ‘1’ if the data rate is over 5Mbps.
CAUTION: Changing the CKUP1 and CKUP0 bits must be
one time or less after releasing a hardware reset.
CKUP1 CKUP0 Clock Frequency (Data Rate)
0 0 20 MHz (Up to 2.5Mbps) Default
0 1 40 MHz (Up to 5Mbps)
1 0 Reserved
1 1 Reserved
Note: After changing the CKUP1 or CKUP0 bits, it is
necessary to write a command data '18H' to the command
register. Because after changing the CKUP [1, 0] bits, the
internal operation is stopped temporarily. The writing of the
command is to start the operation.
These initializing steps are shown below.
1) Hardware reset (Power ON)
2) Change CKUP[1, 0] bit
3) Wait 1mSec (wait until stable oscillation)
4) Write command '18H' (start internal operation)
5) Start initializing routine (Execute existing software)
3 Enhanced EF This bit is used to enable the new enhanced functions in the
Functions COM20020I. EF = 0: Disable (Default), EF = 1: Enable. If
EF = 0, the timing and function is the same as in the
COM20020I, Revision B. See appendix “A”. EF bit must
be ‘1’ if the data rate is over 5Mbps.
EF bit should be ‘1’ for new design customers.
EF bit should be ‘0’ for replacement customers.
2 No Synchronous NOSYNC This bit is used to enable the SYNC command during
initialization. NOSYNC= 0, Enable (Default) The line must
be idle for the RAM initialization sequence to be written.
NOSYNC= 1, Disable:) The line does not have to be idle for
the RAM initialization sequence to be written. See appendix
“A”.
DATASHEET

1,0 Reconfiguration RCNTM1,0 These bits are used to program the reconfiguration timer as a
Timer 1, 0 function of maximum node count. These bits set the time out
period of the reconfiguration timer as shown below. The
time out periods shown are for 5 Mbps.
RCNTM1 RCNTM0 Time Out Max Node Count
Period
1 0 52.5 mS Up to 32 nodes
1 1 26.25 mS* Up to 16 nodes
Note*: The node ID value 255 must exist in the network for
26.25 mS timeout to be valid.
Data Register
I/O Address 04H Memory
Data Bus
2K x 8
D0-D7 8
INTERNAL
RAM
Address Pointer Register
I/O Address 02H I/O Address 03H
High Low
Memory
Address Bus
11-Bit Counter
11
FIGURE 8 – SEQUENTIAL ACCESS OPERATION
7.3 Internal Ram

The integration of the 2K x 8 RAM in the COM20020I represents significant real estate savings. The most obvious
benefit is the 48 pin package in which the device is now placed (a direct result of the integration of RAM). In addition,
the PC board is now free of the cumbersome external RAM, external latch, and multiplexed address/data bus and
control functions which were necessary to interface to the RAM. The integration of RAM represents significant cost
savings because it isolates the system designer from the changing costs of external RAM and it minimizes reliability
problems, assembly time and costs, and layout complexity.
DATASHEET
Sequential Access Memory

The internal RAM is accessed via a pointer-based scheme. Rather than interfering with system memory, the internal
RAM is indirectly accessed through the Address High and Low Pointer Registers. The data is channeled to and from the
microcontroller via the 8-bit data register. For example: a packet in the internal RAM buffer is read by the microcontroller
by writing the corresponding address into the Address Pointer High and Low Registers (offsets 02H and 03H). Note that
the High Register should be written first, followed by the Low Register, because writing to the Low Register loads the
address. At this point the device accesses that location and places the corresponding data into the data register. The
microcontroller then reads the data register (offset 04H) to obtain the data at the specified location. If the Auto
Increment bit is set to logic "1", the device will automatically increment the address and place the next byte of data into
the data register, again to be read by the microcontroller. This process is continued until the entire packet is read out of
RAM. Refer to Figure 8 for an illustration of the Sequential Access operation. When switching between reads and
writes, the pointer must first be written with the starting address. At least one cycle time should separate the pointer
being loaded and the first read (see timing parameters).
Access Speed
The COM20020I is able to accommodate very fast access cycles to its registers and buffers. Arbitration to the buffer
does not slow down the cycle because the pointer based access method allows data to be prefetched from memory and
stored in a temporary register. Likewise, data to be written is stored in the temporary register and then written to
memory.
For systems which do not require quick access time, the arbitration clock may be slowed down by setting bit 0 of the
Setup1 Register equal to logic "1". Since the Slow Arbitration feature divides the input clock by two, the duty cycle of the
input clock may be relaxed.
SOFTWARE INTERFACE
The microcontroller interfaces to the COM20020I via software by accessing the various registers. These actions are
described in the Internal Registers section. The software flow for accessing the data buffer is based on the Sequential
Access scheme. The basic sequence is as follows:
Disable Interrupts
Write to Pointer Register High (specifying Auto-Increment mode)
Write to Pointer Register Low (this loads the address)
Enable Interrupts
Read or Write the Data Register (repeat as many times as necessary to empty or fill the buffer)
The pointer may now be read to determine how many transfers were completed.
The software flow for controlling the Configuration, Node ID, Tentative ID, and Next ID registers is generally limited to
the initialization sequence and the maintenance of the network map.
Additionally, it is necessary to understand the details of how the other Internal Registers are used in the transmit and
receive sequences and to know how the internal RAM buffer is properly set up. The sequence of events that tie these
actions together is discussed as follows.
Selecting RAM Page Size

During normal operation, the 2K x 8 of RAM is divided into four pages of 512 bytes each. The page to be used is
specified in the "Enable Transmit (Receive) from (to) Page fnn" command, where "nn" specifies page 0, 1, 2, or 3.
This allows the user to have constant control over the allocation of RAM.
When the Offset bit "f" (bit 5 of the "Enable Transmit (Receive) from (to) Page fnn" command word) is set to logic "1", an
offset of 256 bytes is added to the page specified. For example: to transmit from the second half of page 0, the
command "Enable Transmit from Page fnn" (fnn=100 in this case) is issued by writing 0010 0011 to the Command
Register. This allows a finer resolution of the buffer pages without affecting software compatibility. This scheme is useful
for applications which frequently use packet sizes of 256 bytes or less, especially for microcontroller systems with limited
memory capacity. The remaining portions of the buffer pages which are not allocated for current transmit or receive
packets may be used as temporary storage for previous network data, packets to be sent later, or as extra memory for
the system, which may be indirectly accessed.
DATASHEET
If the device is configured to handle both long and short packets (see "Define Configuration" command), then receive
pages should always be 512 bytes long because the user never knows what the length of the receive packet will be. In
this case, the transmit pages may be made 256 bytes long, leaving at least 512 bytes free at any given time. Even if the
Command Chaining operation is being used, 512 bytes is still guaranteed to be free because Command Chaining only
requires two pages for transmit and two for receive (in this case, two 256 byte pages for transmit and two 512 byte
pages for receive, leaving 512 bytes free). Please note that it is the responsibility of software to reserve 512 bytes for
each receive page if the device is configured to handle long packets. The COM20020I does not check page boundaries
during reception. If the device is configured to handle only short packets, then both transmit and receive pages may be
allocated as 256 bytes long, freeing at least 1KByte at any given time.
Even if the Command Chaining operation is being used, 1KByte is still guaranteed to be free because Command
Chaining only requires two pages for transmit and two for receive (in this case, a total of four 256 byte pages, leaving 1K
free).
The general rule which may be applied to determine where in RAM a page begins is as follows:
Address = (nn x 512) + (f x 256).
Transmit Sequence
During a transmit sequence, the microcontroller selects a 256 or 512 byte segment of the RAM buffer and writes into it.
The appropriate buffer size is specified in the "Define Configuration" command. When long packets are enabled, the
COM20020I interprets the packet as either a long or short packet, depending on whether the buffer address 2 contains a
zero or non-zero value. The format of the buffer is shown in Figure 9. Address 0 contains the Source Identifier (SID);
Address 1 contains the Destination Identifier (DID); Address 2 (COUNT) contains, for short packets, the value 256-N,
where N represents the number of information bytes in the message, or for long packets, the value 0, indicating that it is
indeed a long packet. In the latter case, Address 3 (COUNT) would contain the value 512-N, where N represents the
number of information bytes in the message.
DATASHEET
SHORT PACKET LONG PACKET

FORMAT FORMAT
ADDRESS ADDRESS
0 SID 0 SID
1 DID 1 DID
2 COUNT = 256-N 2 0
3 COUNT = 512-N
NOT USED
COUNT DATA BYTE 1 NOT USED

DATA BYTE 2
COUNT DATA BYTE 1
DATA BYTE 2
DATA BYTE N-1
255 DATA BYTE N
DATA BYTE N-1
NOT USED
511 511 DATA BYTE N
N = DATA PACKET LENGTH

SID = SOURCE ID
DID = DESTINATION ID
(DID = 0 FOR BROADCASTS)
FIGURE 9 – RAM BUFFER PACKET CONFIGURATION
The SID in Address 0 is used by the receiving node to reply to the transmitting node. The COM20020I puts the local
ID in this location, therefore it is not necessary to write into this location. Please note that a short packet may contain
between 1 and 253 data bytes, while a long packet may contain between 257 and 508 data bytes. A minimum value
of 257 exists on a long packet so that the COUNT is expressible in eight bits. This leaves three exception packet
lengths which do not fit into either a short or long packet; packet lengths of 254, 255, or 256 bytes. If packets of
these lengths must be sent, the user must add dummy bytes to the packet in order to make the
packet fit into a long packet.
Once the packet is written into the buffer, the microcontroller awaits a logic "1" on the TA bit, indicating that a previous
transmit command has concluded and another may be issued. Each time the message is loaded and a transmit
command issued, it will take a variable amount of time before the message is transmitted, depending on the traffic on
the network and the location of the token at the time the transmit command was issued. The conclusion of the Transmit
Command will generate an interrupt if the Interrupt Mask allows it. If the device is configured for the Command Chaining
operation, please see the Command Chaining section for further detail on the transmit sequence. Once the TA bit
becomes a logic "1", the microcontroller may issue the "Enable Transmit from Page fnn" command, which resets the TA
and TMA bits to logic "0". If the message is not a BROADCAST, the COM20020I automatically sends a FREE BUFFER
ENQUIRY to the destination node in order to send the message. At this point, one of four possibilities may occur.
DATASHEET
The first possibility is if a free buffer is available at the destination node, in which case it responds with an
ACKnowledgement. At this point, the COM20020I fetches the data from the Transmit Buffer and performs the transmit
sequence. If a successful transmit sequence is completed, the TMA bit and the TA bit are set to logic "1". If the packet
was not transmitted successfully, TMA will not be set. A successful transmission occurs when the receiving node
responds to the packet with an ACK. An unsuccessful transmission occurs when the receiving node does not respond
to the packet.
The second possibility is if the destination node responds to the Free Buffer Enquiry with a Negative AcKnowledgement.
A NAK occurs when the RI bit of the destination node is a logic "1". In this case, the token is passed on from the
transmitting node to the next node. The next time the transmitter receives the token, it will again transmit a FREE
BUFFER ENQUIRY. If a NAK is again received, the token is again passed onto the next node. The Excessive NAK bit
of the Diagnostic Status Register is used to prevent an endless sending of FBE's and NAK's. If no limit of FBE-NAK
sequences existed, the transmitting node would continue issuing a Free Buffer Enquiry, even though it would
continuously receive a NAK as a response. The EXCNAK bit generates an interrupt (if enabled) in order to tell the
microcontroller to disable the transmitter via the "Disable Transmitter" command. This causes the transmission to be
abandoned and the TA bit to be set to a logic "1" when the node next receives the token, while the TMA bit remains at a
logic "0". Please refer to the Improved Diagnostics section for further detail on the EXCNAK bit.
The third possibility which may occur after a FREE BUFFER ENQUIRY is issued is if the destination node does not
respond at all. In this case, the TA bit is set to a logic "1", while the TMA bit remains at a logic "0". The user should
determine whether the node should try to reissue the transmit command.
The fourth possibility is if a non-traditional response is received (some pattern other than ACK or NAK, such as noise).
In this case, the token is not passed onto the next node, which causes the Lost Token Timer of the next node to time
out, thus generating a network reconfiguration.
The "Disable Transmitter" command may be used to cancel any pending transmit command when the COM20020I next
receives the token. Normally, in an active network, this command will set the TA status bit to a logic "1" when the token
is received. If the "Disable Transmitter" command does not cause the TA bit to be set in the time it takes the token to
make a round trip through the network, one of three situations exists. Either the node is disconnected from the network,
or there are no other nodes on the network, or the external receive circuitry has failed. These situations can be
determined by either using the improved diagnostic features of the COM20020I or using another software timeout which
is greater than the worst case time for a round trip token pass, which occurs when all nodes transmit a maximum length
message.
Receive Sequence
A receive sequence begins with the RI status bit becoming a logic "1", which indicates that a previous reception has
concluded. The microcontroller will be interrupted if the corresponding bit in the Interrupt Mask Register is set to logic
"1". Otherwise, the microcontroller must periodically check the Status Register. Once the microcontroller is alerted to the
fact that the previous reception has concluded, it may issue the "Enable Receive to Page fnn" command, which resets
the RI bit to logic "0" and selects a new page in the RAM buffer. Again, the appropriate buffer size is specified in the
"Define Configuration" command. Typically, the page which just received the data packet will be read by the
microcontroller at this point. Once the "Enable Receive to Page fnn" command is issued, the microcontroller attends to
other duties. There is no way of knowing how long the new reception will take, since another node may transmit a
packet at any time. When another node does transmit a packet to this node, and if the "Define Configuration" command
has enabled the reception of long packets, the COM20020I interprets the packet as either a long or short packet,
depending on whether the content of the buffer location 2 is zero or non-zero. The format of the buffer is shown in
Figure 10. Address 0 contains the Source Identifier (SID), Address 1 contains the Destination Identifier (DID), and
Address 2 contains, for short packets, the value 256-N, where N represents the message length, or for long packets, the
value 0, indicating that it is indeed a long packet. In the latter case, Address 3 contains the value 512-N, where N
represents the message length. Note that on reception, the COM20020I deposits packets into the RAM buffer in the
same format that the transmitting node arranges them, which allows for a message to be received and then
retransmitted without rearranging any bytes in the RAM buffer other than the SID and DID. Once the packet is received
and stored correctly in the selected buffer, the COM20020I sets the RI bit to logic "1" to signal the microcontroller that
the reception is complete.
DATASHEET
MSB LSB
TRI RI TA POR TEST RECON TMA TTA
TRI TMA TTA
FIGURE 10 - COMMAND CHAINING STATUS REGISTER QUEUE
7.4 Command Chaining

The Command Chaining operation allows consecutive transmissions and receptions to occur without host
microcontroller intervention.
Through the use of a dual two-level FIFO, commands to be transmitted and received, as well as the status bits, are
pipelined.
In order for the COM20020I to be compatible with previous SMSC ARCNET device drivers, the device defaults to the
non-chaining mode. In order to take advantage of the Command Chaining operation, the Command Chaining Mode
must be enabled via a logic "1" on bit 6 of the Configuration Register.
In Command Chaining, the Status Register appears as in Figure 10.
The following is a list of Command Chaining guidelines for the software programmer. Further detail can be found in the
Transmit Command Chaining and Receive Command Chaining sections.
The device is designed such that the interrupt service routine latency does not affect performance.
Up to two outstanding transmissions and two outstanding receptions can be pending at any given time. The
commands may be given in any order.
Up to two outstanding transmit interrupts and two outstanding receive interrupts are stored by the device, along with
their respective status bits.
The Interrupt Mask bits act on TTA (Rising Transition on Transmitter Available) for transmit operations and TRI
(Rising Transition of Receiver Inhibited) for receive operations. TTA is set upon completion of a packet
transmission only. TRI is set upon completion of a packet reception only. Typically there is no need to mask the
TTA and TRI bits after clearing the interrupt.
The traditional TA and RI bits are still available to reflect the present status of the device.
Transmit Command Chaining
When the processor issues the first "Enable Transmit to Page fnn" command, the COM20020I responds in the usual
manner by resetting the TA and TMA bits to prepare for the transmission from the specified page. The TA bit can be
used to see if there is currently a transmission pending, but the TA bit is really meant to be used in the non-chaining
mode only. The TTA bits provide the relevant information for the device in the Command Chaining mode.
In the Command Chaining Mode, at any time after the first command is issued, the processor can issue a second
"Enable Transmit from Page fnn" command. The COM20020I stores the fact that the second transmit command was
issued, along with the page number.
After the first transmission is completed, the COM20020I updates the Status Register by setting the TTA bit, which
generates an interrupt. The interrupt service routine should read the Status Register. At this point, the TTA bit will be
found to be a logic "1" and the TMA (Transmit Message Acknowledge) bit will tell the processor whether the
transmission was successful. After reading the Status Register, the "Clear Transmit Interrupt" command is issued, thus
resetting the TTA bit and clearing the interrupt. Note that only the "Clear Transmit Interrupt" command will clear the TTA
bit and the interrupt. It is not necessary, however, to clear the bit or the interrupt right away because the status of the
transmit operation is double buffered in order to retain the results of the first transmission for analysis by the processor.
DATASHEET
This information will remain in the Status Register until the "Clear Transmit Interrupt" command is issued. Note that the
interrupt will remain active until the command is issued, and the second interrupt will not occur until the first interrupt is
acknowledged. The COM20020I guarantees a minimum of 200nS (at EF=1) interrupt inactive time interval between
interrupts. The TMA bit is also double buffered to reflect whether the appropriate transmission was a success. The
TMA bit should only be considered valid after the corresponding TTA bit has been set to a logic "1". The TMA bit never
causes an interrupt.
When the token is received again, the second transmission will be automatically initiated after the first is completed by
using the stored "Enable Transmit from Page fnn" command. The operation is as if a new "Enable Transmit from Page
fnn" command has just been issued. After the first Transmit status bits are cleared, the Status Register will again be
updated with the results of the second transmission and a second interrupt resulting from the second transmission will
occur. The COM20020I guarantees a minimum of 200ns (at EF=1) interrupt inactive time interval before the following
edge.
The Transmitter Available (TA) bit of the Interrupt Mask Register now masks only the TTA bit of the Status Register, not
the TA bit as in the non-chaining mode. Since the TTA bit is only set upon transmission of a packet (not by RESET),
and since the TTA bit may easily be reset by issuing a "Clear Transmit Interrupt" command, there is no need to use the
TA bit of the Interrupt Mask Register to mask interrupts generated by the TTA bit of the Status Register.
In Command Chaining mode, the "Disable Transmitter" command will cancel the oldest transmission. This permits
canceling a packet destined for a node not ready to receive. If both packets should be canceled, two "Disable
Transmitter" commands should be issued.
Receive Command Chaining

Like the Transmit Command Chaining operation, the processor can issue two consecutive "Enable Receive from Page
fnn" commands.
After the first packet is received into the first specified page, the TRI bit of the Status Register will be set to logic "1",
causing an interrupt. Again, the interrupt need not be serviced immediately. Typically, the interrupt service routine will
read the Status Register. At this point, the RI bit will be found to be a logic "1". After reading the Status Register, the
"Clear Receive Interrupt" command should be issued, thus resetting the TRI bit and clearing the interrupt. Note that only
the "Clear Receive Interrupt" command will clear the TRI bit and the interrupt. It is not necessary, however, to clear the
bit or the interrupt right away because the status of the receive operation is double buffered in order to retain the results
of the first reception for analysis by the processor, therefore the information will remain in the Status Register until the
"Clear Receive Interrupt" command is issued. Note that the interrupt will remain active until the "Clear Receive Interrupt"
command is issued, and the second interrupt will be stored until the first interrupt is acknowledged. A minimum of
200nS (at EF=1) interrupt inactive time interval between interrupts is guaranteed.
The second reception will occur as soon as a second packet is sent to the node, as long as the second "Enable Receive
to Page fnn" command was issued. The operation is as if a new "Enable Receive to Page fnn" command has just been
issued. After the first Receive status bits are cleared, the Status Register will again be updated with the results of the
second reception and a second interrupt resulting from the second reception will occur.
In the COM20020I, the Receive Inhibit (RI) bit of the Interrupt Mask Register now masks only the TRI bit of the Status
Register, not the RI bit as in the non-chaining mode. Since the TRI bit is only set upon reception of a packet (not by
RESET), and since the TRI bit may easily be reset by issuing a "Clear Receive Interrupt" command, there is no need to
use the RI bit of the Interrupt Mask Register to mask interrupts generated by the TRI bit of the Status Register. In
Command Chaining mode, the "Disable Receiver" command will cancel the oldest reception, unless the reception has
already begun. If both receptions should be canceled, two "Disable Receiver" commands should be issued.
RESET DETAILS
Internal Reset Logic

The COM20020I includes special reset circuitry to guarantee smooth operation during reset. Special care is taken to
assure proper operation in a variety of systems and modes of operation. The COM20020I contains digital filter circuitry
and a Schmitt Trigger on the nRESET signal to reject glitches in order to ensure fault-free operation.
The COM20020I supports two reset options; software and hardware reset. A software reset is generated when a logic
"1" is written to bit 7 of the Configuration Register. The device remains in reset as long as this bit is set. The software
DATASHEET
reset does not affect the microcontroller interface modes determined after hardware reset, nor does it affect the contents
of the Address Pointer Registers, the Configuration Register, or the Setup1 Register. A hardware reset occurs when a
low signal is asserted on the nRESET input. The minimum reset pulse width is 5TXTL. This pulse width is used by the
internal digital filter, which filters short glitches to allow only valid resets to occur.
Upon reset, the transmitter portion of the device is disabled and the internal registers assume those states outlined in the
Internal Registers section. After the nRESET signal is removed the user may write to the internal registers. Since writing
a non-zero value to the Node ID Register wakes up the COM20020I core, the Setup1 Register should be written before
the Node ID Register. Once the Node ID Register is written to, the COM20020I reads the value and executes two write
cycles to the RAM buffer. Address 0 is written with the data D1H and address 1 is written with the Node ID. The data
pattern D1H was chosen arbitrarily, and is meant to provide assurance of proper microsequencer operation.
7.5 Initialization Sequence
Bus Determination
Writing to and reading from an odd address location from the COM20020I's address space causes the COM20020I to
determine the appropriate bus interface. When the COM20020I is powered on the internal registers may be written to.
Since writing a non-zero value to the Node ID Register wakes up the core, the Setup1 Register should be written to
before the Node ID Register. Until a non-zero value is placed into the NID Register, no microcode is executed, no
tokens are passed by this node, and no reconfigurations are generated by this node. Once a non-zero value is placed in
the register, the core wakes up, but the node will not attempt to join the network until the TX Enable bit of the
Configuration Register is set.
Before setting the TX Enable bit, the software may make some determinations. The software may first observe the
Receive Activity and the Token Seen bits of the Diagnostic Status Register to verify the health of the receiver and the
network.
Next, the uniqueness of the Node ID value placed in the Node ID Register is determined. The TX Enable bit should still
be a logic "0" until it is ensured that the Node ID is unique. If this node ID already exists, the Duplicate ID bit of the
Diagnostic Status Register is set after a maximum of 420mS (or 840mS if the ET1 and ET2 bits are other than 1,1). To
determine if another node on the network already has this ID, the COM20020I compares the value in the Node ID
Register with the DID's of the token, and determines whether there is a response to it. Once the Diagnostic Status
Register is read, the DUPID bit is cleared. The user may then attempt a new ID value, wait 420mS before checking the
Duplicate ID bit, and repeat the process until a unique Node ID is found. At this point, the TX Enable bit may be set to
allow the node to join the network. Once the node joins the network, a reconfiguration occurs, as usual, thus setting the
MYRECON bit of the Diagnostic Status Register.
The Tentative ID Register may be used to build a network map of all the nodes on the network, even once the
COM20020I has joined the network. Once a value is placed in the Tentative ID Register, the COM20020I looks for a
response to a token whose DID matches the Tentative ID Register. The software can record this information and
continue placing Tentative ID values into the register to continue building the network map. A complete network map is
only valid until nodes are added to or deleted from the network. Note that a node cannot detect the existence of the next
logical node on the network when using the Tentative ID. To determine the next logical node, the software should read
the Next ID Register.
7.6 Improved Diagnostics

The COM20020I allows the user to better manage the operation of the network through the use of the internal
Diagnostic Status Register.
A high level on the My Reconfiguration (MYRECON) bit indicates that the Token Reception Timer of this node expired,
causing a reconfiguration by this node. After the Reconfiguration (RECON) bit of the Status Register interrupts the
microcontroller, the interrupt service routine will typically read the MYRECON bit of the Diagnostic Status Register.
Reading the Diagnostic Status Register resets the MYRECON bit. Successive occurrences of a logic "1" on the
MYRECON bit indicates that a problem exists with this node. At that point, the transmitter should be disabled so that the
entire network is not held down while the node is being evaluated.
The Duplicate ID (DUPID) bit is used before the node joins the network to ensure that another node with the same ID
does not exist on the network. Once it is determined that the ID in the Node ID Register is unique, the software should
write a logic "1" to bit 5 of the Configuration Register to enable the basic transmit function. This allows the node to join
the network.
DATASHEET
The Receive Activity (RCVACT) bit of the Diagnostic Status Register will be set to a logic "1" whenever activity (logic "1")
is detected on the RXIN pin.
The Token Seen (TOKEN) bit is set to a logic "1" whenever any token has been seen on the network (except those
tokens transmitted by this node).
The RCVACT and TOKEN bits may help the user to troubleshoot the network or the node. If unusual events are
occurring on the network, the user may find it valuable to use the TXEN bit of the Configuration Register to qualify
events. Different combinations of the RCVACT, TOKEN, and TXEN bits, as shown indicate different situations:
Normal Results:
RCVACT=1, TOKEN=1, TXEN=0: The node is not part of the network. The network is operating properly without this
node.
RCVACT=1, TOKEN=1, TXEN=1: The node sees receive activity and sees the token. The basic transmit function is
enabled. Network and node are operating properly.
MYRECON=0, DUPID=0, RCVACT=1, TXEN=0, TOKEN=1: Single node network.

Abnormal Results:
RCVACT=1, TOKEN=0, TXEN=X: The node sees receive activity, but does not see the token. Either no other nodes
exist on the network, some type of data corruption exists, the media driver is malfunctioning, the topology is set up
incorrectly, there is noise on the network, or a reconfiguration is occurring.
RCVACT=0, TOKEN=0, TXEN=1: No receive activity is seen and the basic transmit function is enabled. The
transmitter and/or receiver are not functioning properly.
RCVACT=0, TOKEN=0, TXEN=0: No receive activity and basic transmit function disabled. This node is not connected
to the network.
The Excessive NAK (EXCNAK) bit is used to replace a timeout function traditionally implemented in software. This
function is necessary to limit the number of times a sender issues a FBE to a node with no available buffer. When the
destination node replies to 128 FBEs with 128 NAKs or 4 FBEs with 4 NAKs, the EXCNAK bit of the sender is set,
generating an interrupt. At this point the software may abandon the transmission via the "Disable Transmitter"
command. This sets the TA bit to logic "1" when the node next receives the token, to allow a different transmission to
occur. The timeout value for the EXNACK bit (128 or 4) is determined by the FOUR-NAKS bit on the Setup1 Register.
The user may choose to wait for more NAK's before disabling the transmitter by taking advantage of the wraparound
counter of the EXCNAK bit. When the EXCNAK bit goes high, indicating 128 or 4 NAKs, the "POR Clear Flags"
command maybe issued to reset the bit so that it will go high again after another count of 128 or 4. The software may
count the number of times the EXCNAK bit goes high, and once the final count is reached, the "Disable Transmitter"
command may be issued.
The New Next ID bit permits the software to detect the withdrawal or addition of nodes to the network.
The Tentative ID bit allows the user to build a network map of those nodes existing on the network. This feature is
useful because it minimizes the need for human intervention. When a value placed in the Tentative ID Register matches
the Node ID of another node on the network, the TENTID bit is set, telling the software that this NODE ID already exists
on the network. The software should periodically place values in the Tentative ID Register and monitor the New Next ID
bit to maintain an updated network map.
OSCILLATOR
The COM20020I contains circuitry which, in conjunction with an external parallel resonant crystal or TTL clock, forms an
oscillator.
If an external crystal is used, two capacitors are needed (one from each leg of the crystal to ground). No external
resistor is required, since the COM20020I contains an internal resistor. The crystal must have an accuracy of 0.020% or
better. The oscillation frequency range is from 10 MHz to 20 MHz.
DATASHEET
The crystal must have an accuracy of 0.010% or better when the internal clock multiplier is turned on. The oscillation
frequency must be 20MHz when the internal clock multiplier is turned on.
The XTAL2 side of the crystal may be loaded with a single 74HC-type buffer in order to generate a clock for other
devices.
The user may attach an external TTL clock, rather than a crystal, to the XTAL1 signal. In this case, a 390Ω pull-up
resistor is required on XTAL1, while XTAL2 should be left unconnected.
DATASHEET
8.0 OPERATIONAL DESCRIPTION

8.1 Maximum Guaranteed Ratings*
Operating Temperature Range........................................................................................................................-40oC to +85oC
o o
Storage Temperature Range.........................................................................................................................-55 C to +150 C
Lead Temperature (soldering, 10 seconds) ................................................................................................................+325 oC
Positive Voltage on any pin, with respect to ground ...............................................................................................VDD+0.3V
Negative Voltage on any pin, with respect to ground......................................................................................................-0.3V
Maximum VDD ....................................................................................................................................................................+7V
*Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other condition above those indicated in the operational sections of this
specification is not implied.
Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum
Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their
outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on
the DC output. If this possibility exists it is suggested that a clamp circuit be used.
8.2 Dc Electrical Characteristics

VDD=3.3V±5%
TA=-40oC to +85oC
PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT

Low Input Voltage 1 VIL1 0.6 V
(All inputs except A2,
XTAL1, nRESET, nRD,
nWR, and RXIN)
High Input Voltage 1 VIH1 2.0 V
XTAL1, nRESET, nRD,
nWR, and RXIN)
Low Input Voltage 2 VIL2 1.0 V TTL Clock Input
(XTAL1)
High Input Voltage 2 VIH2 2.4 V
(XTAL1)
Low to High Threshold VILH 1.8 V Schmitt Trigger,
Input Voltage All Values at VDD =
(A2, nRESET, nRD, nWR, 3.3V
and RXIN)
High to Low Threshold VIHL 1.2 V
Input Voltage
(A2, nRESET, nRD, nWR,
and RXIN)
Low Output Voltage 1 VOL1 0.4 V ISINK=2mA
(nPULSE1 in Push/Pull
Mode, nPULSE2,
NTXEN)
High Output Voltage 1 VOH1 2.4 V ISOURCE=-1mA
(nPULSE1 in Push/Pull
Mode, nPULSE2,
nTXEN)
DATASHEET

(D0-D7)
(D0-D7)
(nINTR)
(nINTR)
(nPULSE1 in Open-Drain Open Drain Driver
Mode)
Dynamic VDD Supply IDD 35 mA 5 Mbps
Current All Outputs Open
Input Pull-up Current IP 80 200 µA VIN=0.0V
(nPULSE1 in Open-Drain
Mode, A1, AD0-AD2,
D3-D7)
Input Leakage Current IL ±10 µA VSS < VIN < VDD
AD0-AD2, D3-D7,
XTAL1, XTAL2
CAPACITANCE (TA = 25°C; fC = 1MHz; VDD = 0V)

Output and I/O pins capacitive load specified as follows:

Input Capacitance CIN 5.0 pF
Output Capacitance 1 COUT1 45 pF Maximum
(All outputs except Capacitive Load
XTAL2, nPULSE1 in which can be
Push/Pull Mode) supported by each
Output Capacitance 2 output.
COUT2 400 pF
(nPULSE1, in BackPlane
Mode Only - Open
Drain)
DATASHEET
AC Measurements are taken at the following points:
Inputs: Outputs:
t
t
2.4V 2.0V
1.4V 50%
0.4V 0.8V
t
2.4V 2.0V
1.4V
0.4V 50%
0.8V
t
Inputs are driven at 2.4V for logic "1" and 0.4 V for logic "0" except XTAL1 pin.
Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0".
DATASHEET
9.0 TIMING DIAGRAMS
AD0-AD2,
VALID VALID DATA
D3-D7
t1 t2,
nCS t4
t3 t12
ALE t11
t6 t7
t5 t13
nDS
t14
Note 2
t8
t9 t10
DIR
MUST BE: RBUSTMG bit = 0
Parameter min max units
t1 Address Setup to ALE Low 20 nS

t2 Address Hold from ALE Low 10 nS
t3 nCS Setup to ALE Low 10 nS
t4 nCS Hold from ALE Low 10 nS
t5 ALE Low to nDS Low 15 nS
t6 nDS Low to Valid Data 40 nS
t7 nDS High to Data High Impedance 0 20 nS
t8 Cycle Time (nDS Low to Next Time Low) 4TARB* nS
t9 DIR Setup to nDS Active 10 nS
t10 DIR Hold from nDS Inactive 10 nS
t11 ALE High Width 20 nS
t12 ALE Low Width 20 nS
t13 nDS Low Width 60 nS
t14 nDS High Width 20 nS
* TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 1: The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access
to Data Register requires a minimum of 5TARB from the trailing edge of nDS to
the leading edge of the next nDS.
FIGURE 11 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE
DATASHEET
AD0-AD2,
VALID VALID DATA
D3-D7
t1 t2,
t4
nCS
t3 t10
ALE
t9
t6
nRD t7
t5
t8
nWR t13 Note 3 t11
t12
Note 2
MUST BE: RBUSTMG bit = 0

t5 ALE Low to nRD Low 15 nS
t6 nRD Low to Valid Data 40 nS
t7 nRD High to Data High Impedance 0 20 nS
t8 Cycle Time (nRD Low to Next Time Low) 4TARB* nS
t11 nRD Low Width 60 nS
t12 nRD High Width 20 nS
t13 nWR to nRD Low 20 nS

Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
FIGURE 12 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE
DATASHEET
AD0-AD2, VALID VALID DATA

D3-D7
t1 t2,
nCS t4
t3 t12
ALE t11
t5 t7
nDS t6
Note 2
t8**
t13 t8
DIR t14
t9 t10

t6 Valid Data Setup to nDS High 30 nS
t7 Data Hold from nDS High 10 nS
t8 Cycle Time (nDS to Next )** 4TARB* nS

** Note 2: Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4TARB from the trailing edge of nDS to the leading edge of the
next nDS.
Write cycle for Address Pointer Low Register occurring after an access to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
FIGURE 13 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE
DATASHEET
AD0-AD2, VALID VALID DATA

D3-D7
t1 t2,
nCS t4
t3
t10
t9
ALE
t5 t7
nWR t6
Note 2
t8**
t12 t8
Note 3 t11
nRD t13

t6 Valid Data Setup to nDS High 30 nS
t8 Cycle Time (nWR to Next )** 4TARB* nS
t11 nWR Low Width 20 nS
t12 nWR High Width 20 nS
t13 nRD to nWR Low 20 nS

** Note 2: Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4TARB from the trailing edge of nWR to the leading edge of the
next nWR.
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
FIGURE 14 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE
DATASHEET
A0-A2 VALID
t1 t2
nCS
t4
t3
Note 3 t5
nRD
t10 t8 t9
Note 2
nWR t6 t7
D0-D7 VALID DATA
CASE 1: RBUSTMG bit = 0
t1 Address Setup to nRD Active 15 nS

t2 Address Hold from nRD Inactive 10 nS
t3 nCS Setup to nRD Active 5** nS
t4 nCS Hold from nRD Inactive 0 nS
t5 Cycle Time (nRD Low to Next Time Low) 4TARB* nS
t6 nRD Low to Valid Data 40** nS

** nCS may become active after control becomes active, but the access time (t6)
will now be 45nS measured from the leading edge of nCS.
**Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
FIGURE 15 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE
DATASHEET
A0-A2 VALID
t1 t2
nCS
t4
t3
Note 3 t5
nRD t10 t8 t9
Note 2
nWR t6 t7
D0-D7 VALID DATA
t1 Address Setup to nRD Active -5 nS

t2 Address Hold from nRD Inactive 0 nS
t3 nCS Setup to nRD Active -5 nS
t4 nCS Hold from nRD Inactive 0 nS
t5 Cycle Time (nRD Low to Next Time Low) 4TARB*+30 nS
t6 nRD Low to Valid Data 60** nS

** t6 is measured from the latest active (valid) timing among nCS, nRD, A0-A2.
Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
DATASHEET
A0-A2 VALID
t1 t2
nCS
t3 t4
DIR t7
t5
t6
nDS
t10 t11
Note 2
t8 t9
D0-D7 VALID DATA

t1 Address Setup to nDS Active 15 nS
t2 Address Hold from nDS Inactive 10 nS
t3 nCS Setup to nDS Active 5** nS
t4 nCS Hold from nDS Inactive 0 nS
t6 Cycle Time (nDS Low to Next Time Low) 4TARB* nS
t8 nDS Low to Valid Data 40** nS
t9 nDS High to Data High Impedence 0 20 nS

** nCS may become active after control becomes active, but the access time (t8) will
now be 45nS measured from the leading edge of nCS.
DATASHEET
A0-A2 VALID
t1 t2
nCS
t3 t4
DIR t7
t5
t6
nDS
t10 t11
Note 2
t8 t9
D0-D7 VALID DATA

t1 Address Setup to nDS Active -5 nS
t3 nCS Setup to nDS Active -5 nS
t6 Cycle Time (nDS Low to Next Time Low) 4TARB*+30 nS
t8 nDS Low to Valid Data 60** nS
t9 nDS High to Data High Impedence 0 20 nS

** t8 is measured from the latest active (valid) timing among nCS, nDS, A0-A2.
DATASHEET
A0-A2
VALID
t1 t2
nCS
t4
t3
Note 3 t8 t9
nRD t10 t5
nWR
Note 2
t6 t5**
t7
D0-D7 VALID DATA

t1 Address Setup to nWR Active 15 nS
t2 Address Hold from nWR Inactive 10 nS
t3 nCS Setup to WR Active 5 nS
t4 nCS Hold from nWR Inactive 0 nS
t5 Cycle Time (nWR to Next )** 4TARB* nS
t6 Valid Data Setup to nWR High 30*** nS
t7 Data Hold from nWR High 10 nS
t8 nWR Low Width 20 nS
t9 nWR High Width 20 nS
t10 nRD to nWR Low 20 nS

***: nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
**Note 2: Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nWR to the leading edge
of the next nWR.
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.
FIGURE 19 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE
DATASHEET
A0-A2 VALID
t1 t2
nCS
t4
DIR t3
t5 t7
nDS t10 t11
Note 2
t8 t6**
t9 t6
D0-D7 VALID DATA

t1 Address Setup to nDS Active 15 nS
t3 nCS Setup to nDS Active 5 nS
t6 Cycle Time (nDS to Next Time )** 4TARB* nS
t8 Valid Data Setup to nDS High 30*** nS

***: nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
**Note 2: Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nDS to the leading edge
of the next nDS.
Write cycle for Address Pointer Low Registers occurring after an access to
Data Register requires a minimum of 5TARB from the trailing edge of nDS to
FIGURE 20 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE
DATASHEET
nTXEN
t4
t2 t5
t1
nPULSE1
LAST BIT
(400 nS BIT TIME)
t3
t2
t1
nPULSE2
t6 t8
RXIN
t7
Parameter min typ max units

t1 nPULSE1, nPULSE2 Pulse Width 100 nS
t2 nPULSE1, nPULSE2 Period 400 nS
t3 nPULSE1, nPULSE2 Overlap -10 0 +10 nS
t4 nTXEN Low to nPULSE1 Low 850 950 nS
t5 Beginning of Last Bit Time to nTXEN High 250 350 nS
t6 RXIN Active Pulse Width 10 100 nS
t7 RXIN Period 400 nS
t8 RXIN Inactive Pulse Width 20 nS
Note: Use Only 2.5 Mbps
FIGURE 21 – NORMAL MODE TRANSMIT OR RECEIVE TIMING

(These signals are to and from the hybrid)
t1 t2 t3
4.0V
50% of VDD
XTAL1 1.0V

t1 Input Clock High Time 10 nS
t2 Input Clock Low Time 10 nS
t3 Input Clock Period 25 100 nS
t4 Input Clock Frequency 10 40 MHz
t5 Frequency Accuracy* -200 200 ppm
Note*: Input clock frequency must be 20 MHz (+-100ppm or better) to use the internal Clock Multiplier.
t5 is applied to crystal oscillaton.
FIGURE 22 – BACKPLANE MODE TRANSMIT OR RECEIVE TIMING

(These signals are to and from the differential driver or the cable)
DATASHEET
t1
nRESET
nINTR
t2
t1 nRESET Pulse Width*** 5TXTL*

t2 nINTR High to Next nINTR Low EF = 0 TDR**/2
EF = 1 4TXTL*
Note*: TXTL is period of external XTAL oscillation frequency.
Note**: TDR is period of Data Rate (i.e. at 2.5 Mbps, TDR = 400 nS)
Note***: When the power is turned on, t1 is measured from stable XTAL
oscillation after VDD was over 4.5V.
FIGURE 23 – TTL INPUT TIMING ON XTAL1 PIN
t1
nRESET
nINTR
t2
t1 nRESET Pulse Width*** 5TXTL*

t2 nINTR High to Next nINTR Low EF = 0 TDR**/2
EF = 1 4TXTL*
Note*: TXTL is period of external XTAL oscillation frequency.
Note**: TDR is period of Data Rate (i.e. at 2.5 Mbps, TDR = 400 nS)
Note***: When the power is turned on, t1 is measured from stable XTAL
oscillation after VDD was over 4.5V.
FIGURE 24 – RESET AND INTERRUPT TIMING
DATASHEET
10.0 PACKAGE OUTLINES
G
E PIN N O. J
1 A
B1
D3 D2
J J C
D1
A1
D
Seating
Plane
Plane
Base
D IM 28L
A .160-.180
A1 .090-.120
B .013-.021
B1 .026-.032
C .020-.045
D .485-.495
D1 .450-.456
D2 .390-.430
D3 .300 R EF
E .050 BSC
F .042-.056
G .042-.048
J .000-.020
R .025-.045
N OTES:
1. A ll dim ensions are in inches.
2. C ircle indicating pin 1 can appear on a top surface as show n on the draw ing or
right above it on a beveled edge.
FIGURE 25 - 28 PIN PLCC PACKAGE DIMENSIONS
DATASHEET
FIGURE 26 - 48 PIN TQFP PACKAGE OUTLINE
MIN NOMINAL MAX REMARK

A ~ ~ 1.6 Overall Package Height
A1 0.05 0.10 0.15 Standoff
A2 1.35 1.40 1.45 Body Thickness
D 8.80 9.00 9.20 X Span
1
D/2 4.40 4.50 4.60 /2 X Span Measure from Centerline
D1 6.90 7.00 7.10 X body Size
E 8.80 9.00 9.10 Y Span
1
E/2 4.40 4.50 4.60 /2 Y Span Measure from Centerline
E1 6.90 7.00 7.10 Y body Size
H 0.09 ~ 0.20 Lead Frame Thickness
L 0.45 0.60 0.75 Lead Foot Length from Centerline
L1 ~ 1.00 ~ Lead Length
e 0.50 Basic Lead Pitch
θ 0o ~ 7o Lead Foot Angle
W 0.17 ~ 0.27 Lead Width
R1 0.08 ~ ~ Lead Shoulder Radius
R2 0.08 ~ 0.20 Lead Foot Radius
ccc ~ ~ 0.0762 Coplanarity (Assemblers)
ccc ~ ~ 0.08 Coplanarity (Test House)
Note 1: Controlling Unit: millimeter
DATASHEET
11.0 APPENDIX A
This appendix describes the function of the NOSYNC and EF bits.
NOSYNC Bit
The NOSYNC bit controls whether or not the RAM initialization sequence requires the line to be idle by enabling or
disabling the SYNC command during initialization. It is defined as follows:
NOSYNC: Enable/Disable SYNC command during initialization. NOSYNC=0, Enable (Default): the line has to be idle
for the RAM initialization sequence to be written, NOSYNC=1, Disable: the line does not have to be idle for the RAM
initialization sequence to be written.
The following discussion describes the function of this bit:
During initialization, after the CPU writes the Node ID, the COM20020I will write "D1"h data to Address 000h and
Node-ID to Address 001h of its internal RAM within 6uS. These values are read as part of the diagnostic test. If the
D1 and Node-ID initialization sequence cannot be read, the initialization routine will report it as a device diagnostic
failure. These writes are controlled by a micro-program which sometimes waits if the line is active; SYNC is the micro-
program command that causes the wait. When the micro-program waits, the initial RAM write does not occur, which
causes the diagnostic error. Thus in this case, if the line is not idle, the initialization sequence may not be written,
which will be reported as a device diagnostic failure.
However, the initialization sequence and diagnostics of the COM20020I should be independent of the network status.
This is accomplished through some additional logic to decode the program counter, enabled by the NOSYNC bit.
When it finds that the micro-program is in the initialization routine, it disables the SYNC command. In this case, the
initialization will not be held up by the line status.
Thus, by setting the NOSYNC bit, the line does not have to be idle for the RAM initialization sequence to be written.
EF Bit
The EF bit controls several modifications to internal operation timing and logic. It is defined as follows:
EF: Enable/Disable the new internal operation timing and logic refinements. EF=0: (Default) Disable the new internal
operation timing (the timing is the same as in the COM20020I Rev. B); EF=1: Enable the new internal operation
timing.
The EF bit controls the following timing/logic refinements in the COM20020I:
A) Extend Interrupt Disable Time
While the interrupt is active (nINTR pin=0), the interrupt is disabled by writing the Clear Tx/Rx interrupt and Clear Flag
command and by reading the Next-ID register. This minimum disable time is changed by the Data Rate. For
example, it is 200 nS at 2.5 Mbps and 100 nS at 5 Mbps. The 100 nS width will be too short to for the Interrupt to be
seen.
Setting the EF bit will change the minimum disable time to always be more than 200 nS even if the Data Rate is 5
Mbps . This is done by changing the clock which is supplied to the Interrupt Disable logic. The frequency of this clock
is always less than 20MHz even if the data rate is 5 Mbps.
B) Synchronize the Pre-Scalar Output
The Pre-Scalar is used to change the data rate. The output clock is selected by CKP3-1 bits in the Set-Up register.
The CKP3-1 bits are changed by writing the Set-Up register from outside the CPU. It's not synchronized between the
CPU and COM20020I. Thus, changing the CKP3-1 timing does not synchronize with the internal clocks of Pre-Scalar,
and changing CKP3-1 may cause spike noise to appear on the output clock line.
Setting the EF bit will include flip-flops inserted between the Configuration register and Pre-Scalar for synchronizing
the CKP3-1 with Pre-Scalar’s internal clocks.
DATASHEET
Never change the CKP3-1 when the data rate is over 5 Mbps. They must all be zero.
C) Shorten The Write Interval Time To The Command Register
The COM20020I limits the write interval time for continuous writing to the Command register. The minimum interval
time is changed by the Data Rate. It's 100 nS at the 2.5 Mbps and 1.6 μS at the 156.25 Kbps. This 1.6 μS is very long
for CPU.
Setting the EF bit will change the clock source from OSCK clock (8 times frequency of data rate) to XTAL clock
which is not changed by the data rate, such that the minimum interval time becomes 100 nS.
D) Eliminate The Write Prohibition Period For The Enable Tx/Rx Commands
The COM20020I has a write prohibition period for writing the Enable Transmit/Receive Commands. This period is
started by the TA or RI bit (Status Reg.) returning to High. This prohibition period is caused by setting the TA/RI bit
with a pulse signal. It is 3.2 μS at 156.25 Kbps. This period may be a problem when using interrupt processing. The
interrupt occurrs when the RI bit returns to High. The CPU writes the next Enable Receive Command to the other
page immediately. In this case, the interval time between the interrupt and writing Command is shorter than 3.2 μS.
Setting the EF bit will cause the TA/RI bit to return to High upon release of the pulse signal for setting the TA/RI bit,
instead of at the start of the pulse. This is illustrated in Figure 27.
EF=0
Tx/Rx completed
TA/RI bit
Setting Pulse
nINTR pin
prohibition period
EF=1
Tx/Rx completed
TA/RI bit
Setting Pulse
nINTR pin
FIGURE 27 - EFFECT OF THE EF BIT ON THE TA/RI BIT
DATASHEET
The EF bit also controls the resolution of the following issues from the COM20020I Rev. B:
A) Network MAP Generation
Tentative ID is used for generating the Network MAP, but it sometimes detects a non-existent node. Every time the
Tentative-ID register is written, the effect of the old Tentative-ID remains active for a while, which results in an
incorrect network map. It can be avoided by a carefully coded software routine, but this requires the programmer to
have deep knowledge of how the COM20020I works. Duplicate-ID is mainly used for generating the Network MAP.
This has the same issue as Tentative-ID.
A minor logic change clears all the remaining effects of the old Tentative-ID and the old Duplicate-ID, when the
COM20020I detects a write operation to Tentative-ID or Node-ID register. With this change, programmers can use
the Tentative-ID or Duplicate-ID for generating the network MAP without any issues. This change is Enabled/Disabled
by the EF bit.
B) Mask Register Reset
The Mask register is reset by a soft reset in the COM20020I Rev. A, but is not reset in Rev. B. The Mask register is
related to the Status and Diagnostic register, so it should be reset by a soft reset. Otherwise, every time the soft
reset happens, the COM20020I Rev. B generates an unnecessary interrupt since the status bits RI and TA are back
to one by the soft reset.
This is resolved by changing the logic to reset the Mask register both by the hard reset and by the soft reset. The soft
reset is activated by the Node-ID register going to 00h or by the RESET bit going to High in the Configuration
register. This solution is Enabled/Disabled by the EF bit.
DATASHEET
12.0 APPENDIX B
12.1 Software Identification of the COM20020I Rev B, Rev C and Rev D
In order to properly write software to work with the COM20020I Rev B, C and D it is necessary to be able to identify
the different revisions of the part.
To identify the COM20020I Revision follow the following procedure:
1. Write 0x98 to Register-6 (Address = 6)

2. Write 0x02 to Register-5 (Address = 5)
3. Read Register-6
* If the value read from Register-6 is 0x98 then the part is a COM20020I Rev B or earlier
* If the value read from Register-6 is 0x9A then go to next step below
4. Write 0x80 to Register-5

5. Read Register-5
* If the value read from Register-5 is 0x00 then the part is a COM20020I Rev C
• If the value read from Register-5 is 0x80 then the part is a COM20020I Rev D
DATASHEET

Com20020i3v HT

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COM20020I 3.

SMSC COM20020I 3.3V 1 Revision 12-06-06

COM20020I3VLJP for 28 pin PLCC package

Copyright © 2006 SMSC or its subsidiaries. All rights reserved.

Revision 12-06-06 2 SMSC COM20020I 3.3V

3.0 PIN CONFIGURATIONS .................................................................................................................................6

4.0 DESCRIPTION OF PIN FUNCTIONS FOR TQFP ..........................................................................................8

5.0 PROTOCOL DESCRIPTION .........................................................................................................................11

10.0 PACKAGE OUTLINES..................................................................................................................................60

11.0 APPENDIX A.................................................................................................................................................62

12.0 APPENDIX B.................................................................................................................................................65

Figure 1 - COM20020I OPERATION ...........................................................................................................................10

SMSC COM20020I 3.3V Page 3 Revision 12-06-06

Figure 14 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE.................................................51

Table 1 - Typical Media ................................................................................................................................................23

Revision 12-06-06 4 SMSC COM20020I 3.3V

2.0 General Description

SMSC COM20020I 3.3V Page 5 Revision 12-06-06

3.0 PIN CONFIGURATIONS

AD2 19 VDD 28 16 XTAL1

D3 7 18 nTXEN A0/nMUX 1 15 VDD

Revision 12-06-06 6 SMSC COM20020I 3.3V

SMSC COM20020I 3.3V Page 7 Revision 12-06-06

4.0 DESCRIPTION OF PIN FUNCTIONS FOR TQFP

Revision 12-06-06 8 SMSC COM20020I 3.3V

PIN NO NAME SYMBOL I/O DESCRIPTION

SMSC COM20020I 3.3V Page 9 Revision 12-06-06

FIGURE 1 - COM20020I OPERATION

Revision 12-06-06 10 SMSC COM20020I 3.3V

5.0 PROTOCOL DESCRIPTION

5.2 Data Rates

Selecting Clock Frequencies Above 2.5 Mbps

CKUP1 CKUP0 CLOCK FREQUENCY (DATA RATE)

SMSC COM20020I 3.3V Page 11 Revision 12-06-06

5.3 Network Reconfiguration

5.4 Broadcast Messages

5.5 Extended Timeout Function

Revision 12-06-06 12 SMSC COM20020I 3.3V

5.6 Line Protocol

ALERT EOT DID DID

Free Buffer Enquiries

ALERT ENQ DID DID

SMSC COM20020I 3.3V Page 13 Revision 12-06-06

ALERT BURST ACK

ALERT BURST NAK

Revision 12-06-06 14 SMSC COM20020I 3.3V

6.0 SYSTEM DESCRIPTION

SMSC COM20020I 3.3V Page 15 Revision 12-06-06

ALE A2/BAL RXIN

BACKPLANE NOTE: COM20020 must be in backplane mode

FIGURE 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE

Revision 12-06-06 16 SMSC COM20020I 3.3V

FIGURE 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE

SMSC COM20020I 3.3V Page 17 Revision 12-06-06

High Speed CPU Bus Timing Support

A2-A0, nCS VALID

Sampled A2-A0, nCS VALID

More delayed nRD

FIGURE 4 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE