MAX2992

MAX2992 G3-PLC MAC/PHY Powerline Transceiver
Benefits and Features General Description

●● G3-PLC™ Compliant The MAX2992 powerline communication (PLC) baseband
●● Prestandard Conformance: IEEE® P1901.2, ITU modem delivers half-duplex, asynchronous data commu-
G.9903 nication over AC power lines at speeds up to 300kbps (full
FCC band data rate). The MAX2992 is a system-on-chip
●● Frequency-Band Compliant with CENELEC, FCC, (SoC) that combines the physical (PHY) and media access
and ARIB control (MAC) layers using Maxim’s 32-bit MAXQ30 micro-
●● Operating Frequency from 10kHz to 490kHz controller core. The MAX2991 integrated analog front-end
●● Single-Chip Solution Integrating Physical Layer transceiver interfaces seamlessly with the MAX2992, and
(PHY) and Media Access Controller (MAC) together with the MAX2992 G3-PLC firmware, forms a
complete G3-PLC-compliant modem solution.
●● Two UART and Two SPI™ Interfaces
The MAX2992 utilizes OFDM techniques with DBPSK,
●● Supports IPV6-Compatible Networking Layer
DQPSK, D8PSK modulation and forward error correc-
• 6LoWPAN IPV6 Header Compression Maximizes
tion (FEC) to enable robust data communication using
Payload Size
the electrical power grid. The design provides inherent
• Dynamic Routing Mechanism Supports Mesh
adaptability to frequency selective channels, robustness
Networking
in the presence of group delay, and immunity to impulsive
• CSMA/CA (Carrier Sense Multiple Access with
noise. To allow for regulatory compliance, the MAX2992
Collision Avoidance/Channel Access)
incorporates a programmable tone notching mechanism.
●● High-Speed, Reliable Communication This allows the notching of certain frequency bands in the
• Data Rate of up to 300kbps transmit spectrum of the modem. This feature also pro-
• Two Layers of Forward Error Correction (FEC) and vides an alternative method to address coexistence with
Cyclic Redundancy Check (CRC16) other narrowband transmitters such as legacy FSK-based
• Enhanced FEC with Reed-Solomon and Viterbi PLC systems.
• CCM* Authentication Coprocessor featuring
The MAX2992 MAC incorporates a 6LoWPAN adaptation
AES-128 Encryption/Decryption
layer to support IPv6 packets. An enhanced CSMA/CA
• Automatic Repeat Request (ARQ) Enhances Error
and ARQ, together with the mesh routing protocol, sup-
Detection and Data Reliability
ports all common MAC layer services for various network
• Dynamic Link Adaptation to Select Optimum Data
topologies. Intelligent communication mechanisms adapt
Rate Based on Channel Condition
and enhance system performance over a range of channel
• Programmable Tone Notching
conditions. These mechanisms include channel estimation,
●● AEC-Q100 Automotive Qualified adaptive tone mapping, and routing protocols. An on-chip
CCM (an extension of CCM specified in IEEE 802.15.4)
Applications authentication coprocessor with AES-128 encryption/
●● Smart Grid Communications decryption provides security and authentication.
●● Advanced Metering Infrastructure (AMI)
●● Smart Meters Ordering Information
●● AMI Concentrators PART TEMP RANGE PIN-PACKAGE
●● Electronic Vehicle Charging MAX2992ECB+ -40°C to +85°C 64 LQFP
●● Street Lighting Automation
+Denotes lead(Pb)-free/RoHS-compliant package.
●● Home Energy Monitoring
●● Building Automation Ordering Information continued at end of data sheet.
●● Solar and Renewable Energy Management
G3-PLC is a trademark of Maxim Integrated Products, Inc. SPI
is a trademark of Motorola, Inc.
IEEE is registered service mark of the Institute of Electrical and
Electronics Engineers, Inc.
19-5812; Rev 1; 4/14

Typical Application Circuit
MAX2992 MAX2991
HOST MCU Tx BLOCK

LINE LINE AC POWER
APPLICATION INTERFACE PHY
AFE DRIVER COUPLER LINE
µC
Rx BLOCK
FLASH
(G3-PLC FIRMWARE)
www.maximintegrated.com Maxim Integrated │ 2

TABLE OF CONTENTS
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Normal Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clocks, PLL, and Power-on-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AFE Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Automatic Bootstrap from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bootstrap Using the UART0 Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bootstrap Using the JTAG Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CSMA/CA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Automatic Repeat Request (ARQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PHY Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Electrical Characteristics Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
External Crystal Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
External Flash Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

TABLE OF CONTENTS (CONTINUED)

Network Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MAX2992 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LIST OF FIGURES
Figure 1. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2. MAX2992 to MAX2991 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. MAX2992 Boot Sequence Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4. Zero-Crossing AC Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. Transmitter/Receiver Block Diagram of the Baseband Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 7. SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. AFE Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 9. Star Network Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10. Tree Network Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11. Peer-to-Peer Network Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Route Request Message Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. Route Reply Message Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LIST OF TABLES
Table 1. Frequency Bands Supported by the MAX2992 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 2. Frame Error Rate Requirements in AWGN Channels (100 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3. Receiver Specification with MAX2991 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Device Details
Functional Diagram
SCK SO SI CS PROG TXDO RXDO TXD1 RXD1
FSH_SCK
UART0
FSH_SO MULTIPLIER SPI1 UART1
SERIAL SPI0 (BOOT LOADER)
FLASH FSH_SI (BOOT LOADER) PERIPHERAL BUS
FSH_CS
SECURITY KEYS AES CCM

CRC32 TIMERS (7)
128/256 BIT
BOOT ROM
PACKET MEMORY CRC16 (2)
CLOCK DOMAIN BOUNDARY

MAXQ30
INSTRUCTION
32-BIT
MEMORY RXCONV
CPU PHY RX PATH
INTRODUCTION BUS
DATA LINE
VETERBI ENRX
DATA DESCRAMBLER REED SOLOMON DEINTERLEAVER
DECODER
MEMORY
TCK RXDATA
JTAG
TMS CHANNEL SYNC
BOOT LOADER DEMODULATOR FFT RXCLK
TDI AND ESTIMATOR DETECTOR
AFE TXCONV
TDO ICE DEBUGGER
PHY TX PATH INTERFACE
ENTX
VDD WATCH CONVOLUTION
SCRAMBLER REED SOLOMON INTERLEAVER
DOG ENCODER TXDATA
RST
POWER MONITOR TXCLK
& MODULATION FIR
INTERRUPT IFFT SHAPER
RESET CONTROL MAPPER NOTCHING AFE_RST
CONTROL
GND
GND
XTAL1S XTALS
XTALS
PLLS1
PLLS1 CLK_CPU
MULT M DIV N PLLS2
PLLA2 MAX2992
PLLS2
DIV O PLLS2
XTAL2S PLLS CLK_PHY
XTALA DIV P
XTAL1A XTALS PLLA2
XTALS
PLLA1 PLLS2
MULT M DIV N CLK_AFE
XTALA DIV P
PLLA2 PLLA1
DIV O
XTAL2A PLLA

Pin Configuration
P2.4/AFE_SHDN
P2.2/AGC_FRZ
P2.0/SCK
TOP VIEW
P2.3/SO
XTAL1A
P2.5/CS
XTAL2A
P2.1/SI
VDDIO
VDDC
TMS
P2.6
P2.7
TCK
VSS
TDI
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSS 49 32 TDO
VDD 50 31 PROG
P3.0/TXCONV 51 30 VSS
P3.1/TXDATA 52 29 P1.7/FSH_CS
VSS 53 28 P1.6/FSH_SO
VDDC 54 27 P1.5/FSH_SI
P3.2/TXCLK 55 MAX2992 26 P1.4/FSH_SCK
VDDIO 56 25 VDDIO
P3.3/RXCLK 57 24 P1.3
VSS 58 23 P1.2
VDDC 59 22 P1.1/RXD0
P3.4/RXDATA 60 21 P1.0/TXD0
P3.5/RXCONV 61 20 VDDC
P3.6/AFE_RST 62 19 VSS
P3.7/ENRX 63 18 XTAL2S
P3.8/ENTX 64 17 XTAL1S
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
P0.4/COL
P0.2/AFE_SDOUT
P0.5/ACT
P0.6/RDY
RST
P0.0/AFE_CS
P0.1/AFE_SDIN
P0.3/AFE_SCLK
VSS
VDDC
VDDIO
VDDC
VSS
P0.7/PULSE
VDD
VSS
LQFP

Pin Description
PIN NAME TYPE FUNCTION
5, 9, 16,
19, 30,
VSS P Ground
33, 49,
53, 58
6, 8, 20,
+1.2V Digital Power Supply. Bypass VDDC to VSS with a 100nF capacitor as close as
34, 54, VDDC P
possible to the device.
59,
7, 25, +3.3V I/O Power Supply. Bypass VDDIO to VSS with a 100nF capacitor as close as
VDDIO P
39, 56 possible to the device.
Reset. The RST input/output recognizes external active-low reset inputs and employs
an internal pullup resistor to allow for a combination of wired-OR external reset
14 RST I/O
sources. Bypass with a 220nF capacitor to VSS and use a 10kΩ pullup resistor to
VDDIO.
+1.2V Analog Power Supply. Bypass VDD to VSS with a 100nF capacitor as close as
15, 50 VDD P
possible to the device.
17 XTAL1S I Crystal Oscillator Input/Output. The crystal oscillator input/output provide support
for parallel resonant, AT cut crystals. XTAL1S also acts as an input when there is
an external clock source in place of a crystal. XTAL2S is the output of the crystal
18 XTAL2S O amplifier. Signal XTALS provides the clock base for the system clock.
PROG. PROG serves to initiate the UART boot loader. To activate the UART boot
loader, PROG must be held low for at least 3 system clock cycles. The host must
31 PROG I then send the autobaud character (0x0D) at a baud rate of 57,600 baud or less. The
MAX2992 detects the serial baud rate and reply with the prompt character (0x3E). At
this time, the bootloader protocol can be used to program the device.
32 TDO O JTAG Data Output
44 TDI I JTAG Data Input
45 TMS I JTAG Mode Select Input
46 TCK I JTAG Clock Input
47 XTAL1A I Crystal Oscillator Input/Output. The crystal oscillator input/output provides support
for parallel resonant, AT cut crystals. XTAL1A also acts as an input when there is
an external clock source in place of a crystal. XTAL2A is the output of the crystal
48 XTAL2A O amplifier. Signal XTALA provides the clock base for the AFE interface.
PORT 0
P0.0/AFE_CS. P0.0/AFE_CS is used by the MAX2992 G3-PLC firmware to
implement an SPI command bus to the MAX2991 AFE. P0.0/AFE_CS is the chip-
select line to the MAX2991. This is the general-purpose I/O hardware and part of the
I/O 8-bit I/O port P0.
1 P0.0/AFE_CS
O P0.0/AFE_CS provides hardware support that is available, but not utilized by the
MAX2992 G3-PLC firmware.
● Interrupt input/stop mode wake-up.
● Timer I/O to Timer 0, In/Out A (Note 1).

Pin Description (continued)

P0.1/AFE_SDIN. P0.1/AFE_SDIN is used by MAX2992 G3-PLC firmware to
implement an SPI command bus to the MAX2991 AFE. P0.1/AFE_SDIN is the serial
data to the MAX2991. This is general-purpose I/O hardware and part of the 8-bit I/O
I/O port P0.
2 P0.1/AFE_SDIN
O P0.1/AFE_SDIN provides hardware support that is available, but not utilized by the
● Timer I/O to Timer 0, In/Out B (Note 1).
P0.2/AFE_SDOUT. P0.2/AFE_SDOUT is used by the MAX2992 G3-PLC firmware

to implement an SPI command bus to the MAX2991 AFE. P0.2/AFE_SDOUT is the
serial data returned from the MAX2991. This is the general-purpose I/O hardware and
I/O part of the 8-bit I/O port P0.
3 P0.2/AFE_SDOUT
O P0.2/AFE_SDOUT provides hardware support that is available, but not utilized by the
P0.3/AFE_SCLK. P0.3/AFE_SCLK is used by MAX2992 G3-PLC firmware to

implement an SPI command bus to the MAX2991 AFE. P0.3/AFE_SCLK is the serial
clock to the MAX2991.This is the general-purpose I/O hardware and part of the 8-bit
I/O I/O port P0.
4 P0.3/AFE_SCLK
O P0.3/AFE_SCLK provides hardware support that is available, but not utilized by the
P0.4/COL. P0.4/COL is used by the MAX2992 G3-PLC firmware to indicate modem

status. P0.4/COL is the collision/packet error indicator, and can be used to drive a
COL LED. This is the general-purpose I/O hardware and part of the 8-bit I/O port P0.
I/O
10 P0.4/COL P0.4/COL provides hardware support that is available, but not utilized by the
O
P0.5/ACT. P0.5/ACT is used by the MAX2992 G3-PLC firmware to indicate modem

status. P0.5/ACT is the activity indicator and can be used to drive an ACT LED. This
is general-purpose I/O hardware and part of the 8-bit I/O port P0.
I/O
11 P0.5/ACT P0.5/ACT provides hardware support that is available, but not utilized by the
O


P0.6/RDY. P0.6/RDY is used by the MAX2992 G3-PLC firmware to indicate modem

status. PO.6/RDY is the modem-ready indicator and is used to drive a RDY LED. This
is the general-purpose I/O hardware and part of the 8-bit I/O port P0.
12 P0.6/RDY I/O P0.6/RDY provides hardware support that is available, but not utilized by the
P0.7/PULSE. P0.7/PULSE is used by the MAX2992 G3-PLC firmware to input pulses

from an external zero-crossing detector. This is general-purpose I/O hardware and
part of the 8-bit I/O port P0.
13 P0.7/PULSE I/O P0.7/PULSE provides hardware support that is available, but not utilized by the
PORT 1
P1.0/TXD0. P1.0/TXD0 provides connections to dedicated UART hardware. This is
used by the MAX2992 G3-PLC firmware to implement the UART host interface. P1.0/
I/O
21 P1.0/TXD0 TXD0 is the transmit data from the MAX2992 to the host. This is the general-purpose
O
I/O hardware and part of the 8-bit I/O port P1.
Connect P1.0/TXD0 with a 5kΩ resistor to VDDIO (Note 1).
P1.1/RXD0. P1.1/RXD0 provides connections to dedicated UART hardware. This is

I/O used by the MAX2992 G3-PLC firmware to implement the UART host interface. P1.1/
22 P1.1/RXD0
I RXD0 is the receive data from the host to the MAX2992. This is the general-purpose
I/O hardware and part of the 8-bit I/O port P1 (Note 1).
P1.2. P1.2 provides connections to dedicated UART hardware used by the MAX2992
I/O
23 P1.2 G3-PLC firmware for reserved function. Leave unconnected. This is the general-
O
purpose I/O hardware and part of the 8-bit I/O port P1 (Note 1).
P1.3. P1.3 provides connections to dedicated UART hardware used by the MAX2992
I/O
24 P1.3 G3-PLC firmware for reserved function. This is the general-purpose I/O hardware and
I
part of the 8-bit I/O port P1 (Note 1).
P1.4/FSH_SCK. P1.4/FSH_SCK provides dedicated connections to the SPI hardware,

and after power-on reset, the MAX2992 attempts to bootstrap code from an external
flash if it is present. P1.4/FSH_SCK is the serial clock from the MAX2992 to the flash.
This is the general-purpose I/O hardware and part of the 8-bit I/O port P1.
I/O
26 P1.4/FSH_SCK After boot, the SPI hardware can be used by the MAX2992 G3-PLC firmware. This
O
is not utilized by the MAX2992 G3-PLC firmware, but P1.4/FSH_SCK provides the
capability of:
● SPI master clock output.
● SPI slave clock input (Note 1).


P1.5/FSH_SI. P1.5/FSH_SI provides dedicated connections to the SPI hardware, and

after power-on reset, the MAX2992 attempts to bootstrap code from an external flash
if it is present. P1.5/FSH_SI is the serial data from the MAX2992 to the flash. This is
the general-purpose I/O hardware and part of the 8-bit I/O port P1.
I/O
27 P1.5/FSH_SI After boot, the SPI hardware can be used by the MAX2992 G3-PLC firmware. This
O
is not utilized by the MAX2992 G3-PLC firmware, but P1.4/FSH_SI provides the
capability of:
● SPI master output data.
● SPI slave input data (Note 1).
P1.6/FSH_SO. P1.6/FSH_SO provides dedicated connections to the SPI hardware,

flash if it is present. P1.6/FSH_SO is the serial data return to the MAX2992 from the
flash. This is the general-purpose I/O hardware and part of the 8-bit I/O port P1.
I/O
28 P1.6/FSH_SO After boot, the SPI hardware can be used by the MAX2992 G3-PLC firmware. This
O
is not utilized by the MAX2992 G3-PLC firmware, but P1.6/FSH_SO provides the
capability of:
● SPI master data input.
● SPI slave data output (Note 1).
P1.7/FSH_CS. P1.7/FSH_CS provides dedicated connections to the SPI hardware,
flash if it is present. P1.7/FSH_CS is the serial chip select from the MAX2992 to the
I/O flash. This is the general-purpose I/O hardware and part of the 8-bit I/O port P1.
29 P1.7/FSH_CS
O After boot, the SPI hardware can be used by the MAX2992 G3-PLC firmware. This
is not utilized by the MAX2992 G3-PLC firmware, but P1.7/FSH_CS provides the
capability of:
● SPI slave chip select (Note 1).
PORT 2
P2.7. P2.7 is not used by the MAX2992 G3-PLC firmware. It is configured as an

unused input with the internal pullup enabled. It can be left unconnected. This is the
general-purpose I/O hardware and part of the 8-bit I/O port P2.
P2.7 provides hardware support that is available, but not utilized by the MAX2992
35 P2.7 I/O
G3-PLC firmware:
● Hardware flow control line CTS for UART0.
● Timer I/O to Timer 4, In/Out A.


P2.6. P2.6 is not used by the MAX2992 G3-PLC firmware. It is configured as an

unused input with the internal pullup enabled. It can be left unconnected. This is the
general-purpose I/O hardware and part of the 8-bit I/O port P2.
P2.6 provides hardware support that is available, but not utilized by the MAX2992
36 P2.6 I/O
G3-PLC firmware
● Hardware flow control line RTS for UART0.
● Timer I/O to Timer 4, In/Out A.
P2.5/CS. P2.5/CS provides dedicated connections to SPI hardware. This is used by

the MAX2992 G3-PLC firmware to implement the SPI host interface. P2.5/CS is the
active-low, chip select from the host to the MAX2992. This is general-purpose I/O
I/O
37 P2.5/CS hardware and part of the 8-bit I/O port P2.
O
P2.5/CS provides hardware support that is available, but not utilized by the MAX2992
G3-PLC firmware.
P2.4/AFE_SHDN. P2.4/AFE_SHDN is used by the MAX2992 G3-PLC firmware to

place the MAX2991 AFE into shutdown mode for lowest power consumption. P2.4/
AFE_SHDN provides hardware support that is available, but not utilized by the
38 P2.4/AFE_SHDN I/O
MAX2992 G3-PLC firmware. This is general-purpose I/O hardware and part of the
8-bit I/O port P2.
P2.3/SO. P2.3/SO provides dedicated connections to SPI hardware. This is used by

I/O the MAX2992 G3-PLC firmware to implement the SPI host interface. P2.3/SO is the
40 P2.3/SO
O serial data to the host from the MAX2992. This is general-purpose I/O hardware and
part of the 8-bit I/O port P2 (Note 1).
P2.2/AGC_FRZ. P2.2/AGC_FRZ provides dedicated connections to the PHY

I/O hardware. This is used by the MAX2992 G3-PLC firmware to signal the MAX2991
41 P2.2/AGC_FRZ
O AFE to freeze its automatic gain control (AGC) setting. This is general-purpose I/O
hardware and part of the 8-bit I/O port P2 (Note 1).
P2.1/SI. P2.1/SI provides dedicated connections to SPI hardware. This is used by the
I/O MAX2992 G3-PLC firmware to implement the SPI host interface. P2.1/SI is the serial
42 P2.1/SI
O data from the host to the MAX2992. This is general-purpose I/O hardware and part of
the 8-bit I/O port P2 (Note 1).
P2.0/SCK. P2.0/SCK provides dedicated connections to SPI hardware. This is used

I/O by the MAX2992 G3-PLC firmware to implement the SPI host interface. P2.0/SCK is
43 P2.0/SCK
I the serial clock from the host to the MAX2992. This is general-purpose I/O hardware
and part of the 8-bit I/O port P2 (Note 1).


PORT 3
P3.0/TXCONV. P3.0/TXCONV provides dedicated connections to AFE interface
I/O hardware. This is used by the MAX2992 G3-PLC firmware to implement the AFE
51 P3.0/TXCONV
O interface to the MAX2991. P3.0/TXCONV is the TX enable line to the MAX2991. This
is general-purpose I/O hardware and part of the 8-bit I/O port P3 (Note 1).
P3.1/TXDATA. P3.1/TXDATA provides dedicated connections to AFE interface hardware.

I/O This is used by the MAX2992 G3-PLC firmware to implement the AFE interface to the
52 P3.1/TXDATA
O MAX2991. P3.1/TXDATA is the TX serial data output to the MAX2991. This is general-
purpose I/O hardware and part of the 8-bit I/O port P3 (Note 1).
P3.2/TXCLK. P3.2/TXCLK provides dedicated connections to AFE interface

55 P3.2/TXCLK
O interface to the MAX2991. P3.2/TXCLK is the TX serial clock to the MAX2991. This is
general-purpose I/O hardware and part of the 8-bit I/O port P3 (Note 1).
P3.3/RXCLK. P3.3/RXCLK provides dedicated connections to AFE interface

57 P3.3/RXCLK
O interface to the MAX2991. P3.3/RXCLK is the RX serial clock to the MAX2991. This
P3.4/RXDATA. P3.4/RXDATA provides dedicated connections to AFE interface

60 P3.4/RXDATA
I interface to the MAX2991. P3.4/AFE_SDI is the RX serial data from the MAX2991.
This is general-purpose I/O hardware and part of the 8-bit I/O port P3 (Note 1).
P3.5/RXCONV. P3.5/RXCONV provides dedicated connections to AFE interface

61 P3.5/RXCONV
O interface to the MAX2991. P3.5/RXCONV is the RX Enable line to the MAX2991. This
P3.6/AFE_RST. P3.6/AFE_RST is used by the MAX2992 G3-PLC firmware to reset the
I/O
62 P3.6/AFE_RST MAX2991. This is general-purpose I/O hardware and part of the 8-bit I/O port P3
O
(Note 1).
P3.7/ENRX. P3.7/ENRX is used by the MAX2992 G3-PLC firmware to enable the RX
I/O
63 P3.7/ENRX channel in the MAX2991. This is general-purpose I/O hardware and part of the 8-bit
O
I/O port P3 (Note 1).
P3.8/ENTX. P3.8/ENTX is used by the MAX2992 G3-PLC firmware to enable the TX
I/O
64 P3.8/ENTX channel in the MAX2991. This is general-purpose I/O hardware and part of the 8-bit
O
I/O port P3 (Note 1).
Note 1: Refer to the MAX2992 G3-PLC Firmware Release Note for updates to the function implemented.

Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)
G3-PLC DATA RATE* G3-PLC DATA RATE* G3-PLC DATA RATE*

CENELEC A (36kHz to 91kHz) MAX2992 toc01
FCC (150kHz TO 487.5kHz) FCC (10kHz TO 487.5kHz)
MAX2992 toc02
MAX2992 toc03
D8PSK (MAX) D8PSK (MAX) D8PSK (MAX)
D8PSK (TYP) D8PSK (TYP) D8PSK (TYP)
DQPSK (TYP) DQPSK (TYP) DQPSK (TYP)
DBPSK (TYP) DBPSK (TYP) DBPSK (TYP)
ROBO (TYP) ROBO (TYP) ROBO (TYP)
0 10 20 30 40 50 0 50 100 150 200 250 300 0 50 100 150 200 250 300
*POINT-TO-POINT DATA RATE (kbps) *POINT-TO-POINT DATA RATE (kbps) *POINT-TO-POINT DATA RATE (kbps)
Detailed Description provides advanced CSMA/CA and ARQ functions and

The MAX2992 integrates a high-performance Maxim supports all common MAC layer services.
MAXQ30 32-bit RISC core with optimized OFDM PHY, Power Management
128/256-bit AES and CRC hardware and peripherals
The MAX2992 power-management features minimize
including UART serial communication, SPI interface,
power consumption by clock gating and by adjusting the
serial AFE interface, watchdog/countdown timers, GPIO,
operating frequency. Clock gating is used to eliminate
and external interrupts. The MAX2992 G3-PLC modem
active power of on-chip functional units when not in use.
is based on Orthogonal Frequency Division Multiplexing
A clock divider of up to 256 is set by software to reduce
(OFDM) that places multiple evenly spaced carriers within
the operating frequency to the required performance level
the available frequency band. Data is modulated onto
per single application.
these carriers and three modulation methods are support-
ed: DBPSK, DQPSK, and D8PSK. Special data interleav- Normal Operating Mode
ing and forward error correction techniques enhance the In normal operating mode, the MAX2992’s power-
robustness of communication that is immune to impulsive management features minimize power consumption by
noise, adaptable to frequency selective channels, and adjusting the frequency of CPU and PHY operation to
robust in the presence of group delay. Additional perfor- match the dynamic load on the device.
mance is obtained by adaptive tone mapping, a process
by which the MAX2992 automatically detects carriers with Idle Mode
poor SNR, redistributing data onto better performing carri- In idle mode, the MAX2992 lowers power consumption
ers. These features allow the MAX2992 to adapt to chan- by shutting down the MAXQ30 processor, but keeps the
nel conditions to provide superior data rates for a given PHY’s receive circuitry active so that it can detect a pow-
channel condition. External flash stores the complete erline packet. At least one clock must be running during
G3-PLC application firmware supplied by Maxim, which idle mode. The processor awakes on the detection of a
executes from the on-chip SRAM memory. G3-PLC data line SYNC at the beginning of a packet and returns to
and control is accomplished using the G3-PLC modem normal operating mode to receive the powerline packet.
interface over the UART or SPI port. A full description Stop Mode
of this interface is provided in the MAX2992 G3-PLC
Stop mode disables all clocks and circuits within the
Interface Guide. The MAC, implemented on the MAXQ30,
MAX2992. All modem functions are disabled. This is

the lowest power state for the device where only leak- Refer to the MAX2992 G3-PLC Interface Guide and
age power is consumed. An external interrupt causes MAX2992 G3-PLC Firmware Release Note for details on
the MAX2992 to exit from the stop mode. Stop mode is the use of the SPI1 port.
controlled by the MAX2992 G3-PLC firmware. Refer to
the MAX2992 G3-PLC Interface Guide and MAX2992 GPIO
G3-PLC Firmware Release Note for details on the use of The MAX2992 features 5V tolerant, 3.3V I/O. Each I/O
stop mode. can be either an input or output. The MAX2992 G3-PLC
firmware configures each I/O as described in the Pin
UART Interface Configuration section. Refer to the MAX2992 G3-PLC
The MAX2992 features two hardware UARTs (UART0 Firmware Release Note for additional GPIO assignments.
and UART1). UART0 has a 16-byte deep receive and When in input mode, a weak pullup resistance is enabled
transmit FIFO with configurable interrupt thresholds and pulling the I/O high. A series NFET provides the I/O’s
it supports hardware flow control. Additionally, UART0 high voltage tolerance (Figure 1). This degrades the
provides a hardware function for booting the device. The VOH observed and an external resistive pullup is recom-
MAX2992 G3-PLC firmware dedicates UART0 to the host mended when the I/O is not actively driven (such as RST
interface with a baud rate of 115,200bps without flow con- or PROG, see the Pin Description).
trol. See the MAX2992 G3-PLC Firmware Release Note
for additional information on the UART0 host interface
settings.
VDDIO
Data transfer for communication on the power line and
status and control commands are passed between host
and the MAX2992 G3-PLC modem over UART0. A simple
frame format is used to define data and management I/O
REN
primitives. A complete description of the frame format and DEVICE
command primitives is provided in the MAX2992 G3-PLC CLOAD
Interface Guide.
The MAX2992 G3-PLC firmware utilizes UART1 for a WEAK PULLUP
reserved function. Do not connect in user designs.
Serial Peripheral Interface (SPI) Figure 1. GPIO
The MAX2992 includes two serial peripheral interface Timers
modules (SPI0 and SPI1). The MAX2992 SPI hard-
The MAX2992 incorporates seven 16-bit programmable
ware can operate in slave or master modes. This is a
timers to allow precise control of internal and external
common, high-speed, synchronous peripheral interface
events. Each timer can operate in two modes: count-stop
that shifts a bit stream of variable length and data rate
or wrap-round. The timers can be configured so that the
between the microcontroller and other peripheral devices.
timers generate interrupts upon reaching the extreme
Programmable clock frequency, character lengths, polar-
value. The timers also feature output modes suitable for
ity, and error handling enhance the usefulness of the
synthesizing PWM. The MAX2992 G3-PLC firmware uses
peripheral. The maximum baud rate of the SPI interface is
these timers within its operating system, and to implement
half the system clock for master mode operation and 1/8th
CSMA and AC phase detection. Refer to the MAX2992
the system clock for slave mode operation.
G3-PLC Interface Guide and MAX2992 G3-PLC Firmware
SPI0 features a boot loading function that is the primary Release Note for information on timer use.
method for initializing the MAXQ30 memory after reset.
SPI0 boot loading is described in the Boot Options section. Clocks, PLL, and Power-on-Reset
SPI1 is assigned by the MAX2992 G3-PLC firmware to The MAX2992 provides two built-in oscillators each with
implement an alternative host interface to UART0. When an associated PLL. The device can function in a one or a
used as a host interface, four MAX2992 signals, P2.0/ two crystal configuration, either reducing system compo-
SCK, P2.5/CS, P2.1/SI, and P2.3/SO must be connected nents or maximizing flexibility of the operating frequencies
to the host processor. in the system. The one crystal configuration requires a

crystal connected between XTAL1S and XTAL2S. Drive

XTAL1A low, have XTAL2A unconnected, and connect
VDD (Pin 50) to VSS in one crystal mode. ENTX P3.8/ENTX
The MAX2992 G3-PLC firmware uses the one crys- TXDATA P3.1/TXDATA
tal configuration with a 19.2MHz crystal connected to
TXCONV P3.0/TXCONV
XTAL1S and XTAL2S. This crystal is used to generate
both CPU and AFE clocks. For this configuration, the CPU TXCLK P3.2/TXCLK
clock is set to 76.8MHz and AFE clock is 6.4MHz for the ENRX P3.7/ENRX
MAX2991 MAX2992
CENELEC frequency band with a 400kHz sample rate. AFE
For FCC and ARIB bands, the AFE clock is 19.2MHz with RXDATA P3.4/RXDATA
a 1.2MHz sample rate. RXCONV P3.5/RXCONV

The two crystal configuration requires that a crystal be RXCLK P3.3/RXCLK
connected between XTAL1S and XTAL2S, and XTAL1A
AGC_CS P2.2/AGC_FRZ
and XTAL2A. Refer to the MAX2992 G3-PLC Firmware
Release Note for information on the crystal configuration RESET P3.6AFE_RST
used.
External Reset Figure 2. MAX2992 to MAX2991 Interface
During normal operation, the MAX2992 can be placed
into external reset mode by holding RST low for a mini- ● At any time, the PROG can be used to initiate a
mum of eight clock cycles. After RST returns high, the UART0 boot load cycle.
MAXQ30 processor exits the reset state within eight clock
● From POR, if the JTAG interface and PROG are not
cycles and begins program execution.
active, the MAX2992 boots load from external flash
Watchdog Timer using the SPI0 interface.
The watchdog timer is a programmable hardware timer ● Once a program is loaded (by any means) and the
that can be used to reset the processor in case of a soft- program valid bit is set, successive resets causes
ware lockup or other unrecoverable error. The MAX2992 reexecution of the loaded code. An additional boot
G3-PLC firmware uses the watchdog timer to enhance load cycle is not required.
system reliability.
Automatic Bootstrap from Flash
AFE Serial Interface ● When the JTAG and UART0 bootstrap are not select-
The MAX2992 AFE interface is designed to support the ed, the MAX2992 boots from an external flash device
MAX2991. The interface includes separate receive and over SPI0. The flash must be preprogrammed with
transmit serial interfaces. Connect the MAX2992 to the the MAX2992 G3-PLC firmware. AES encryption of
MAX2991 as shown in Figure 2. Refer to the MAX2991 the flash image is supported to protect any deployed
data sheet for a description of the serial interface timing. application. Refer to the MAX2992 Evaluation Kit for
details on programming the flash.
Boot Options
The MAX2992 executes program code from internal Bootstrap Using the UART0 Loader
SRAM. This SRAM is volatile and must be loaded with The MAX2992 can be booted over the UART0 host inter-
application code after a power-cycle event. There are face to avoid the need for a dedicated flash device. The
three options for loading the SRAM: UART0 boot load procedure is:
● Automatic bootstrap from external flash 1. Pull PROG low for a minimum of 8 clock cycles. If
automatic boot after power-up is desired, place an RC
● Bootstrap through the UART0 loader
on PROG so that PROG rises at least 8 clock cycles
● Bootstrap through the JTAG loader after RST.
Figure 3 shows the flow diagram for MAX2992 booting. 2. Send the MAX2992 the character 0x0D (8-bit, no par-
The flowchart illustrates: ity) at a rate of 57,600 baud or less.

PROG INPUT RESET

SPE = SYSTEM PROGRAM ENABLE BIT WITHIN THE JTAG SPR REGISTER.
PSPE = PROG SYSTEM PROGRAM ENABLE BIT, SET BY THE PROG INPUT
AND CLEARED BY OTHER FORMS OF RESET.
PV = PROGRAM VALID BIT, SET AT THE COMPLETION OF LOADING CODE
EXECUTE ROM
SET PSPE INTO INSTRUCTION RAM AND CLEARED BY POWER-ON RESET.
0x800000h
YES
SPE? JTAG BOOTLOADER
NO
YES
PSPE?
NO
RUN APPLICATION JUMP TO YES

PV?
0x000000h
NO
BOOTSTRAP FROM FLASH UART0 AUTOBAUD
NO
PASS UART0 BOOTLOADER
YES
SET PV ON SUCCESSFUL
SET PV
CODE LOAD
RESET RESET
Figure 3. MAX2992 Boot Sequence Flow Chart
3. The MAX2992 measures the timing and autocalibrates Toggling RST exits the serial boot loader whereby the
to the baud rate. MAX2992 follows the boot sequence described by Figure 3.
4. The MAX2992 acknowledges entry to the serial loader Details of using the serial boot loader commands to imple-
by transmitting a prompt character (0x3E). ment a UART0 boot strap are provided in the MAX2992
Evaluation Kit.
Details of using the serial boot-loader commands to imple-
ment a UART0 bootstrap are provided in the MAX2992
Evaluation Kit. The serial bootloader does not utilize the
hardware flow control feature of UART0. The loader man-
ages flow control using the communication protocol.

PULSE WIDTH
HALF CYCLE
=10ms/8.3ms
50Hz/60Hz
ZERO-CROSSING DETECTOR
Figure 4. Zero-Crossing AC Detector
Bootstrap Using the JTAG Loader Automatic Repeat Request (ARQ)

The JTAG bootstrap loader mode initializes the nonvola- To enhance error detection and improve data reliability,
tile memory of the internal MAXQ30 microcontroller. The the MAX2992 utilizes an automatic repeat request proto-
JTAG loader is used by Maxim as a development inter- col. Since PLC communication is a half-duplex connec-
face and should not be utilized in user systems. tion, the transmitter waits for an acknowledgment (ACK)
of each transmission before it proceeds with the next
AC Phase Detector transmission. If the transmitter does not receive an ACK
To know the phases of each meter, the MAX2992 fea- packet, the transmitter resends the packet.
tures internal timers to measure time intervals of pulses
resulted from zero-crossing of AC 50Hz/60Hz as shown PHY Overview
in Figure 4. P0.7/PULSE is used to input pulses received The MAX2992 powerline modem is designed to over-
from an external zero-crossing detector to reset an 8-bit come the challenges associated with the harsh powerline
counter. The minimum required pulse width is 1% of the environment for data communications. Some of the chal-
cycle. lenges are noted below:
CSMA/CA ● Channel variability with frequency, location, and time
Concurrent transmission by multiple nodes can result in ● Narrowband, wideband, and impulsive noise com-
frame collisions that occur when multiple transmissions monly present on the power line
interfere with each other, distorting the signal sufficiently ● Presence of narrowband interference and multipath
to cause communication to fail. Carrier Sense Multiple signal propagation
Access/Collision Avoidance (CSMA/CA) is a mechanism
● Low and time varying network impedance (3Ω to 30Ω)
to reduce the probability of collisions. When using CSMA
as soon as a node is ready to transmit a packet, the ● Propagation through transformers that subject the
device checks the channel for activity. If no other node channel to severe group delay and attenuation
is transmitting the node transmits its packet. If another The MAX2992 modem solution is based on orthogonal
transmitter is detected, the device waits for that transmis- frequency division multiplexing (OFDM) to overcome the
sion to end and then waits for a randomly selected period powerline channel impairment, providing high reliability
of time for another device to start transmitting on the in data transmission. This method combines good band-
channel. This wait time is called a random back-off time. width efficiency (high data rate) with the possibility of a
If no other device has started transmitting at the end of very flexible bandwidth allocation. In combination with
the back-off time, the device starts its transmission. This error correction coding, the MAX2992 is robust in the
process is repeated until the device gets access to the presence of frequency selective channels and resilient to
channel. All the devices in the system randomly choose jammer signals and impulsive noise.
their back-off time from one of a limited number of pre-
defined time slots after the end of the prior transmission.

The OFDM technique places evenly spaced carriers into Table 1 shows the frequency bands with which the
the available frequency band. The MAX2992 can be con- MAX2992 modem complies.
figured to operate in a subset of frequencies in the range
10kHz to 490kHz, encompassing CENELEC, ARIB, and Table 1. Frequency Bands Supported by
FCC frequency bands. Three modulation methods are the MAX2992
supported; DBPSK, DQPSK, and D8PSK. This allows
the MAX2992 to trade off channel condition and data rate NUMBER FIRST LAST
to achieve the highest possible data through for a given COMPONENT OF CARRIER CARRIER
channel condition. Additional performance is obtained by CARRIERS (kHz) (kHz)
adaptive tone mapping, a process by which the MAX2992 CENELEC A 36 35.93 90.62
automatically detects carriers with poor SNR, redistribut- CENELEC B 16 98.43 121.87
ing data onto better performing channels. CENELEC C 7 128.12 137.50
There are several advantages of the MAX2992 OFDM CENELEC BC 26 98.43 137.50
scheme as compared to traditional single carrier FSK or CENELEC D 4 142.18 146.87
spread-spectrum systems: FCC1 72 154.6875 487.5
● The MAX2992 OFDM allows an extremely flexible FCC2 97 37.5 487.5
allocation and use of a given channel bandwidth. As FCC3 24 154.6875 262.5
an example, the lower and the upper limit of the used FCC4 40 304.6875 487.5
frequency band can easily be configured. It is also
ARIB1 54 154.6875 403.125
possible to use two or more noncontiguous sub-bands
for the transmission of a single data stream. ARIB2 79 37.5 403.125
● It is considerably more robust against intersymbol inter- The combined PHY and MAC in the MAX2992 meet the
ference (ISI) or group delay distortion caused by the transmitter/receiver technical requirements for highly
transmission channel than narrowband systems. This reliable data communication in powerline networks, as
is mainly due to the fact that the parallel transmission shown in Table 2 and Table 3.
on several carriers leads to longer symbol duration.
Furthermore, ISI is simply removed by inserting guard Table 2. Frame Error Rate Requirements
intervals and cyclic prefixes between the symbols. in AWGN Channels (100 Bytes)
The MAX2992 is robust in presence of narrowband inter-
ference because such jammers typically destroy a single SIGNAL-TO- MODULATION
FRAME ERROR
carrier only. Through the use of forward error correction NOISE RATIO AND CODING
RATE (%)
coding—the erroneous data is detected and corrected (dB) RATE
using the received coded information. -1.2 ROBO 0.01
On the transmitter side, the PLC modem layer receives 2.6 DBPSK 0.01
input data from the UART and passes the data through 6.1 DQPSK 0.01
the FEC, modulator, and IFFT. On the receiver side, the 9.9 D8PSK 0.01
PLC modem layer receives inputs from the AFE and
hands the data over to the application layer (Figure 5). Table 3. Receiver Specification with
Two separate signal paths are shown for the receiver.
The first path is dedicated to the detection of narrow
MAX2991
band interference, and the second path processes the RECEIVER SPECIFICATION REQUIREMENT
preamble for symbol and frame synchronization followed Sensitivity 1mV
by the FEC decoding block. After descrambling the output
Dynamic range 60dB
of the FEC decoder data are available for the MAC layer.
Clock frequency tolerance ±25ppm

OFDM MODULATOR
MAPPING
DBPSK
PREEMPHASIS IFFT ADD CP WINDOWING
DQPSK
D8PSK
FCH
INTERLEAVER
SCRAMBLER BIT AFE
REED-SOLOMON CONVOLUTIONAL
DATA ENCODER ENCODER ROBUST (RC4)
S-ROBUST (RC6)
FEC ENCODER
POWER LINE
JAMMER OFDM DEMODULATOR

CANCELLER
DETECTED
JAMMER SYNC REMOVE FFT DEMODULATOR

AFE DBPSK
DETECTOR DETECTION CP
DQPSK
NOT D8PSK
DETECTED
RMS
CHANNEL
MEASUREMENT
ESTIMATION
ROBUST4
AND VITERBI REED-SOLOMON DATA
DEINTERLEAVER
ROBUST DECODER DECODER
DESCRAMBLER
COMBINER
FCH
FEC DECODER
Figure 5. Transmitter/Receiver Block Diagram of the Baseband Processor

Absolute Maximum Ratings

VDDIO to VSS........................................................-0.5V to +4.0V Operating Temperature Range.......................... -40°C to +105°C
VDDC to VSS.........................................................-0.5V to +1.5V Junction Temperature.......................................................+125°C
VDD to VSS............................................................-0.5V to +1.5V Storage Temperature Range............................. -65°C to +150°C
XTAL1A, XTAL2A, XTAL1S, XTAL2S to VSS........-0.5V to +4.0V Lead Temperature (soldering, 10s).................................. +300°C
All I/O Pins............................................................-0.5V to +5.5V Soldering Temperature (reflow)........................................+260°C
Continuous Power Dissipation (TA = +70°C)
LQFP (derate 25mW/°C above +70°C)......................2000mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 2)

LQFP
Junction-to-Ambient Thermal Resistance (θJA)...........40°C/W Junction-to-Case Thermal Resistance (θJC)..................8°C/W
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VDDIO = +3.3V, VDDC = VDD = +1.2V, VSS = 0, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.
Specifications over the entire operating temperature range are guaranteed by design and characterization.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER-SUPPLY CHARACTERISTICS
Digital Supply Voltage Range VDDIO 3.0 3.3 3.6 V
Core Supply Voltage Range VDDC 1.14 1.2 1.32 V
PLL Supply Voltage Range VDD Pins 15 and 50 1.14 1.2 1.32 V
VDDIO supply current 25
Operating Supply Current IOPERATING VDDC supply current 40 70 mA
VDD supply current 1 3
Idle Mode Current IIDLE VDDC supply current 12 mA
VDD supply current 1
Stop Mode Current ISTOP VDDC supply current 1.8 mA
VDD supply current 0.2
IOH = -5mA 2.4
Output Voltage High VOH V
IOH = -8mA (pins 55 and 57) 2.4
IOl = 5mA 0.4
Output Voltage Low VOL V
IOl = 8mA (pins 55 and 57) 0.4
LOGIC INPUT CHARACTERISTICS
2 5.5
Input High Voltage VIH V
XTAL1S, XTAL1A 2 3.6
Input Low Voltage VIL -0.3 +0.8 V
Input Capacitance CIN XTAL1S and XTAL1A 3 pF
Input Leakage current IIN Internal pullup disabled -10 +10 µA
GPIO Pullup Resistance RPU Internal pullup enabled 25 45 60 kΩ

AC Electrical Characteristics

External Crystal/Input Frequency 1/tXTAL ESR < 90Ω for 19.2MHz (Note 4) 2 19.2 30 MHz
External Crystal/Clock Tolerance (Note 4) 25 ppm
As configured by G3-PLC firmware

CPU Clock Frequency 1/tCPU 76.8 MHz
(Note 4)
As configured by G3-PLC firmware
AFE Clock Frequency 1/tAFE 48 MHz
(Note 4)
As configured by G3-PLC firmware 1/16 x
UART Baud Rate 115,200 bps
(Notes 3 and 4) tCPU
SPI MASTER (Flash Bootloader, See Figure 6)
1/2 x
Flash boot after POR (Note 4)
tXTAL
SPI Master Operating Frequency 1/tMCK MHz
User programmable after bootstrap 1/ 2 x
(Note 4) tCPU
I/O Rise/Fall Time tMRF CL = 100pF, pullup = 560Ω 5 ns
SCLK Output Pulse Width High/ tMCH, tMCK/2
ns
Low tMCL - tRF
MOSI Output Valid to SCLK tMCK/2
tMOH MOSI setup ns
Sample Edge - tRF
MOSI Output Hold after SCLK tMCK/2
tMOV ns
Last Sample Edge - tRF
SCLK Last Sample Edge to tMCK +
tMLH MOSI last hold ns
MOSI Output Change tRF
MISO Input Valid to SCLK
tMIS MISO setup 10 ns
Sample Edge
MISO Input Hold After SCLK
tMIH 0 ns
Sample Edge
SPI SLAVE (See Figure 7)
1/8 x
SPI Slave Operating Frequency 1/tSCK (Note 4) MHz
tCPU
I/O Rise/Fall Time tSRF CL = 100pF, pullup = 560Ω 5 ns
SCLK Input Pulse Width High/ tSCH,
tCPU ns
Low tSCL
SSEL Active to First Shift Edge tSSE 0 ns
MOSI Input to SCLK Sample
tSIS tCPU ns
Edge Rise/Fall Setup

AC Electrical Characteristics (continued)


MOSI Input from SCLK Sample
tSIH tCPU ns
Edge Transition Hold
MISO Output Valid after SCLK 4x
tSOV ns
Shift Edge Transition tCPU
SSEL Inactive to Next SSEL 2x
tSSH ns
Asserted tCPU
SCLK Inactive to SSEL 3x
tSD ns
Deasserted tCPU
MISO Output Disabled After 4x
tSLH ns
SSEL Edge Deasserted tCPU
AFE INTERFACE SERIAL MODE (See Figure 8)
AFE Interface Operating
1/tTRCK (Note 5) 48 MHz
Frequency
Clock Rise/Fall Time tCRF CL = 100pF 5 ns
RXCLK/TXCLK Output Pulse tRCH, 0.4 x 0.6 x
ns
Width High/Low tRCL tTRCK tTRCK
SDI Input Setup to RXCLK Active
tRIS 6 ns
Edge
SDI Input Hold After RXCLK
tRIH 1 ns
Active Edge
RXEN/TXEN Inactive Level 0.8 x 1.2 x
tTREW tTRCK ns
Output Pulse Width tTRCK tTRCK
RXCLK/TXCLK to RXEN/TXEN
tTREDF 0 10 ns
Active
RXCLK/TXCLK to RXEN/TXEN
tTREDR 0 10 ns
Inactive
TXCLK to SDO Output tTOD 0 10 ns
Note 3: Typical values are measured at TA = +25°C, VDDC = 1.2V.
Note 4: Guaranteed by design.
Note 5: The maximum operating frequency is 20MHz when paired with the MAX2991.

SHIFT SAMPLE SHIFT SAMPLE

SSEL
(SAS = 0)
tMCK
SCLK
CKPOL/CKPHA
0/1 OR 1/0
tMCH tMCL
SCLK
CKPOL/CKPHA
0/0 OR 1/1
tMOV
tMOH
tRF tMLH
MOSI MSB MSB-1 LSB
tMIS tMIH
MISO MSB MSB-1 LSB
Figure 6. SPI Master Timing Diagram
SHIFT SAMPLE SHIFT SAMPLE
SSEL tSSE tSSH
tSCK tSD
SCLK
CKPOL/CKPHA
0/1 OR 1/0
tSCH tSCL
SCLK
CKPOL/CKPHA
0/0 OR 1/1
tSIS
tSIH
MOSI MSB MSB-1 LSB
tSOV tRF tSLH
MOSO MSB MSB-1 LSB
Figure 7. SPI Slave Timing Diagram

tTREW
TXCONV
tTREDR
tTREDF
tRCH tRCL
TXCLK
tTOD
TXDATA
tTREW
RXCONV
tTREDR
tTREDF
tRCH tRCL
RXCLK
tRIS
tRIH
RXDATA
Figure 8. AFE Timing Diagram
Applications Information External Crystal Requirements

The MAX2992 is a powerline communications device that The MAX2992 accepts crystals of various designs to set
transports information from the application layer across a the clock frequency. For example, use a crystal with a
powerline network. In a typical application, the MAX2992 maximum ESR of 1kΩ and CL of 20pF between 2MHz
is used with an external host processor that handles and 6MHz. Use a crystal with a maximum ESR of 160Ω
application layers and an IPV6 stack. For instance, in and CL of 16pF between 6MHz and 10MHz. Use a crystal
a metering application, an external host processor that with a maximum ESR of 90Ω and CL of 12pF between
is connected to the MAX2992 using the UART or SPI 10MHz and 20MHz. Use a crystal with a maximum ESR
interface processes metering data and encapsulates of 40Ω and CL of 8pF between 20MHz and 30MHz.
the processed data into IPV6 packets to be transported
over the AC line. Additionally, the host implements inter-
External Flash Requirements
face primitives to communicate to the MAX2992. These An external flash device is required for the automatic
primitives direct data transfer as well as status and control bootstrap from the external flash option (see the Boot
commands between the host and the MAX2992. Refer to Options section). The external flash supported by the
the MAX2992 G3-PLC Interface Guide for a description of MAX2992 for booting is the AT45DB021D.
the interface primitives.

Network Support When a device receives a route request message, it cal-

Depending on the application requirements, the MAX2992 culates the route cost required for the message to get to
can use various network topologies. In a star topology, it. It stores that route cost and sends on the route request
communication is established between devices and a message with the route cost it calculated. Since there
single central controller. Applications such as industrial are many devices forwarding the route request message,
control and monitoring, sensor networks, asset and inven- devices are likely to receive more than one route request
tory tracking, and security benefit from the star topology. messages to support the creation of the same route.
The redundant copies of the message have the same
The MAX2992 can also operate in a tree network topol- or higher calculated route cost. All the redundant copies
ogy where a controller communicates with devices in the are dropped. When the message forwarding is complete,
network either directly or by having messages forwarded the devices along the best path have the lowest route
by other devices in the network. Applications such as cost back to the route request originator in their memory.
metering and lighting automation benefits from the tree Figure 12 shows the route generated in bold by the route
network topology. request that makes up the best path from the requester to
The MAX2992 supports peer-to-peer mesh network the target. The lighter lines show messages that are not
topologies. In peer-to-peer mesh networks, two devices on the optimal path.
communicate with each other using other devices as for-
warders without either of the devices in the network being
a controller.
MAX2992 Routing
The MAX2992 network of devices discovers routes
among the devices in the network. A route is discovered
by a device sending a route request message. The route
request message is sent by a device when the device
does not know how to route its message to the desired
device. Every device in the network except the target
device forwards the route request message at least once.
Figure 10. Tree Network Topology
Figure 9. Star Network Topology Figure 11. Peer-to-Peer Network Topology

When the route request message reaches the target cost back to the requester in their memory. Each device
device, it broadcasts a route reply message. This mes- updates its routing table with the path that is the lowest
sage includes the lowest route cost from the requestor route cost from the target. Figure 13 shows the route
it received. Other devices update the message and reply messages generated in this example. The MAX2992
rebroadcast it if the route reply message contains a builds an optimal route from device A to device B.
route cost from the requester that is more than the route
A B A B
Figure 12. Route Request Message Flow Figure 13. Route Reply Message Flow

Ordering Information (continued) Package Information

PART TEMP RANGE PIN-PACKAGE For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
MAX2992ECB+T -40°C to +85°C 64 LQFP that a “+”, “#”, or “-” in the package code indicates RoHS status
MAX2992GCB+ -40°C to +85°C 64 LQFP only. Package drawings may show a different suffix character, but
MAX2992GCB+T -40°C to +85°C 64 LQFP the drawing pertains to the package regardless of RoHS status.
+Denotes lead(Pb)-free/RoHS-compliant package. PACKAGE PACKAGE OUTLINE LAND
T = Tape and reel.
TYPE CODE NO. PATTERN NO.
64 LQPF C64-8 21-0083 90-0141
Chip Information
PROCESS: CMOS

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 3/11 Initial release —
Updated General Description, Benefits and Features, Ordering Information, Pin
1, 11,
1 4/14 Description, Electrical Characteristics table, AC Electrical Characteristics table
18, 20, 21
sections and Table 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2014 Maxim Integrated Products, Inc. │ 28

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MAX2992 G3-PLC MAC/PHY Powerline Transceiver

Benefits and Features General Description

19-5812; Rev 1; 4/14

Typical Application Circuit

HOST MCU Tx BLOCK

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TABLE OF CONTENTS (CONTINUED)

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SCK SO SI CS PROG TXDO RXDO TXD1 RXD1

SECURITY KEYS AES CCM

CLOCK DOMAIN BOUNDARY

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P3.2/TXCLK 55 MAX2992 26 P1.4/FSH_SCK

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Pin Description (continued)

P0.2/AFE_SDOUT. P0.2/AFE_SDOUT is used by the MAX2992 G3-PLC firmware

P0.3/AFE_SCLK. P0.3/AFE_SCLK is used by MAX2992 G3-PLC firmware to

P0.4/COL. P0.4/COL is used by the MAX2992 G3-PLC firmware to indicate modem

P0.5/ACT. P0.5/ACT is used by the MAX2992 G3-PLC firmware to indicate modem

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Pin Description (continued)

P0.6/RDY. P0.6/RDY is used by the MAX2992 G3-PLC firmware to indicate modem

P0.7/PULSE. P0.7/PULSE is used by the MAX2992 G3-PLC firmware to input pulses

P1.1/RXD0. P1.1/RXD0 provides connections to dedicated UART hardware. This is

P1.4/FSH_SCK. P1.4/FSH_SCK provides dedicated connections to the SPI hardware,

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Pin Description (continued)

P1.5/FSH_SI. P1.5/FSH_SI provides dedicated connections to the SPI hardware, and

P1.6/FSH_SO. P1.6/FSH_SO provides dedicated connections to the SPI hardware,

P2.7. P2.7 is not used by the MAX2992 G3-PLC firmware. It is configured as an

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Pin Description (continued)

P2.6. P2.6 is not used by the MAX2992 G3-PLC firmware. It is configured as an

P2.5/CS. P2.5/CS provides dedicated connections to SPI hardware. This is used by

P2.4/AFE_SHDN. P2.4/AFE_SHDN is used by the MAX2992 G3-PLC firmware to

P2.3/SO. P2.3/SO provides dedicated connections to SPI hardware. This is used by

P2.2/AGC_FRZ. P2.2/AGC_FRZ provides dedicated connections to the PHY

P2.0/SCK. P2.0/SCK provides dedicated connections to SPI hardware. This is used

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Pin Description (continued)

P3.1/TXDATA. P3.1/TXDATA provides dedicated connections to AFE interface hardware.

P3.2/TXCLK. P3.2/TXCLK provides dedicated connections to AFE interface

P3.3/RXCLK. P3.3/RXCLK provides dedicated connections to AFE interface

P3.4/RXDATA. P3.4/RXDATA provides dedicated connections to AFE interface

P3.5/RXCONV. P3.5/RXCONV provides dedicated connections to AFE interface

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Typical Operating Characteristics

G3-PLC DATA RATE* G3-PLC DATA RATE* G3-PLC DATA RATE*

D8PSK (TYP) D8PSK (TYP) D8PSK (TYP)

DQPSK (TYP) DQPSK (TYP) DQPSK (TYP)

DBPSK (TYP) DBPSK (TYP) DBPSK (TYP)

ROBO (TYP) ROBO (TYP) ROBO (TYP)

Detailed Description provides advanced CSMA/CA and ARQ functions and

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crystal connected between XTAL1S and XTAL2S. Drive

a 1.2MHz sample rate. RXCONV P3.5/RXCONV

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