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978-1-107-03041-1 - Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs

Jerry G. Fossum and Vishal P. Trivedi
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Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs

Understand the theory, design, and applications of the two principal candidates for the
next mainstream semiconductor-industry device with this concise and clear guide to FD/
UTB transistors.
This book
* Describes FD/SOI MOSFETs and 3-D FinFETs in detail

* Covers short-channel effects, quantum-mechanical effects, and applications of UTB

devices to floating-body DRAM and conventional SRAM

* Provides design criteria for nanoscale FinFET and nanoscale thin- and thick-BOX

planar FD/SOI MOSFET to help reduce technology development time

* Projects potential nanoscale UTB CMOS performances

* Contains end-of-chapter exercises

For professional engineers in the CMOS IC field who need to know about optimal
nonclassical device design and integration, this is a must-have resource.

Jerry G. Fossum is Distinguished Professor Emeritus of Electrical and Computer

Engineering at the University of Florida, Gainesville, and a Fellow of the IEEE. He
won the IEEE/EDS J. J. Ebers Award in 2004 for “outstanding contributions to the
advancement of SOI CMOS devices and circuits through modeling.”
Vishal P. Trivedi is a Member of the Technical Staff and a Distinguished Innovator at
Freescale Semiconductor, Inc., and a Senior Member of the IEEE.

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Jerry G. Fossum and Vishal P. Trivedi
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“The future of CMOS technology lies in replacing the classical, bulk MOSFET with
new transistor structures such as the FinFET and ultra-thin body MOSFET. Those
with a solid background in classical MOS device theory will find here an authoritative
and comprehensive treatment of the final frontier in CMOS technology.”
Mark Lundstrom, Don and Carol Scifres Distinguished Professor of Electrical and
Computer Engineering, Purdue University

“A valuable volume on the design and modeling of silicon-on-insulator and multiple-gate

MOSFETs by a pioneer and expert on the subject.”
Yuan Taur, University of California at San Diego

“This is precisely the book everybody in the advanced nano-CMOS world wanted to see
out ASAP. Timely, brilliant and most useful - written by a Master (VT) and his own
former Master (JF). A life experience is condensed and distilled to provide the necessary
ingredients needed for understanding the physics mechanisms and for pursuing with
transistor modeling and circuit design. The book is primarily addressed to specialists,
engineers and graduate students. This is not a romantic novel about SOI and FinFET
affair; it is solid stuff where advanced concepts, strong affirmations and lots of practical
equations do not leave space for scientific dust.”
Sorin Cristoloveanu, CNRS, Grenoble, France

“This is a timely book about SOI MOSFETs and FinFETs written by one of the leading
authorities in the field and his former student. Since FinFETs have started being imple-
mented by various companies in production, there is a need for clear understanding of the
design trade-offs of such devices. Prof. Fossum, who has done seminal work on model-
ing SOI MOSFETs since the 1980s, provides a clear elucidation of the physics of these
devices. Graduate students, faculty and industrial practitioners should benefit from the
pedagogy in this book.”
Sanjay Banerjee, University of Texas at Austin

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978-1-107-03041-1 - Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs
Jerry G. Fossum and Vishal P. Trivedi
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Fundamentals of Ultra-Thin-Body
MOSFETs and FinFETs
JERRY G. FOSSUM
University of Florida, Gainesville

VISHAL P. TRIVEDI
Freescale Semiconductor, Arizona

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Jerry G. Fossum and Vishal P. Trivedi
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University Printing House, Cambridge CB2 8BS, United Kingdom

Published in the United States of America by Cambridge University Press, New York
Cambridge University Press is part of the University of Cambridge.
It furthers the University’s mission by disseminating knowledge in the pursuit of
education, learning, and research at the highest international levels of excellence.

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© Cambridge University Press 2013
This publication is in copyright. Subject to statutory exception
and to the provisions of relevant collective licensing agreements,
no reproduction of any part may take place without the written
permission of Cambridge University Press.
First published 2013
Printing in the United Kingdom by TJ International Ltd. Padstow Cornwall
A catalog record for this publication is available from the British Library
Library of Congress Cataloging in Publication data
Fossum, Jerry G., 1943–
Fundamentals of ultra-thin-body MOSFETs and FinFETs / Jerry G. Fossum, Vishal
P. Trivedi.
pages cm
ISBN 978-1-107-03041-1 (hardback)
1. Metal oxide semiconductor field-effect transistors. 2. Integrated circuits – Very large scale
integration. I. Title.
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Contents

Preface page vii

Table of physical constants ix
List of symbols x
List of acronyms xv

1 Introduction 1
1.1 Ultimate nanoscale CMOS 3
1.1.1 Planar FD/SOI MOSFET 5
1.1.2 FinFET 5
1.2 Brief overview of the book 9

2 Unique features of UTB MOSFETs 13

2.1 Long-channel threshold voltage 15
2.1.1 The depletion approximation 15
2.1.2 Review of the classical charge-coupling model 16
2.1.3 Nonclassical model 17
2.1.4 Applications 22
2.1.5 Generalized charge coupling 23
2.2 Quantum-mechanical effects on Vt 25
2.3 Short-channel effects on Vt 31
2.3.1 Modeling 31
2.3.2 SCE control 33
2.4 Random-dopant effect on Vt 35
2.5 Adjustment of Vt 36
2.5.1 S/D doping-dependent Vt 37
2.5.2 Sensitivity and RDF analyses 41
2.6 Current–voltage characteristics 42
2.6.1 Classical current formalism with bulk inversion 42
2.6.2 Quantization and 2-D density of states 53
2.6.3 Bulk-inversion effects 63
2.6.4 Carrier mobility 67
2.7 Gate-source/drain underlap 78
2.7.1 Effective channel length 78
2.7.2 Impact of S/D doping profile 84

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vi Contents

2.7.3 Insights from optimized 18 nm DG FinFETs 87

2.7.4 Fringe capacitance 89
2.8 Charge/capacitance dynamics 93
2.9 Floating-body effects 94
2.9.1 Transient BJT effect 95
2.9.2 FD/UTB floating-body DRAM 96
Exercises 100

3 Planar fully depleted SOI MOSFETs 103

3.1 Why thin BOX? 103
3.1.1 Field fringing in thick BOX 104
3.1.2 Benefits of BOX-thickness scaling 106
3.1.3 Challenges with thin BOX 107
3.2 Basic analyses of scaling and design 109
3.2.1 2-D effects in the UTB 109
3.2.2 Vt control via UTB doping? 115
3.2.3 Vt and SCE control with gate work-function engineering 116
3.3 Insights on design and scalability with thin BOX 120
3.3.1 Thin-BOX FD/SOI CMOS design space 121
3.3.2 LP versus HP design 124
3.3.3 General insights on GP/bias design for variable Vt 132
Exercises 136

4 FinFETs 138
4.1 Triple- or double-gate? 138
4.1.1 Effects of fin-UTB doping 139
4.1.2 Effects of bulk inversion 141
4.1.3 The pragmatic choice 149
4.2 DG FinFETs 149
4.2.1 Bulk Si versus SOI 150
4.2.2 SDG versus ADG 154
4.2.3 Potential speed superiority 160
4.2.4 Pragmatic FinFET design 165
4.3 The ITFET: a hybrid option 171
4.4 Independent-gate FinFET 173
4.5 SRAM application 176
4.5.1 Vt modulation via underlap 176
4.5.2 Cell design and performance 179
Exercises 186

Appendix UFDG 188

References 200
Index 208

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Preface

The computer revolution (i.e., faster, smaller, and cheaper computers), and the technol-
ogies it has enabled (e.g., the Internet, laptops, smart phones), have been driven by
continued size-scaling of the CMOS transistors in the constituent integrated circuits (ICs,
e.g., the microprocessor) of the computer. This scaling, which has doubled the transistor
density on the CMOS IC chip about every two years, has been achieved by simply
ratioing the dimensions and related parameters of the basic, classical transistor structure
(i.e., the planar single-gate MOSFET in bulk silicon or partially depleted SOI) (Taur and
Ning, 2009) as improvements in lithography enabled reduced minimum feature size. The
CMOS devices have now become so small (e.g., gate lengths are 30–40 nm) that this
straightforward scaling is no longer possible, mainly because of fundamental limitations
in reliable doping of the classical MOSFET. Thus, continued CMOS scaling will require
a new, nonclassical transistor structure with ultra-thin body (UTB) that avoids these
limitations. The first concrete evidence of the transition to a UTB transistor structure is
Intel Corporation’s adoption of the “trigate transistor” (or FinFET) (Auth et al., 2012) for
22 nm CMOS technology and beyond.
This book details the fundamental physics of silicon-based UTB MOSFETs,
overviews their designs, with links to the process integration, and projects potential
nanoscale UTB-CMOS performance. The presentations are facilitated by the
authors’ process/physics-based compact model for double-gate MOSFETs, UFDG
(Appendix). This book is suitable as a textbook for a one-semester graduate or senior-
undergraduate university course, as well as for a fundamental guide to optimal non-
classical device design and integration for professional engineers in the CMOS IC field.
The prerequisites are good backgrounds in basic semiconductor device physics (e.g.,
as in Sze and Ng (2007)) and in fundamentals of classical bulk-Si MOSFETs (Taur
and Ning, 2009). In fact, this book is intended to be a supplementary text for the
latter book.
The authors acknowledge the SOI-related works of many colleagues, which provided
the bases of much of this book. Special thanks are given to Professor Fossum’s former
Ph.D. students who so contributed: Shishir Agrawal, Duckhyun Chang, Meng-Hsueh
Chiang, Jin-Young Choi, Siddharth Chouksey, Murshed Chowdhury, Lixin Ge,
Keunwoo Kim, Seung-Hwan Kim, Srinath Krishnan, Hyung-Kyu Lim, Zhichao Lu,
Mario Pelella, Dongwook Suh, Surya Veeraraghavan, Glenn Workman, Ji-Woon Yang,
Ping Yeh, Weimin Zhang, and Zhenming Zhou; and to Leo Mathew who has provided us

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viii Preface

“theoretical guys” with invaluable technological insights for so many years. We also
thank Malgorzata Jurczak and imec for providing the microscopy images on the front and
back covers of the book.
We are also grateful to our families. Professor Fossum especially thanks his wife, Mary
Fossum, for unrelenting support of his “SOI obsessions.” Dr. Trivedi especially thanks
his parents (Pareexit and Hansa Trivedi), brother (Vaibhav), sister-in-law (Krushangi),
and niece (Eesha) for their constant love, care, and support.

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Physical constants

Description Symbol Value and unit

Electronic charge q 1.6 × 10–19 C

Boltzmann’s constant k 1.38 × 10–23 J/K
Vacuum permittivity ε0 8.85 × 10–14 F/cm
Silicon permittivity εSi 1.04 × 10–12 F/cm
Oxide permittivity εox 3.45 × 10–13 F/cm
Si3N4 (spacer) permittivity εsp 6.64 × 10–13 F/cm
Planck’s constant h 6.63 × 10–34 J-s
Free-electron mass m0 9.1 × 10–31 kg
Thermal voltage (T = 300 K) kT/q 0.0259 V
Silicon electron affinity χSi 4.05 eV
Silicon bandgap Eg(Si) 1.12 eV
Silicon intrinsic carrier concentration (T = 300 K) ni 1.33 × 1010 cm−3
Silicon effective density of states in conduction band (T = 300 K) Nc ~2.8 × 1019 cm−3
Silicon effective density of states in valence band (T = 300 K) Nv ~1.0 × 1019 cm−3

Note the values (at T = 300 K) listed for ni, Nc, and Nv. There is inconsistency in the
archival literature among these constants. The given value for ni, which is lower than
commonly presumed (Taur and Ning, 2009), was taken from unpublished measurements
done by C. T. Sah et al. in 1974 at the University of Illinois; correspondingly, Eg(Si) was
measured at 1.12 eV, which is the commonly accepted value. The given values for Nc and
Nv, which are common, are indicated to be crude approximations because they are not
consistent with ni and Eg(Si) in the parabolic band-based expression for ni(Eg, Nc, Nv, T)
(Taur and Ning, 2009).

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Symbols

af FinFET fin aspect ratio

β coefficient for surface-roughness-limited mobility model V3/cm3-s
β term in Cifw model radian
bj variational parameter of jth subband
b0 variational parameter of ground-state subband
χSi electron affinity eV
Cb body capacitance (per unit area) F/cm2
CB composite body capacitance F
Cb(eff) effective body capacitance (per unit area) F/cm2
Cbf BOX fringe capacitance (per unit width) F/cm
Cd depletion capacitance (per unit area) F/cm2
CG MOSFET gate capacitance (per unit area) F/cm2
Ci inversion-layer capacitance (per unit area) F/cm2
Cif inner-fringe capacitance (per unit width) F/cm
Cof outer-fringe capacitance (per unit width) F/cm
Cox gate-oxide capacitance (per unit area) F/cm2
Coxb back-gate oxide capacitance (per unit area) F/cm2
Coxf front-gate oxide capacitance (per unit area) F/cm2
CS/D source/drain-junction capacitance (per unit area) F/cm2
Δϕ0 drain bias-induced increase in channel potential V
Δϕ0(sb) drain bias-induced increase in back-surface potential V
Δϕ0(sf) drain bias-induced increase in front-surface potential V
Δϕ1(max) increase in leakiest source-drain “surface” potential V
Δϕ1(sb) SCE-induced change in back-surface potential V
Δϕ1(sf) SCE-induced change in front-surface potential V
ΔΦGf difference in front-gate work function relative to midgap eV
ΔϕQM change in channel potential due to quantization V
DϕQMsf change in front-surface potential due to quantization V
DIBL drain-induced barrier lowering mV/V
DQDICE
i DICE-induced change in inversion (channel) charge density C/cm2
ΔrQM change in charge-coupling factor due to QMEs
ΔrSCE change in charge-coupling factor due to SCEs
ΔVOS offset voltage between front and back bias V
ΔVta change in Vta due to stored charge in the body V
DVQM t Vt shift due to QMEs V
DVSCEt Vt shift due to SCEs V
Δzj over-diffusion of source/drain junction in bulk FinFET nm
E0 ground-state energy J
Ec Conduction-band-edge energy J
Eeff effective transverse electric field V/cm

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List of symbols xi

EF Fermi energy level J

Eg energy bandgap J
εhk permittivity of high-k dielectric F/cm
Ei intrinsic Fermi level J
Ej jth-subband energy in unprimed valley J
E0j jth-subband energy in primed valley J
Ej〈kin〉 kinetic energy of carriers in jth subband J
Ej〈pot〉 potential energy of carriers in jth subband J
εox oxide permittivity F/cm
εSi silicon permittivity F/cm
Ev valence-band-edge energy J
Ex transverse electric field V/cm
Exc weak-inversion (constant) transverse field in UTB V/cm
Exsb transverse electric field at back surface V/cm
Exsf transverse electric field at front surface V/cm
Ey lateral electric field V/cm
Ey0 lateral electric field at virtual source at back surface V/cm
ϕ UTB potential V
ϕ0(max) potential at the leakiest source-drain “surface” V
ϕ1 long-channel potential V
ϕB Fermi potential of the body V
ϕc band bending necessary for inversion/accumulation V
ϕCL classical channel potential V
ΦGb back-gate work function eV
ΦGbS back gate-body work-function difference eV
ΦGf front-gate work function eV
ΦGfS front-gate-body work-function difference eV
fLO LO frequency MHz
ΦMS gate-body work-function difference eV
ϕQM quantum-mechanical channel potential V
fRF RF frequency MHz
ϕsb back-surface potential V
ϕsf front-surface potential V
ϕtsf front-surface potential at threshold V
γ degree of carrier occupation of higher subband energies
γ proportionality constant for SCE-impact on BOX field fringing
g degeneracy of unprimed valley
g0 degeneracy of primed valley
h Planck’s constant J-s
hSi fin height of FinFET nm
IBJT parasitic-BJT current A
IDS(sat) MOSFET saturation current (per unit width) A/μm
IG generation current in the body A
IGi impact-ionization-based generation current A
Ioff MOSFET off-state current (per unit width) A/μm
Ion MOSFET on-state current (per unit width) A/μm
IR recombination current in the body A
k Boltzmann constant J/K
k dielectric constant of high-k dielectric
κ proportionality constant for VDS-impact on BOX field fringing
λ MOSFET scale/natural length nm

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xii List of symbols

LD Debye length nm
Le effective channel length with modulation nm
LeD gate-drain underlap nm
Leff effective channel length nm
Leff(strong) strong-inversion effective channel length nm
Leff(weak) weak-inversion effective channel length nm
LeS gate-source underlap nm
LeSD gate-source/drain underlap nm
Lext source/drain extension length nm
Lg MOSFET gate length nm
Lgch MOSFET gradual-channel length nm
Lmet MOSFET metallurgical channel length nm
Ls location of virtual source nm
m0 free-electron mass kg
md density-of-states effective mass kg
mx effective mass in confinement direction kg
mx〈100〉 mx along {100}-Si surface kg
mx〈110〉 mx along {110}-Si surface kg
μco Coulomb-limited carrier mobility cm2/V-s
μeff effective carrier mobility cm2/V-s
μmax maximum saturation value of μph cm2/V-s
μmin minimum saturation value of μph cm2/V-s
μ0 constant low-field carrier mobility cm2/V-s
μph phonon-limited carrier mobility cm2/V-s
μph(bulk) bulk-phonon carrier mobility cm2/V-s
μsr surface-roughness-limited carrier mobility cm2/V-s
n electron concentration cm−3
NAL punch-through-stop doping density cm−3
NB doping density in the body cm−3
Nc effective density of states in conduction band cm−3
ni intrinsic carrier concentration cm−3
Ninv inversion-carrier density cm−2
Nj inversion-carrier density (per unit area) in jth subband cm−2
NSD source/drain doping density cm−3
Nv effective density of states in valence band cm−3
p hole concentration cm−3
P fin pitch nm
q electron charge C
Qa accumulation charge density (per unit area) C/cm2
Qb depletion-charge density in body (per unit area) C/cm2
QB body terminal charge C
QD drain terminal charge C
QGb back-gate terminal charge C
QGf front-gate terminal charge C
Qi inversion-charge density (per unit area) C/cm2
Qi0 inversion-charge density at VDS = 0 V C/cm2
Qib bulk component of inversion-charge density C/cm2
QCLi classical inversion-charge density C/cm2
QQMi quantum-mechanical inversion-charge density C/cm2
Qis surface component of inversion-charge density C/cm2
QS source terminal charge C

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List of symbols xiii

r UTB-MOSFET charge-coupling factor

ra charge-coupling factor for accumulated body
reff effective charge-coupling factor
Rext extrinsic source/drain resistance Ω
RSD extrinsic source/drain series resistance Ω
S inverse subthreshold slope (gate swing) mV/dec
σL lateral straggle of source/drain doping profile nm
σV vertical straggle of PTS doping profile nm
T temperature K
tBOX BOX thickness of SOI MOSFETs nm
tg gate height nm
thk thickness of high-k dielectric nm
tox gate-oxide thickness nm
toxb back-gate oxide thickness nm
toxf front-gate oxide thickness nm
τpd propagation delay ps
tSi UTB thickness nm
v carrier velocity cm/s
vb average carrier velocity in fin bulk cm/s
Vbi built-in junction potential V
VBS body-source voltage V
VDD supply voltage V
VDS drain-source voltage V
VDS(eff) effective drain-source voltage at end of gradual channel V
VDS(sat) MOSEFT drain saturation voltage V
VFB flat-band voltage V
VFBb back-gate flat-band voltage V
VFBf front-gate flat-band voltage V
VGb back-gate voltage V
VA Gb onset VGB for back accumulation in UTB V
VBIGb onset VGB for predominant bulk inversion in UTB V
VIGB onset VGB for back inversion in UTB V
VGbS(eff) effective back-gate voltage due to BOX field fringing V
VGf front-gate voltage V
VGP ground-plane voltage V
VGS gate-source voltage V
vs average carrier velocity at fin surfaces cm/s
vsat saturation velocity of carriers cm/s
vsat(eff) effective saturation velocity of carriers cm/s
Vt threshold voltage V
Vt(ADG) threshold voltage of ADG MOSFET V
Vt(SDG) threshold voltage of SDG MOSFET V
Vt(thickBOX) threshold voltage of FD/SOI MOSFET with thick BOX V
Vt(thinBOX) threshold voltage of FD/SOI MOSFET with thin BOX V
VA t UTB-MOSFET Vt for accumulated back surface V
Vtf threshold voltage of front surface V
Vts strong-inversion threshold voltage V
Vtw weak-inversion threshold voltage V
Weff MOSFET effective width nm
Weff(DG) effective gate width of DG FinFET nm
Weff(TG) effective gate width of TG FinFET nm

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xiv List of symbols

Wg gate width nm
wSi fin width of FinFET nm
xav average inversion-carrier depth nm
xc inversion-charge centroid nm
ψ carrier wave function (1-D) nm−1/2
ψj carrier wave function in jth subband (1-D) nm−1/2

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Acronyms

ADG asymmetrical double-gate

BJT bipolar junction transistor
BOX buried oxide (in SOI structure)
CMOS complementary MOS
DG double-gate
DIBL drain-induced barrier lowering
DICE drain-induced charge enhancement
DOS density of (quantum) states
DRAM dynamic random-access memory
EOT effective gate-oxide thickness
FD fully depleted
GIDL gate-induced drain leakage
GP ground plane
HP high performance
IC integrated circuit
IGFET independent-gate (DG) MOSFET
ITFET inverted-T (hybrid) field-effect transistor
ITRS International Technology Roadmap for Semiconductors
LP low power
LSTP low standby power
MOS metal (gate)-oxide (insulator)-semiconductor
MOSFET MOS field-effect transistor
MPU micro-processing unit
PD partially depleted
PE Poisson’s equation
PTS punch-through stopping
QME quantum-mechanical effect
QSA quasi-static approximation
RDF random dopant fluctuation
SCE short-channel effect
SDE source/drain extension
SDG symmetrical double-gate
SG single-gate

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xvi List of acronyms

SIA Semiconductor Industry Association

SNM static noise margin
SOI silicon-on-insulator
SRAM static random-access memory
TG triple-gate
UTB ultra-thin body
VLSI very large-scale integration

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