Computer Architecture - Notes2
Computer Architecture - Notes2
com
Following the saying that it can be better to ask for forgiveness than to ask for
permission, the next great idea is prediction. In some cases it can be faster on
average to guess and start working rather than wait until you know for sure,
assuming that the mechanism to recover from a misprediction is not too
www.BrainKart.com
7. Hierarchy of memories
Touchscreen
While PCs also use LCD displays, the tablets and smartphones of the PostPC
era have replaced the keyboard and mouse with touch sensitive displays, which has
the wonderful user interface advantage of users pointing directly what they are
interested in rather than indirectly with a mouse. While there are a variety of ways to
implement a touch screen, many tablets today use capacitive sensing. Since people
are electrical conductors, if an insulator like glass is covered with a transparent
conductor, touching distorts the electrostatic fi eld of the screen, which results in a
change in capacitance. Th is technology can allow multiple touches simultaneously,
which allows gestures that can lead to attractive user interfaces.
of 1 GHz. Th e processor is the active part of the computer, following the instructions
of a program to the letter. It adds numbers, tests numbers, signals I/O devices to
activate, and so on. Occasionally, people call the processor the CPU, for the more
bureaucratic-sounding central processor unit.
Cache memory
Itconsists of a small, fast memory that acts as a buff er for the DRAM memory. (Th e
nontechnical defi nition of cache is a safe place for hiding things.) Cache is built using
a diff erent memory technology, static random access memory (SRAM). SRAM is faster
but less dense, and hence more expensive, than DRAM (see Chapter 5). SRAM and
DRAM are two layers of the memory hierarchy.
Transistors fall in the last category. A VLSI circuit, then, is just billions of
combinations of conductors, insulators, and switches manufactured in a single
small package.aluminum wire)
www.BrainKart.com
Performance
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
The power limit has forced a dramatic change in the design of microprocessors.
Figure 1.17 shows the improvement in response time of programs for desktop
microprocessors over time. Since 2002, the rate has slowed from a factor of 1.5 per
year to a factor of 1.2 per year.
Rather than continuing to decrease the response time of a single program
running on the single processor, as of 2006 all desktop and server companies are
shipping microprocessors with multiple processors per chip, where the benefit is oft
en more on throughput than on response time. To reduce confusion between the
words processor and microprocessor, companies refer to processors as “cores,” and
such microprocessors are generically called multicore microprocessors.
Hence, a “quadcore” microprocessor is a chip that contains four processors or
four cores. In the past, programmers could rely on innovations in hardware,
architecture, and compilers to double performance of their programs every 18 months
without having to change a line of code. Today, for programmers to get significant
improvement in response time, they need to rewrite their programs to take advantage
of multiple processors. Moreover, to get the historic benefit of running faster on new
microprocessors, programmers will have to continue to improve performance of their
code as the number of cores increases.
To reinforce how the soft ware and hardware systems work hand in hand, we
use a special section, Hardware/Soft ware Interface, throughout the book, with the
first one appearing below. These elements summarize important insights at this
critical interface.
www.BrainKart.com
www.BrainKart.com
This notation is rigid in that each MIPS arithmetic instruction performs only one
operation and must always have exactly three variables. For example, suppose we
want to place the sum of four variables b, c, d, and e into variable a. (In this section
we are being deliberately vague about what a “variable” is; in the next section we’ll
explain in detail.)
A very large number of registers may increase the clock cycle time simply
because it takes electronic signals longer when they must travel farther. Guidelines
such as “smaller is faster” are not absolutes; 31 registers may not be faster than 32.
Yet, the truth behind such observations causes computer designers to take them
seriously. In this case, the designer must balance the craving of programs for more
registers with the designer’s desire to keep the clock cycle fast. Another reason for
not using more than 32 is the number of bits it would take in the instruction format,
as Section 2.5 demonstrates.
www.BrainKart.com
www.BrainKart.com
Logical Operations
Although the first computers operated on full words, it soon became clear that
it was useful to operate on fields of bits within a word or even on individual bits.
Examining characters within a word, each of which is stored as 8 bits, is one example
of such an operation (see Section 2.9). It follows that operations were added to
programming languages and instruction set architectures to simplify, among other
things, the packing and unpacking of bits into words. Th ese instructions are called
logical operations. Figure 2.8 shows logical operations in C, Java, and MIPS.
www.BrainKart.com
www.BrainKart.com
The first class of such operations is called shift s. They move all the bits in a word to
the left or right, filling the emptied bits with 0s. For example, if register $s0 contained
and the instruction to shift left by 4 was executed, the new value would be:
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
Although keeping all MIPS instructions 32 bits long simplifi es the hardware,
there are times where it would be convenient to have a 32-bit constant or 32-bit
address. Th is section starts with the general solution for large constants, and then
shows the optimizations for instruction addresses used in branches and jumps.
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
5. Pseudodirect addressing, where the jump address is the 26 bits of the instruction
concatenated with the upper bits of the PC
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
Building a Datapath
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
An Overview of Pipelining
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
Control Hazards
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
Exceptions
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
UNIT IV PARALLELISM
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
Memory hierarchy
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
Memory technologies
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
Virtual Memory
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com
www.BrainKart.com