Lab7 DLD Final
Lab7 DLD Final
Lab7 DLD Final
EE-272L
Lab # 7 Manual
Roll No
Marks Obtained
Date Performed
2. Learning Outcomes
This lab satisfies the following learning outcomes of the course:
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Fall 2023 DLD Lab 07 Version 2.0
5. Introduction
BCD and Grey codes are the binary codes of decimal numbers where each digit is represented by fixed
number of bits. In this lab students will perform 3 lab experiments. In the first task students will use SSD
(7-segment) decoder to display the decimal digits which were represented by fixed number of bits. This
schematic will be displayed on Proteus.
In the second task students will design a circuit to convert 4 bit grey code to binary number and will display
the BCD and Grey code on two SSDs. This circuit will be implemented on hardware.
Third task is based on error checking. In this task students will design a system that will check for any error
in the BCD. 9‘s complement will be used for error detection and logic 1 and logic 0 will highlight the errors
if any.
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Fall 2023 DLD Lab 07 Version 2.0
• The common cathode display (CCD): In the common cathode display, all the cathode connections
of the LEDs are joined together to logic “0” or ground. The individual segments are illuminated by
application of a “HIGH”, logic “1” signal to the individual Anode terminals.
• The common anode display (CAD): In the common anode display, all the anode connections of the
LEDs are joined together to logic “1” and the individual segments are illuminated by connecting the
individual Cathode terminals to a “LOW”, logic “0” signal.
So in order to display the number 3 for example, segments a, b, c, d and g needs to be illuminated. A truth
table showing which segments needs to be illuminated is given in Table 3 where “x” denotes which of the
segment is to be highlighted. Whether they are highlighted by applying logic “1” or “0” depends on their
type.
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Fall 2023 DLD Lab 07 Version 2.0
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6. Procedure
1. Based on Table 2, design a combinational circuit with 4 inputs and 4 outputs that converts a four-bit gray
code number into an equivalent four-bit binary number. Use Karnaugh map technique for simplification.
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Fall 2023 DLD Lab 07 Version 2.0
2. Implement it on trainer board. Show all the working and use two 7-segment displays on the trainer board
to display both the binary and gray code number.
3. Why does the 7-segment display displays alphabets instead of numbers beyond 9?
Note: The two 7-segment displays on the trainer board only requires 4-inputs. It has a built in decoder.
The output of gray code can be directly applied to the inputs of the 7-segment display on the trainer
board.
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Fall 2023 DLD Lab 07 Version 2.0
6.2 Task 2 Using the above combinational circuit from part 1, Write the Verilog code and verify it.
1. Implement a system which takes in a four-bit input signal in BCD format and outputs its 9’s complement
using Verilog. Provide a fifth output that detects an error in the input BCD number. This output should be
equal to logic 1 when the four inputs have one of the unused combinations of the BCD code. In such a case,
the four bit 9’s complement number shall be pulled high (in the Z state). For e.g., if the input to such a
system is 0010, then the output shall be 0111 with the error signal equal to logic “0”. However, if the input
is 1100, then the output shall be ZZZZ and the error signal will be equal to logic “1”.
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Lab Rubrics
Marking Rubric