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    Ec3352 - Digital Systems Design Set I - Iat2

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    venki08
    This document contains an internal assessment test for a Digital Systems Design course. The test assesses students on designing combinational digital circuits using logic gates and analyzing and designing asynchronous sequential circuits. It contains 3 parts - Part A has 5 short answer questions worth 2 marks each, Part B has 2 long answer questions worth 13 marks each, and Part C has 1 long answer question worth 14 marks. The questions cover topics like combinational circuits, full adders, multiplexers, latches, flip-flops, registers, parity generators, encoders, multiplexers, and look ahead carry adders.

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    Ec3352 - Digital Systems Design Set I - Iat2

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    venki08
    57 views2 pages
    This document contains an internal assessment test for a Digital Systems Design course. The test assesses students on designing combinational digital circuits using logic gates and analyzing and designing asynchronous sequential circuits. It contains 3 parts - Part A has 5 short answer questions worth 2 marks each, Part B has 2 long answer questions worth 13 marks each, and Part C has 1 long answer question worth 14 marks. The questions cover topics like combinational circuits, full adders, multiplexers, latches, flip-flops, registers, parity generators, encoders, multiplexers, and look ahead carry adders.

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    EC3352- DIGITAL SYSTEMS DESIGN SET I - IAT2[1]

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    This document contains an internal assessment test for a Digital Systems Design course. The test assesses students on designing combinational digital circuits using logic gates and analyzing and designing asynchronous sequential circuits. It contains 3 parts - Part A has 5 short answer questions worth 2 marks each, Part B has 2 long answer questions worth 13 marks each, and Part C has 1 long answer question worth 14 marks. The questions cover topics like combinational circuits, full adders, multiplexers, latches, flip-flops, registers, parity generators, encoders, multiplexers, and look ahead carry adders.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    57 views2 pages

    Ec3352 - Digital Systems Design Set I - Iat2

    Uploaded by

    venki08
    This document contains an internal assessment test for a Digital Systems Design course. The test assesses students on designing combinational digital circuits using logic gates and analyzing and designing asynchronous sequential circuits. It contains 3 parts - Part A has 5 short answer questions worth 2 marks each, Part B has 2 long answer questions worth 13 marks each, and Part C has 1 long answer question worth 14 marks. The questions cover topics like combinational circuits, full adders, multiplexers, latches, flip-flops, registers, parity generators, encoders, multiplexers, and look ahead carry adders.

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    DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

    INTERNAL ASSESMENT TEST –II (SET I)


    SUBJECT CODE/NAME : EC3352 DIGITAL SYSTEMS DESIGN DATE :
    BRANCH / SEMESTER : II ECE / III TIME :
    ACADEMIC YEAR : 2023-24 MARK : 50
    CO2: Design various combinational digital circuits using logic gates.
    CO3: Analyse and design asynchronous sequential circuits.
    BLOOM'S TAXONOMY
    Remembering Applying Evaluating
    Understanding Analyzing Creating

    PART A (5 x 2 = 10 marks)
    CO2 R 1. Define Combinational Circuits? (2)
    CO2 U 2. What is a Full Adder? (2)
    CO2 R 3. List out the various applications of Multiplexer? (2)
    CO3 U 4. Differentiate Flipflop & Latches (2)
    CO3 C 5. Write down the characteristic’s equation for JK & T Flipflop. (2)

    PART B (2 x 13= 26 marks)


    CO2 a) What is Multiplexer? With a neat Logic diagram explain in detail function of 8:1
    Multiplexer? (OR)
    U
    6. (13)
    CO3 R b) Define Register & explain the working principle of SISO?

    CO2 U a) Explain in detail about the function of Parity Generator / Parity Checker. (OR)

    7. (13)
    CO2 U b) What is Encoder? Explain the function of Priority Encoder.
    PART C (1x 14 = 14 marks)
    CO2 U a) With a neat diagram explain in detail about the working principle of a 4-bit
    look ahead carry adder. (OR)
    (14)
    CO2 U b) Explain in detail about the working principle of Seven Segment Display
    8. Decoder.

    Prepared by Verified by Approved by

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