UCS507

Roll Number:
Thapar Institute of Engineering & Technology, Patiala

Department of Computer Science and Engineering
EST examination: 2021
B. E. COE 3rd Year Course Code: UCS-507
Course Name: Computer Architecture &
Organization
Time: 2 Hours, M. Marks: 50 Name of Faculty: Dr. Anju Bala, Dr. Rupali
Date: 5th Feb. 2021, Time:2:30 p.m. Bhardwaj
Note: Attempt any five questions out of seven questions. Attempt all the questions in
sequence.
Q1 (a) Consider a 3-bit combinational circuit that have three inputs (x, y, and z) (2,2)
and three outputs (a, b, and c). When the input number is 0, 1, 2, and 3,
the binary output should be one less than the 2's complement of input
number. When the input number is 4, 5, 6, and 7, the binary output
should be one greater than the 2's complement of input number. Show
the following:
a. Truth table of the 3-bit combinational circuit.
b. Write the Simplified expression for the three outputs (a, b, and c)
in SOP form using K-map. (Note: discard the carry, if generated
during computations).
Q1 (b) Design a block diagram of 4- bit shifter and truth table by taking (4,2)
selection variable S, when S=0, It will perform shift right, when S=1, it
will perform shift left.
Q2(a) Show the content in hexadecimal of registers PC, AC, AR, DR, IR and SC of (6)
the basic computer. Given the initial content of PC is FFF, the content of
AC is 7EC3. The content of memory at address FFF is 8BCD. The content
of memory at address BCD is B420. The content of memory at address
420 is FFFF. Give the answer in table with six columns, Repeat the
problem six more times starting with an opcode of all other memory
reference instructions by taking the initial values which are given for all
instructions.
Q2(b) An 8-bit computer has register R1 having value #FF (in hexadecimal). (4)
Determine the values of C, S, Z, and V (status flags) after the execution of
following instructions using immediate addressing mode by assuming
input as in hexadecimal:
(i) AND R1, #15 (ii) SUB R1, #B7
Q3.(a) Assume that the three outputs xyz from the priority encoder of size 8x3 (3,2)
that are used to provide a vector address of the form101xyz00. Design
the truth table and list the eight vector addresses starting from the one
with the highest priority. (assume zero has the highest priority)
Q3(b) Using the Booth's algorithm for multiplication of signed 2's complement
numbers, perform (-10) x (5). Mention the output at each step of the
algorithm clearly taking value of n as 5.
Q4(a) A relative mode brach instruction is stored in memory at address 6200.
1
The branch is made to location 53010. The address field in the
instruction is 10 bits long. What is the binary value of the address field
in 2's compliment representation?
Q4(b) A computer uses RAM chips of 1Gx16 capacity. How many chips are (1,1, 2, 3)
needed and how should their address lines to be connected to
implement the memory of 4Gx16 RAM. Construct the memory map and
block diagram to show the connections required to implement the 4G
X16 RAM.
Q5(a) Suppose a computer using direct mapped cache has 2 20 words of main (1,2,2)
memory and a cache of 32 blocks, where each cache block contains 16
words.
a. How many blocks of main memory are there?
b. What is the format of a memory address as seen by the cache,
that is, what are the sizes of the tag, block, and word fields?
c. To which cache block will the memory reference (0DB63)16 map?
Q5(b) How the associative memory is used to read the content fast? Explain it (5)
by using the block diagram.
Q6(a) A 5-stage pipelined processor has Instruction Fetch (IF), Instruction (4,1)
Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write
Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle
each for any instruction. The PO stage takes 1 clock cycle for ADD and
SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles
for DIV instruction respectively. Operand forwarding is used in the
pipeline. Design the space time diagram and find the number of clock
cycles needed to execute the following sequence of instructions?
Instruction Meaning of instruction
10: MUL R2 ,RO, R1 R2 4— RO *R1
II.: DIV R5, R3, R4 R5 R3/R4
12:ADD R2, R5, R2 R2 4— R5+R2
13:SUB R5, R2, R6 R5 R2-R6
Q6(b) The non-pipelining system takes 40 ns to process a task, the same task (2+3)
can be processes in six segment pipeline with clock cycle time of lOns.
Determine the speedup ratio of pipeline for 100 tasks, derive and
calculate the maximum speedup ratio.
Q7(a) Write a program in ARM assembly language to perform multiplication (5)
using repeated addition.
Q7(b) Describe Interrupt cycle in brief with flowchart. Specify corresponding (5)
micro operations at each stage

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