Q.4 Explain CPU organization in detail with necessary block diagram.

2009,
2011
Ans.- CPU ORGNIZATION- CPU is the major part of computer that performs the bulk of data-
processing operations. CPU is the brain of a computer. Its primary function is to execute
programs. The program, which is to be executed, is stored in the main memory. A program is a
sequence of instructions to perform a specified task. The CPU fetches instruction codes from the
memory and decodes them. The necessary data for the execution of an instruction may be in
register of the CPU or in the memory. When the required data for the execution of an instruction
is at hand, the CPU executes the instruction. When all the instructions of a program are executed,
the CPU gives the result. The result is placed in the memory or sent to an output device
according to the instruction given in the program. Besides executing programs, the CPU also
controls input devices, output devices and other components of the computer. It controls input
and output devices to receive and send data. Under its control programs and data are stored in the
memory and display on the CRT screen. The CPU of a small computer is microprocessor. The
CPU of a large computer contains a number of microprocessors. They work in parallel to execute
a program. This makes computer more powerful and faster.
The CPU is made up of three major parts- the register set, ALU and CU. The ALU performs the
required micro operations for executing the instructions. The function of an arithmetic and logic
unit is to perform arithmetic and logic operations. Usually an ALU performs the following
arithmetic and logic operations.–
Addition, subtraction, multiplication,
division, logical AND, OR, EXCLUSIVE-
OR, Complement, Increment, Decrement,
Left or right shift, clear etc. Other
mathematical operations such as
exponential, logarithmic, trigonometric
and floating-point operations are not performed by ALU. These operations are performed by
special purpose math processor called floating-point unit (FPU). Modern microprocessors
contain an FPU on the microprocessor chip itself (i.e. an On-chip FPU). Some cheaper
microprocessor which is used for simple automatic control applications may not contain on-chip
FPU. Such processors use either software or employ a math processor IC (or math coprocessor)
in the microprocessor-based system. The use of software for such mathematical operations
makes execution slower. Math processors speed up program execution and reduce programming
complexity.
The Control Unit of CPU controls the entire operation of the computer. This very important
section of the CPU really acts as the brain of the computer. It also controls all other devices such
as memory, input and output devices connected to the CPU. It fetches instructions from the
memory, decodes the instruction, interprets the instruction to know what tasks are to be
performed and sends suitable control signals to other components to perform further necessary
steps to execute the instruction. It maintains order and directs the operation of the entire system.
It gives order to ALU what operations are to be performed. It generates timing and control
signals, and provides them for all operations. It controls the data flow between CPU and
peripherals (including memory). It provides status, control and timing signals that the memory
and I/O devices require. The control unit supervises the transfer of information among the
registers and instructs the ALU as to which operation to perform. The CPU performs a variety of
functions dictated by the type of instructions that are incorporated in the computer.
Under the control of the control unit the instructions are fetched from the memory one after
another for execution until all the instructions are executed. In a Von-Neumann type processor
such as Intel 8085, for fetching and executing an instruction the following steps are performed
under its control:
1. The address of the memory location where instruction lies, is placed on the address bus.
2. Instruction is read from the memory.
3. The instruction is sent to the decoding circuitry for decoding.
4. Addresses and data required for the execution of the instruction are read from the
memory.
IN 80h.
5. These data/addresses are sent to the other section for processing.
6. The results are sent to the memory or kept in some register e.g. ADD A, M; STA D050h.
7. Necessary steps are taken to fetch next instruction. For this the content of program
counter register is incremented.
Register- A CPU contains a number of registers to store data temporarily during the execution of
a program. The number of registers differs from processor to processor. The register set stores
intermediate data used during the execution of the instructions. Some processor contains more
registers, some less. Memory locations are needed for storing pointers, counters, return
addresses, temporary results, and partial products during multiplication. Having to refer to
memory locations for such applications is time consuming because memory access is the most
time consuming operation in computer. It is more convenient and more efficient to store these
intermediate values in processor registers. Registers are classified as follows-
General Purpose Registers- These registers store data and intermediate results during the
execution of a program. They are accessible to users through instructions if the users are working
in assembly language. MOV B, C; ADD B (AC  (AC) + (B)). In 8085, B, C, D, E, H and L are
general purpose or scratch pad registers.
Accumulator- It is the most important general-purpose register having multiple functions. It is
most efficient in data movement (IN 80H) (AC  port (80H)), OUT 80H (port (80H)  (AC));
arithmetic (ADD B), and logical operations (AND B). Its functions depend on the design of the
processor whether the processor is an accumulator-based processor or general purpose register-
based processor (ADD R1, R2, R3) (R1  R2 + R3)). It has some special features that the other
general-purpose registers do not have. In an accumulator-based processor design, the
accumulator holds one of the operands of arithmetic and logical operation. After the execution of
arithmetic and logical instructions, the result is placed in the accumulator. All data transfer
between the CPU and device/port are performed through the accumulator.
Special Purpose Registers- A CPU contains a number of special purpose registers for different
purposes. These are Program Counter (PC), Stack Pointer (SP), Instruction Register (IR), Flag
/Status Register, Data Register (DR)/ Memory Buffer Register (MBR), Memory Address
Register (MAR) etc.
Program Counter (PC)- The Program Counter keeps track of the address of the instruction
which is to be executed next. So, Program counter holds the memory location of the next
executable instruction. It is auto incremented. In case of jump instruction its contents are
modified, and program jumps to the memory location which contains the desired instruction
to be executed next. The processor which employs Von Neumann architecture contains a
program counter.
Stack Pointer (SP)- The stack is a sequence of memory location defined by the user. It is used
to save the contents of a register if it is required during the execution of a program. Stack
pointer holds the top-empty location of stack. Thus it indicates upto what memory locations
the stack is already filled up. It may be incremented or decremented manually or
automatically by PUSH/POP or CALL/RETURN instruction respectively.
Flag register (Program Status Word-PSW)- It is bit oriented register, used to indicate the
status of obtained result and control. In 8085 microprocessor, the flags register can have a
total of eight flags. Thus a flag can be represented by 1 bit of information. But only five flags
are implemented in 8085. And they are:
 Carry flag (Cy),
 Auxiliary carry flag (AC),
 Sign flag (S),
 Parity flag (P), and
 Zero flag (Z).
The respective position of these flag bits in flag register has been show the below figure. The
positions marked by “x” are to be considered as don't care bits in the flags register. The user is
not required to memorize the positions of these flags in the flags register.

Fig. Flags register

These individual flags are either set to 1, or reset to 0 depending on the result of execution of
the last executed arithmetic or logical instruction.
 Carry flag (Cy): after performing the addition of any two 8-bit numbers, the carry generated
can be either 0 or 1. That is only 1-bit. Thus to store the carry information 1-bit storage is
enough. The Cy flag is stored in the Least Significant bit position in the flags register.
Instructions that use the Cy flag are widely used in the user programs.
A=1010
B=1001
R = 10011
Auxiliary carry flag (Ac): Now let us consider the addition of any two 8-bit (2-hex digit)
numbers, a carry may be generated when we add the LS hex digits (4-bit /nibble group) of the
two numbers. Such a carry is called intermediate carry also known as half carry, or auxiliary
carry (AC).
Sign flag (S): The S flag is set to 1, when the result thus produced against any logical or
arithmetic operations is negative, indicated by MS bit of 8-bit result being 1. It is reset to 0
otherwise if the result is positive, indicated by MS bit of 8-bit result being 0.
Parity flag (P): The P flag is set to 1, if the 8-bit result thus produced against any logical and
arithmetic operation has an even number of 1's in it. If there are odd number of 1's in the 8-bit
result, the P flag is reset to 0.
Zero flag (Z): The Z flag is set to 1, if after arithmetic and logical operations, the 8-bit result
thus produced, is 00H. If the 8-bit result is not equal to 00H, the Z flag is reset to 0. Thus the
Z flag is hoisted to indicate that the result is 0.
Instruction Register (IR)- It holds an instruction until it is decoded. Some computer have two
instruction registers, and so they can fetch and save the next instruction while the execution of
the previous instruction is going on.
Memory Address Register (MAR)- It holds the address of the instruction or data to be fetched
from the memory. The CPU transfers the address of the next instruction from the program
counter (PC) to the memory address register. From MAR it is sent to the memory through the
address bus. Sometimes it is called simply address register (AR). Address register holds the
location of currently executable instruction.
Memory Buffer Register (MBR) or Data Register (DR)- It holds the instruction code or data
received from or sent to the memory. It is connected to data bus. The data, which are written into
the memory, are held in this register until the write operation is completed. It is also called Data
Register (DR). Thus the flow of data from the CPU to the memory or from the memory to CPU
is always through MBR. Data register hold the operand and code of the instruction during the
execution of instruction.
Memory locations are needed for storing pointers, counters, return addresses, temporary results,
and partial products during multiplication. Having to refer to memory locations for such
applications is time consuming because memory access is the most time consuming operation in
computer. It is more convenient and more efficient to store these intermediate values in
processor registers. It is more efficient to connect these registers through a common bus system.
General Register Organization- A bus organization for seven CPU registers is shown in figure.
The output of each register is connected to two multiplexer (MUX) to form the two buses A and
B. The selection lines in each multiplexer select one register or the input data for the particular
bus. The A and B buses form the inputs to a common arithmetic logic unit (ALU). The operation
selected in the ALU determines the arithmetic or logic micro operation that is to be performed.
The register that receives the information from the output bus is selected by a decoder. The
control unit that operates the CPU bus system directs the information flow through the registers
and ALU by selecting the various components in the system. There are 14 binary selection inputs
in the unit, and their combined value specifies a control word. It consists of four fields. Three
fields contain three bits each, and one field has five bits. The three bits of SELA select a source
register for the A input of the ALU. The three bits of SELB select a register for the B input of the
ALU. The three bits of SELD select a destination register using the decoder and its seven load
outputs. The five bits of OPR select one of the operation in the ALU. The useful feature that is
included in the CPU of most computers is a stack or last-in, first-out list. A stack is a storage
device that stores information in such a manner that the item stored last is the first item retrieved.
The stack in digital computers is essentially a memory unit with an address register that can
count only. The register that holds the address for the stack is called a stack pointer (SP) because
its value always points at the top item in the stack. The two operations of a stack are the insertion
and deletion of items. The operation of insertion and deletion are called PUSH and POP
respectively. Most computers fall into one of the three types of CPU organizations:
Single accumulator organization
General register organization
Stack organization
Accumulator type organization- Here all the operations are performed with an implied
accumulator register. The instruction format in this type of computers uses one address fields for
example ADD X performs AC  AC + M[X]; here AC is the accumulator register.
General register type organization- The instruction format in this type of computer needs three
register address fields example- (ADD R1,R2,R3) to denote the operation R1R2 +R3. The
number of address fields can be reduced from three to two if the designation register is the same
as one of the source registers.
Stack-type organization- Operation type instruction does not need an address field in stack
organization computers. This is because the operation is performed on the two items that are on
top of the stack. For example, the instruction ADD in stack computer performs addition on two
top items by popping and then pushing the result on the stack.
Some computers combine features from more than one organizational structure.
Microprocessor : Basically practical implementation of CPU is called microprocessor. It is a
single chip CPU in VLSI technology. It processes or manipulates the data. Microprocessor
consists of CPU (Central Processing Unit), input devices, output devices and memory. 8085,
8086, Pentium 4, Celeron, Athion, Dual core, Core 2 Duo are the general examples of CPU. It is
design for multitasking operation. On the other hand, it performs many tasks simultaneously.

(a) Fetch an instruction from main

memory.
(b) Perform arithmetic and logical
operations.
(c) Decode it and generate appropriate
timing arid control signals.
(d) Control the entire computer
operations.
Clock frequency: The processing speed
of microprocessor depends upon clock
frequency.

 BUS: It is a bundle of wires,

which give single purpose (either data, address). These wire give data, address and acts
as control lines.
 Address Bus: The address bus also a set of parallel connected lines. The address bus
consist of 16, 20, 24 or 32 parallel lines. Address bus carries the address of the memory
or I/O location to be read or written from.
  Data Bus: The data bus consists of
8, 16 or 32 parallel lines. .The data
bus is a bidirectional bus. The data
bus can transfer the data from CPU
to memory or vice versa. The data
bus also connects the I/O ports and
microprocessor.
 ALU (Arithmetic/logic unit): ALU
stands (Arithmetic/logic unit). This
units can perform arithmetic operations (like addition, subtraction, multiplication and
division) and logical operations like (AND, OR, X-OR, NOT, Rotating etc.).
 Register set- These are the temporary storage element inside the CPU. There are various
types of register depends upon their function. Some are as follows-

AC- Accumulator register is special type of register which hold the one operand prior
performing arithmetic, logical, shift or I/O operation in accumulator based CPU.
PC- Program counter holds the memory location of the next executable instruction. It is
auto incremented.
Scatch Pad- It is also called general purpose registers (GPR). It is used to store
intermediate values.
SP- Stack pointer holds the top-empty location of stack. It may be incremented or
decremented manually or automatically by PUSH/POP or CALL/RETURN instruction
respectively.
AR- Address register holds the location of currently executable instruction.
Flag register- It is bit oriented register, used to indicate the status of obtained result and
control.
DR- Date register hold the operand and code of the instruction during the execution of
instruction
8085 (Microprocessor)
1. It is an 8-bit microprocessor. It can accept or provide 8 bit data simultaneously.
2. It has 8 bit ALU that can perform 8 bit operations.
3. It is based on NMOS technology.
4. It provides 16 address lines, hence it can
access 216 = 64 KB of memory.
5. It generates 8 bit I/O address; hence it can
access 28 = 256 I/O ports.
6. It has 8-bit internal data bus and registers.
7. It provides 5 level interrupts.
8. It provides two serial I/O lines.
9. 8085 was the first processor that required
only single +5V power Supply.
10. It has an on-chip clock generator.
 Serial I/O Controller

Pin Configuration of Intel 8085

A8-A15 – (Output)- These are address lines. They form the address bus. They carry 8 MSBs of
the memory address.
AD0-AD7 – (Input/Output)- These are address/data lines. They form time-multiplexed
address/data bus, i.e. they serve dual purpose. They carry 8 LSBs of the memory address or I/O
address during the first clock cycle of a machine cycle. Again they are used to carry data during
the second and third clock cycles.
ALE(Output)- It is an address latch enable signal. It goes high during the first clock cycle of a
machine cycle and enables 8 LSBs of the address to get latched into the on-chip latch of
peripheral.
IO/ ̅ (Output)- It is a status signal to indicate whether the address sent by the microprocessor is
for a memory or an I/O device. When it is high the address on the address bus is for an I/O
device. When it is low the address on the address bus is for the memory.
So and S1 (Output)-These are status signals issued by the microprocessor to identify the various
types of operations given below-

S1 S0 Operation

0 0 Halt
 0 1 Write

1 0 Read

1 1 Fetch

̅̅̅̅̅(Output)- It is a control signal sent by the microprocessor to control read operation. The
selected memory or I/O device is read when ̅̅̅̅̅ is low.
̅̅̅̅̅ (Output)- It is a control signal sent by the microprocessor to control write operation. The
data on the data bus are written into the selected memory or I/O device when is ̅̅̅̅̅ low.
HOLD (Input)- When an external device wants to use the address and data bus for data transfer,
it sends HOLD signal to the microprocessor. Having received the HOLD signal, the
microprocessor completes its current machine cycle at hand, and then gives up the control of
buses to allow the external device to use them.
HLDA (Output)-It is a HOLD acknowledgement signal. It is sent by the microprocessor to the
external device to indicate that the HOLD request has been received. On the completion of data
transfer, the external device removes the HOLD request. The HLDA goes low after the removal
of HOLD request. The CPU takes over the control of the buses half cycle after the HLDA goes
low.
INTR (Input)- It is an interrupt signal of the lowest priority.
̅̅̅̅̅̅̅ (Output)- it is an interrupt acknowledgement signal. It is issued by microprocessor after
INTR is received.
RST 7.5, RST 6.5, RST 5.5 and TRAP (Input)- These are interrupts. The TRAP is a non-
maskable interrupt and has the highest priority. Others are maskable interrupt.
RESET IN (Input)- When this signal is applied the CPU is brought to reset condition. The
content of the program counter becomes zero.
RESET OUT (Output)- The signal indicates that the CPU is being reset.
READY (Input)- It is an input signal to the microprocessor. It is sent by a peripheral device to
indicate whether it is ready to transfer data or not. If this signal is high it shows that peripherals
are ready to transfer data.
X1 and X2 (Input)- An external crystal oscillator is connected to these terminals to supply clock
for the microprocessor. The crystal oscillator derives an internal circuitry which is within the
microprocessor to produce suitable clock for the operation of the microprocessor.
CLK OUT (Output)- The clock is also required by some other ICs of the computer. Hence CLK
is a clock output from the microprocessor, which can be utilized for the operation of other ICs.
SID (Input)- It is an input line for serial data. The data received from this are loaded into the 7th
bit of the accumulator when RIM instruction is executed.
SOD (Output)- It is an output lines for serial dat. The 7th bit of the accumulator is sent through
this line when SIM instruction is executed.

Instruction format
A computer will usually have a variety of instruction code formats. It is the function of control
unit within the CPU to interpret each instruction code and provide the necessary control
functions needed to process the instruction. The format of instruction is usually depicted in a
rectangular box symbolizing the bits of the instruction as they appear in memory words or in a
control register. The bits of the instructions are divided into groups called fields. The common
fields found in instruction formats are:
1. An operation code field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor register.
3. A mode field that specifies the way the operand or the effective address is determined.
The operation code field of an instruction is a group of bits that define various processor
operations, such as add, subtract, complement, and shift. The bits that define the mode field of an
instruction code specify a variety of alternatives for choosing the operands from the given
address.
An instruction is a command given to the computer to perform a specified operation on given
data. Each instruction consists of two parts: an opcode (operation code) and an operand. The first
part of an instruction, which specifies the operation to be performed, is known as opcode. The
second part of an instruction called operand is the data on which computer performs the specified
operation.
Operations specified by computer instructions are executed on some data stored in memory or
processor registers. Operand residing in memory are specified by memory address. Operands
residing in processor registers are specified with a register address. A register address is a binary
number of k bits that defines one of 2k registers in the CPU. Thus a CPU with 16 processor
registers R0 through R15 will have a register address field of four bits. The binary number 0101,
for example, will designate register R5.
Computers may have instructions of several different lengths containing varying number of
addresses. The number of address fields in the instruction format of a computer depends on the
internal organization of its registers. Most computers fall into one of three types of CPU
organization:
1. Single accumulator organization
2. General register organization
3. Stack organization
In an accumulator based organization, one special register is treated as an accumulator which
store one operand value prior performing arithmetic, logical, shift or other operation namely
Input and output operations. All operations are performed with an implied accumulator register.
The instruction format in this type of computer uses one address field. For example, the
instruction that specifies an arithmetic addition is defined by an assembly language instruction as
ADD X
Where X is the address of the operand. The ADD instruction in this case results in the operation
AC  (AC) + M[X]. AC is the accumulator register and M[X] symbolizes the memory word
located at address X.
The instruction format of a general purpose register type of organization needs three register
address fields. Thus the instruction for an arithmetic addition may be written in an assembly
language as
ADD R1, R2, R3
to denote the operation R1  (R2) + (R3). The number of address fields in the instruction can be
reduced from three to two if the destination register is the same as one of the source register.
Thus the instruction
ADD R1, R2
would denote the operation R1  (R1) + (R2). Only register addresses for R1 and R2 need be
specified in this instruction.
General purpose register type computers employ two or three address fields in their instruction
format.
In a stack oriented computer, there is no address part in an instruction. This is because the
operation is performed on the two items that are on top of stack. The instruction
ADD
in a stack computer consists of an operation code only with no address field. This operation has
the effect of popping the two top numbers from the stack, adding the numbers and pushing the
sum into the stack. There is no need to specify operands with an address field since all operands
are implied to be in the stack

Alternative Way of Classification of Instructions

Instructions can also be classified depending upon the number of operand addresses they
contains. Such a classification is as follows:
1. 0-adddress instruction: These types of instructions do not contain any operand address.
The operand address are implied (hidden). CMP (There is no operand address) It
complements the contain of accumulator which is hidden. RAR rotate the content of
accumulator right.
A stack-organized computer does not use address field for the instruction ADD and MUL.
The PUSH and POP instructions, however, need an address field to specify the operand
that communicates with the stack. The following program shows how X = (A+B) * (C+D)
will be written for a stack organized computer.
PUSH A TOS  A
PUSH B TOS  B
ADD TOS  (A + B)
PUSH C TOS  C
PUSH D TOS  D
ADD TOS  (C + D)
MUL TOS  (C+D) * (A+B)
POP X M[X]  TOS
The name “zero address” is given to this type of computer because of the absence of an
address field in the computational instructions.
 2. 1-address instruction: In 1-address instructions only one operand address is specified in
the instruction. The other operand address is implied. The other operand is in the
accumulator. The result is placed in the accumulator. (ADD B)
The program to evaluate X = (A+B) * (C+D) is
LOAD A AC  M[A]
ADD B AC  AC + M[B]
STORE T M[T]  AC
LOAD C AC  M[C]
ADD D AC  AC + M[D]
MUL T AC  AC * M[T]
STORE X M[X]  AC
All operations are done between the AC register and a memory operand. T is the address of
a temporary memory location required for storing the intermediate results.
3. 2-Address instruction: In this, both operand addresses are specified. The result is placed
in the one of the specified addresses. (ADD R1,R2); R1 (R1) + (R2)
Two-address instructions are the most common in commercial computers. The program to
evaluate X = (A+B) * (C+D) is
MOV R1, A R1  M[A]
ADD R1, B R1  R1 + M[B]
MOV R2, C R2  M[C]
ADD R2, D R2  R2 + M[D]
MUL R1, R2 R1  R1 * r2
MOV X, R1 M[X]  R1
The first symbol listed in an instruction is assumed to be both a source and the destination
where the result of the operation is transferred.
4. 3-Address instruction- In this instruction, two addresses are specified for the two
operands and one address for the result. (ADD R1, R2, R3), (R1)  (R2) + (R3).
Computers with three-address instruction formats can use each address field to specify
either a processor register or a memory operand. The program to evaluate X = (A+B) *
(C+D) is shown below
ADD R1, A, B R1  M[A] + M[B]
ADD R2, C, D R2  M[C] + M[D]
MUL X, R1, R2 M[X]  R1*R2

Instruction Word Size in Microprocessor

The 8085 instruction set is classified into 3 categories by considering the length of the
instructions. In 8085, the length is measured in terms of “byte” rather than “word” because 8085
microprocessor has 8-bit data bus. Three types of instruction are: 1-byte instruction, 2-byte
instruction, and 3-byte instruction.
1. One-byte instructions –
In 1-byte instruction, the opcode and the operand of an instruction are represented in one byte.
 Example-1:
Task- Copy the contents of accumulator in register B.
Mnemonic- MOV B, A
Opcode- MOV
Operand- B, A
Hex Code- 47H
Binary code- 0100 0111
 Example-2:
Task- Add the contents of accumulator to the contents of register B.
Mnemonic- ADD B
Opcode- ADD
Operand- B
Hex Code- 80H
Binary code- 1000 0000
 Example-3:
Task- Invert (complement) each bit in the accumulator.

Mnemonic- CMA
Opcode- CMA
Operand- NA
Hex Code- 2FH
Binary code- 0010 1111
Note – The length of these instructions is 8-bit; each requires one memory location. The mnemonic
is always followed by a letter (or two letters) representing the registers (such as A, B, C, D, E, H, L
and SP).
2. Two-byte instructions –
Two-byte instruction is the type of instruction in which the first 8 bits indicates the opcode and the
next 8 bits indicates the operand.
 Example-1:
Task- Load the hexadecimal data 32H in the accumulator.
Mnemonic- MVI A, 32H
Opcode- MVI
Operand- A, 32H
Hex Code- 3E
32
Binary code- 0011 1110
0011 0010
 Example-2:
Task- Load the hexadecimal data F2H in the register B.
Mnemonic- MVI B, F2H
Opcode- MVI
Operand- B, F2H
Hex Code- 06
F2
Binary code- 0000 0110
 1111 0010
Example-3:
Task- Load input content from specified port
Mnemonics – IN 80H
Opcode- IN
Operand- 80H (address)
Hex code- DB
80H
Binary code- 11011011 10000000
Note – This type of instructions need two bytes to store the binary codes. The mnemonic is always
followed by 8-bit (byte) data.
3. Three-byte instructions –
Three-byte instruction is the type of instruction in which the first 8 bits indicates the opcode and
the next two bytes specify the 16-bit address. The low-order address is represented in second byte
and the high-order address is represented in the third byte.
 Example-1:
Task- Load contents of memory 2050H in the accumulator.
Mnemonic- LDA 2050H
Opcode- LDA
Operand- 2050H
Hex Code- 3A
50
20
Binary code- 0011 1010
0101 0000
0010 0000
 Example-2:
Task- Transfer the program sequence to the memory location 2050H.
Mnemonic- JMP 2085H
Opcode- JMP
Operand- 2085H
Hex Code- C3
85
20
Binary code- 1100 0011
1000 0101
0010 0000
Note – These instructions would require three memory locations to store the binary codes. The
mnemonic is always followed by 16-bit (or adr).
Addressing Modes– The operation field of an instruction specifies the operation to be
performed. This operation must be executed on some data stored in computer registers or
memory words. The way the operand are chosen during program execution is dependent on the
addressing mode of the instruction. The addressing mode specifies a rule for interpreting or
modifying the address field of the instruction before the operand is actually referenced. The term
addressing modes refers to the way in which the operand of an instruction is specified. The
addressing mode specifies a rule for interpreting or modifying the address field of the instruction
before the operand is actually executed. The way of specifying data to be operated by an
instruction is called addressing mode. Computers use addressing mode techniques for the
purpose of accommodating one or both the following provisions:
1. To give programming versatility to the user by providing such facilities as pointers to
memory, counters for loop control, indexing of data, and program relocation.
2. To reduce the number of bits in the addressing field of the instruction.
Types of addressing modes –
In 8085 microprocessor there are 5 types of addressing modes:
1. Immediate Addressing Mode –
In immediate addressing mode the source operand is always data. If the data is 8-bit, then
the instruction will be of 2 bytes, if the data is of 16-bit then the instruction will be of 3
bytes. In this mode, the operand is specified in the instruction itself. In other words, an
immediate-mode instruction has an operand field rather than address field. The operand
field contains the actual operand to be used in conjunction with the operation specified in
the instruction. Immediate-mode instructions are useful for initializing registers to a
constant value.
Examples:
MVI B 45 (move the data 45H immediately to register B)
LXI H 3050 (load the H-L pair with the operand 3050H immediately)
JMP address (jump to the operand address immediately)
Effective Address = Address of Instruction

2. Register Addressing Mode –

In register addressing mode, the data to be operated is available inside the register(s) and
register(s) is (are) operands. Therefore the operation is performed within various registers
of the microprocessor.
Examples:
MOV A, B (move the contents of register B to register A)
ADD B (add contents of registers A and B and store the result in register A)
INR A (increment the contents of register A by one)
Effective Address = Address of Registers

3. Direct Addressing Mode –

In direct addressing mode, the data to be operated is available inside a memory/IO location
and that memory location is directly specified as an operand. The address of operand is
directly available in the instruction itself. In a branch-type instruction the address field
specifies the actual branch address e.g. JMP C050H.
Examples:
LDA 2050 (load the contents of memory location into accumulator A)
LHLD address (load contents of 16-bit memory location into H-L register pair)
IN 35 (read the data from port whose address is 35)
Effective Address = Address part of Instruction
4. Register Indirect Addressing Mode –
In register indirect addressing mode, the data to be operated is available inside a memory
location and that memory location is indirectly specified by a register pair. In this mode the
address part of the instruction gives the address where the effective address is stored in
memory. Control fetches the instruction from memory and uses its address part to access
memory again to read the effective address.
Examples:
MOV A, M (move the contents of the memory location pointed by the H-L pair to the
accumulator)
LDAX B (move contents of B-C register which indicates the memory location to the
accumulator)
Effective Address = Content of Register

5. Implied/Implicit Addressing Mode –

In implied/implicit addressing mode the operand is hidden and the data to be operated is
available in the instruction itself. In this mode the operands are specified implicitly in the
definition of the instruction. For example, the instruction “complement accumulator is an
implied-mode instruction because the operand in the accumulator register is implied in the
definition of the instruction. Zero-address instruction in a stack-organized computer are
implied-mode instruction since the operands are implied to be on top of the stack.
Examples:
CMA (finds and stores the 1’s complement of the contains of accumulator A in A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)
Effective Address = Address of Accumulator or stack

6. Branch Addressing Mode-

In this addressing mode, program counter is modified conditionally or unconditionally. In a
conditional branch instruction, flag bit namely zero, carry, parity etc are checked before
jump to specified location. On the other hand, in an unconditional branch, program counter
is modified without checking any flag viz JMP C050H, here the content of program
counter is altered by putting C050 address from which we can execute subroutines. Some
example of conditional branch instructions are JNC C050H i.e. jump if there is no carry to
specified location C050H.
A few addressing mode require that the address field of the instruction be added to the
content of a specific register in the CPU. The effective address in these mode is obtained
from the following computation:
Effective address = address part of instruction + content of CPU register
The CPU register used in the computation may be the program counter, an index register or
a base register. In either case we have a different addressing mode which is used for a
different application-
1. Relative Addressing Mode- In this mode the content of the program counter is added to
the address part of the instruction in order to obtain the effective address.
2. Index Addressing Mode- In this mode the content of an index register is added to the
address part of the instruction to obtain the effective address. The index register is a
 special CPU register that contains an index value. The address field of the instruction
defines the beginning address of a data array in memory. The distance between the
beginning address and the address of the operand is the index value stored in the index
register.
3. Base Register Address Mode- In this mode the content of a base register is added to the
address part of the instruction to obtain the effective address. This is similar to the
indexed addressing mode except that the register is now called a base register instead of
index register. The difference between the two modes is in the way they are used rather
than in the way that are computed. An index register is assumed to hold an index number
that is relative to the address part of the instruction. A base register is assumed to hold a
base address and the address field of the instruction gives a displacement relative to this
base address. The base register addressing mode is used in computer to facilitate the
relocation of program in memory.
Numerical Example
The two-word instruction at address 200 and 201 us a “load to AC” instruction with an address
field equal to 500. The first word of instruction specifies the operation code and mode, and the
second word specifies the address part. Program Counter (PC) has the value 200 for fetching the
instruction. The content of processor register R1 is 400, and the content of index register XR is
100. AC receives the operand after the instruction is
LDA 500 executed.
Address Memory
PC = 200 200 Load to AC Mode Addressing Effective Content of AC
201 Address = 500
R1 = 400 202 Next instruciton
Mode Address
Direct Address 500 800
XR = 100
Immediate 201 500
AC 399 450 operand
400 700
Indirect Address 800 300
Relative Address 702 325
500 800
Indexed address 600 900
600 900 Register R1 400
Register Indirect 400 700
702 325 Autoincrement 401 350
Autodecrement 399 450
800 300

Problem 8-14, 8-18.

Q.7 Discuss instruction sequencing. 2006