Bias Dependent Attenuation of Coplanar Transmission Lines On Silicon

Bias Dependent Attenuation of Coplanar Transmission Lines on Silicon
W. Zhao, C. Schllhorn, E. Kasper, Institut fr Halbleitertechnik, Universitt Stuttgart Pfaffenwaldring 47, D-70569 Stuttgart, Germany
1. Introduction
Recent trends toward wireless communication and short range sensing with low power radars strengthen the need for integrated circuits in the microwave and millimeter-wave region (frequencies from 10GHz to 100GHz). For the integration of active devices with passive networks or antenna a low loss substrate is required. These substrates may be either dielectric materials like ceramics in hybrid integration or high resistivity semiconductors in the case of monolithic integration. We concentrate on silicon because of the high integration potential of this semiconductor material.
2. Silicon mm-wave integrated circuits

High resistivity silicon substrates are commonly used for silicon monolithic millimeter wave integrated circuits (SIMMWIC) [1]. These substrates are grown using the float zone (FZ) technique. They have a specific resistance from 1000cm to 10000cm. Microstrip lines on such a high resistivity substrate show a low attenuation [2]. Coplanar transmission lines (CPW) have a higher attenuation, but on the other hand they have a number technological advantages. In contrast to microstrip lines there is no need for substrate thinning to reduce high order wave modes. Because signal and ground line are on the same side it is not necessary to etch via holes. In this paper we present measurements of the attenuation of aluminium coplanar transmission lines and show that the attenuation is bias voltage dependent. We give an explanation and proof of the attenuation mechanism. All transmission lines were realized on high resistivity (>1000cm) p-substrates with a uniform 200nm thick silicon oxide between substrate and metallization. The thickness of the aluminium layer is 1m. See figure 1 for a schematic picture of the coplanar lines and the field distribution. All dimensions of our coplanar lines were chosen to give a characteristic impedance of 50, e.g. a signal line width w=20m and a ground-to-ground spacing d=50m.
Fig. 1: Geometry of a coplanar transmission line and its field distribution
3. Attenuation mechanisms
The attenuation of a coplanar transmission line depends on the conductor losses of the metallization and on the substrate losses caused by bulk and interface the conductivity. With increasing line width w of the signal line the conductor losses decrease while the substrate losses are nearly constant. In contrast to the frequency dependent conductor losses the substrate losses do not depend on the frequency [3], [4], [5], [6]. For high resistivity substrates the substrate losses are very small compared to the conductivity losses [7]. This leads to a respectable reduction of the attenuation when the line width of the signal line is increased from 20m to 45m (Fig. 2). Up to 40GHz attenuation values below 1dB/mm were obtained in typical experiment. Even with a small signal width w=20m low losses were obtained. But often the attenuation depends on the oxide quality. The reason for this behaviour is explained in the next section.
2.0 1.8
V41/1
1.6
Attenuation (dB/mm)
w=20m, d=50m w=45m, d=95m
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 5G 10G 15G 20G 25G 30G 35G
Frequency (Hz)
Fig. 2: Attenuation of 50 coplanar transmission lines on high resistivity silicon
4. Bias effects on attenuation

As already mentioned the substrate losses are not only caused by the conductivity of the substrate but also by free interface charges between the silicon oxide and the substrate [8]. By setting up a bias voltage between the signal and ground line, the state of the interface can be switched from accumulation to inversion and vice versa. Between these two states there exists the depletion state. In this case the interface is without free charges leading to a minimum in attenuation. The sequence of layers in a CPW can be seen as a metal oxide silicon (MOS) structure (Fig. 1) therefore it is possible to determine the depletion region with capacity voltage (CV) measurements (Fig. 3). The threshold voltage depends on the substrate doping, the metal work function and the process conditions (e.g. the quality of the silicon oxide and the interface). In our measurements with aluminium metal, thin thermal oxide (0.2m) depletion is reached between -2.5 and -3.5 volts (Fig. 3). Minimal attenuation is reached for a bias voltage of -3 volts (Fig. 4). In the case of accumulation and inversion, charges are induced. This
leads to a higher attenuation. In the case of accumulation majority carriers (holes for ptype substrate) and in the case of inversion minority carriers (electrons for p-type substrate) are induced. As can be seen in figure 4 for increasing positive and negative voltage an increase in attenuation is measured. A positive voltage leads to an inversion while a negative voltage leads to accumulation in p-type substrates.
15
Accumulation
Inversion
10
Capacity pF
CV measurement CV-Messung
5
0 -10 -5 0 5
Bias V
Fig. 3: CV-measurement of the signal line demonstrating the bias dependent depletion case between accumulation and inversion
2.0 1.8
bias=+2V bias= 0V bias=-2V bias=-3V bias=-6V bias=-8V
Attenuation (dB/mm)
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 5G
10G
15G
20G
25G
30G
35G
Frequency (Hz)
Fig. 4: Attenuation of a coplanar transmission line with different bias voltages. (Dimensions: signal line width w=20m, ground to ground spacing d=50m) The bias dependence proves that a considerable part of the losses can be attributed to interface charges. A considerable reduction of losses may be obtained by proper design (e.g. oxide thickness) or proper bias.
5. Conclusion
A satisfactory explanation of attenuation of coplanar transmission lines on high resistivity silicon substrates was obtained. The results of our measurements show the frequency and geometry dependence of the attenuation of CPW on high resistivity silicon. In the investigated frequency regime 1-35GHz we demonstrated acceptable loss properties of CPW. Furthermore the possibility to influence the charge densities by means of a bias voltage between the signal and ground line was shown. In our next efforts we will examine the more conventional Czochralski (CZ) wafers as a substrate material for silicon monolithic mm-wave integrated circuits and we will quantify the improvement obtained by oxide patterning.
Acknowledgement :
Parts of this work was supported by the German Ministry of Research. The authors would like to thank Dr. Coenning and D. Wiegner for RF measurements, T. Guenkova for theoretical calculations, J. Eberhardt for processing, M. Ulm and J. Schier for discussion.
Literature :
[1]: J.-F. Luy, P. Russer, Silicon Based Millimeter Wave Devices, Springer-Verlag, Berlin (1994). [2]: J. Buechler, E. Kasper, P. Russer, K.M. Strohm, Silicon High-Resistivity-Substrate Millimeter-Wave Technology, IEEE Trans. MTT-34, pp. 1516-1521 (1986). [3]: R. K. Hoffmann, Integrierte Mikrowellenschaltungen, Springer-Verlag (1983). [4]: B. C. Wadell, Transmission Line Design Handbook, Artech House, Lodon (1991) [5]: K. Beilenhoff, Simulation und Modellierung von Leitungsdiskontinuitten und Vezweigungen fr monolithisch integrierte Millimeterwellen-schaltungen, VDI-Verlag, Dsseldorf (1996). [6]: W. Heinrich, J.Gerdes, F.J. Schmckle, C. Rheinfelder, and K.Strohm, Coplanar Passive Elements on Si Substrate for Frequencies up to 110GHz, IEEE MTT-46, pp. 709-712 (1998) [7]: W. Zhao, T. Guenkova, E. Kasper, Silicon Substrate Requirements For Microwave Coplanar Transmission Lines, IEDM-S, pp. 277-279 (1998) [8]: Y. Wu, S. Yang H.S. Gamble, B. M. Armstrong, V.F. Fusco, J.A.C. Stewart, The Effect of a SiO2 Interface Layer on CPW Lines and Schottky Barrier Diodes on HRS Substrates, IEEE MTT-S Silicon Monolithic Integrated Circuits in RF Systems, Symposium Abstracts (1998)

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Bias Dependent Attenuation of Coplanar Transmission Lines on Silicon

2. Silicon mm-wave integrated circuits

Fig. 1: Geometry of a coplanar transmission line and its field distribution

w=20m, d=50m w=45m, d=95m

Fig. 2: Attenuation of 50 coplanar transmission lines on high resistivity silicon

4. Bias effects on attenuation

1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 5G

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