INTERCONNECT:

Interconnect in an integrated circuit are physical connections between two transistors and/ or the
external surroundings.

 An electronic circuit designer has multiple choices in realizing the interconnections

between the various devices that make up the circuit.
 Here the start of the art processes offers multiple layers of aluminium or copper, and at
least one layer of polysilicon. Even the heavily doped n+ and p+ diffusion layers are
typically used for the realization of source and drain regions can be employed for wiring
purposes. These wires appear in the schematic diagrams of electronic circuit as simple
lines with no apparent impact on the circuit performance.

These wiring of integrated circuits forms a complex geometry that introduces the following
parasitics:

1. Capacitive Parasitics
2. Resistive Parasitics
3. Inductive Parasitics

The capacitive, resistive and inductive parasitics have multiple effects of the circuit’s behaviour
i.e.

 They all cause an increase in propagation delay, or equivalent, a drop in performance.

 They all have an impact on the energy dissipation and the power distribution.
 They all cause the introduction of extra noise sources, which affect the reliability of the
circuit.

It is important that the designer has a clear insight in the parasitic wiring effects, their relative
importance, and their models. This is best illustrated with the simple example as shown above.
Each wire in a bus network connects a transmitter (or transmitters) to a set of receivers and is
implemented as a link of wire segments of various lengths and geometries. Assume that all
segments are implemented on a single interconnect layer, isolated from the silicon substrate and
from each other by a layer of dielectric material. Be aware that the reality may be far more
complex.

COPING WITH INTERCONNECT:

As till now we have concentrated on the growing impact of interconnect parasitics on all design
metrics of digital integrated circuits. As mentioned, interconnect introduces three types of
parasitic effects i.e. capacitive, resistive, and inductive- all of which influence the signal integrity
and degrade the performance of the circuit. While so far we have concentrated on the modeling
aspects of the wire, we now analyze how interconnect affects the circuit operation, and we
present a collection of design techniques to cope with these effects with considering each
parasitics- this is referred to as coping with interconnect.

CAPACITIVE PARASITICS:

Capacitance reliability and Cross talk:

An unwanted coupling from a neighboring signal wire to a network node introduces an

interference that is generally called cross talk. The resulting disturbance acts as a noise source
and can lead to hard-to-trace intermittent errors, since the injected noise depends upon the
transient value of the other signals routed in the neighborhood. In integrated circuits, this inter
signal coupling can be both capacitive and inductive.
Capacitive cross talk is the dominant effect at current switching speeds, although inductive
coupling forms a major concern in the design of the input-output circuitry of mixed-signal
circuits. The potential impact of capacitive crosstalk is influenced by the impedance of the line
under examination. If the line is floating, the disturbance caused by the coupling persists and
may be worsened by subsequent switching on adjacent wires. If the wire is driven, on the other
hand, the signal returns to its original level.

Floating Lines:
 Capacitive coupling to a floating line

Approaching capacitive parasitic with respect to capacitive coupling to a floating line.

Considering the circuit shown as above, where line X is coupled to wire Y by a parasitic
capacitance CXY. Line Y sees a total capacitance to ground equal to CY. Assuming that the
voltage at node X experiences a step change equal to ΔV X. This step appears on node Y
attenuated by the capacitive voltage divider.

Circuits that are particularly susceptive to capacitive cross talk are networks with low- swing pre
charged nodes, located in adjacent to full- swing wires (with ΔVX = VDD). Examples of these
are dynamic memories, low swing on chip busses and some dynamic families. To address the
cross talk issue, level- restoring device or keepers are a must in dynamic logic.

Driven Lines:

Capacitive coupling to a driven line and its voltage response

As seen from the figure, if the line Y is driven with a resistance RY, a step on line X results in a
transient on line Y. The transient decays with a time constant ƮXY=RY (CXY+CY) . The actual
impact on the victim line is a strong function of the rise- fall time of the interfering signal.

If the rise time is comparable or larger than the time constant, the peak value of disturbance is
diminished. This can be observed in the response figure.
 Obvious, keeping the driving impedance of a wire and hence ƮXY low goes a long way towards
reducing the impact of capacitive cross talk. The keeper transistor added to a dynamic gate or pre
charged wire is an excellent example of how impedance reduction helps to control noise.

Therefore, the impact of cross talk on the signal integrity of driven nodes is rather limited. The
resulting glitches may cause malfunctioning of connecting sequential elements, and should
therefore be carefully monitored. The most important effect is an increase in delay.

Design Techniques to Deal with Capacitive Cross talk:

1. If possible avoid floating nodes, nodes sensitive to cross talk problems such as pre
charged busses, should be equipped with keeper devices to reduce the impedance.
2. Sensitive nodes should be well separated from full swing signals.
3. Making the rise- fall time as large as possible subjection to timing constraints.
4. Use differential signalling in sensitive low swing wiring networks. This turns the cross
talk signal into a common mode noise source that does not impact the operation of the
circuit.
5. To keep the cross talk minimum, do not allow the capacitance between the two signal
wires to grow too large.
6. If necessary provide shielding wire- GND or VDD between the two signals as show
below. This effectively turns the interwire capacitance into a capacitance to ground and
eliminates interference. An adverse effect of shielding is the increased capacitive load.
7. The interwire capacitance between signals on different layers can be further reduced by
addition of extra routing layers.

Cross section of routing layers illustrating the use of shielding to reduce capacitive cross talk
Impact of Cross talk on Propagation Delay (With respect to CMOS):

The circuit schematic illustrates of how capacitive cross talk may result in a data-dependent
variation of the propagation delay. Assume that the inputs to the three parallel wires X, Y, and Z
experience simultaneous transitions. Wire Y (called the victim wire) switches in a direction that
is opposite to the transitions of its neighbouring signals X and Z. The coupling capacitances
experience a voltage swing that is double the signal swing, and hence represent an effective
capacitive load that is twice as large as Cc the by now well-known Miller effect.

Impact of cross talk on propagation delay

Since the coupling capacitance represents a large fraction of the overall capacitance in the deep-
submicron dense wire structures, this increase in capacitance is substantial, and has a major
impact on the propagation delay of the circuit. Observe that this is a worst-case scenario. If all
inputs experience a simultaneous transition in the same direction, the voltage over the coupling
capacitances remains constant, resulting in a zero contribution to the effective load capacitance.

The total load capacitance CL of gate Y, hence depends upon the data activities on the
neighbouring signals and varies between the following bounds:

with CGND the capacitance of node Y to ground, including the diffusion and fan out capacitances.
Design Techniques for Circuit Fabrics with Predictable delay:

With cross talk making wire-delay more and more unpredictable, a designer can choose between
a numbers of different methodology options to address the issue, some of which are,

1. Evaluate and improve: After detailed extraction and simulation, the bottlenecks in delay
are identified, and the circuit is appropriately modified.
2. Constructive layout generation: Wire routing programs take into account the effects of
the adjacent wires, ensuring that the performance requirements are met.
3. Predictable structures: By using predefined, known, or conservative wiring structures,
the designer is ensured that the circuit will meet his specifications and that cross talk will
not be a show stopper.

RESISTIVE PARASITICS:

Resistance and Reliability- Ohmic Voltage Drop:

Ohmic voltage drop on the supply reduces noise margin

Current flowing through a resistive wire results in an ohmic voltage drop that degrades the signal
levels. This is especially important in the power distribution network, where current levels can
easily reach amperes as shown below.

Consider a 2 cm long VDD or GND wire with a current of 1mA per μm width. This current is
about the maximum that can be sustained by an aluminum wire due to electromigration and
assuming a sheet resistance of 0.05 Ω/sq., the resistance of this wire (per μm width) equals 1 kΩ.
A current of 1 mA/μm would result in a voltage drop of 1 V. The altered value of the voltage
supply reduces noise margins and changes the logic levels as a function of the distance from the
supply terminals. This is demonstrated by the circuit shown above, where an inverter placed far
from the power and ground pins connects to a device closer to the supply.

The difference in logic levels caused by the IR voltage drop over the supply rails might partially
turn on transistor M1. This can result in an accidental discharging of the pre charged, dynamic
node X, or cause static power consumption if the connecting gate is static. In short, the current
pulses from the on-chip logic, memories and I/O pins cause voltage drops over the power-
distribution network and are the major source for on- chip power supply noise. Beyond causing a
reliability risk, IR drops on the supply network also impact the performance of the system. A
small drop in the supply voltage may cause a significant increase in delay.

The most obvious problem is to reduce the maximum distance between the supply pins and the
circuit supply connections which is most easily accomplished through a structured layout of the
power distribution network. A number of on- chip power distribution networks with peripheral
bonding.

Impact on the Circuit:

1. Reduced Noise Margins:

 The voltage drop caused by the parasitic resistances decreases the overall power
supplied to the circuit components (the gate in this case).
 With lower voltage levels, the circuit becomes more sensitive to noise.
 The noise margin, which defines how much noise a circuit can tolerate without
causing errors, is reduced because the effective voltage difference between logic
levels (e.g., between VDD and ground) becomes smaller.
2. Signal Integrity Issues:
 The reduced supply voltage can lead to weaker signals, slower switching times, or
incorrect logic operations.

Electromigration:

The current density (current per unit area) in a metal wire is limited due to an effect called
electromigration. A direct current in a metal wire running over a substantial time period causes a
transport of the metal ions. Eventually, this causes the wire to break or to short circuit to another
wire. This type of failure will only occur after the device has been in use for some time.
 Line Open Failure Open Failure in Contact Plug

The rate of the electromigration depends upon the temperature, the crystal structure, and the
average current density. The latter is the only factor that can be effectively controlled by the
circuit designer. Keeping the current below 0.5 to 1 mA/ μm normally prevents migration. This
parameter can be used to determine the minimal wire width of the power and ground network.
Signal wires normally carry an ac current and are less susceptible to migration. The bidirectional
flow of the electrons tends to anneal any damage done to the crystal structure. Most companies
impose a number of strict wire-sizing guidelines on their designers, based on measurements and
past experience.

Electromigration effects are proportional to the average current flow through the wire, while IR
voltage drops are a function of the peak current.

From designing point of view, at the technology level, a number of precautions can be taken to
reduce the migration risk i.e.

1. To add alloying elements (such as Cu or Tu) to the aluminum to prevent the movement of
the Al ions.
2. To control the granularity of the ions.
3. The introduction of new interconnect materials is a big help as well. For instance, the use
of Copper interconnect increases the expected lifetime of a wire with a factor of 100 over
Al.

Resistance and Performance- RC Delay:

The delay of a wire grows quadratically with its length. Doubling the length of a wire increases
its delay by a factor of four. The signal delay of long wires therefore tends to be dominated by
the RC effect. This is becoming an ever larger problem in modern technologies, which feature an
increasing average length of the global wires, at the same time that the average delay of the
individual gates is going down. This leads to the rather bizar situation that it may take multiple
clock cycles to get a signal from one side of a chip to its opposite end. Providing accurate
synchronization and correct operation becomes a major challenge under these circumstances.
Therefore the different design techniques to cope with the delay imposed by the resistance of the
wire are,

1 Better Interconnect Materials:

Use better interconnect materials when they are available and appropriate. The introduction of
silicides and Copper have helped to reduce the resistance of polysilicon (and diffused) and metal
wires, respectively, while the adoption of dielectric materials with a lower permittivity lowers
the capacitance. Both Copper and low- permittivity dielectrics have become common in
advanced CMOS technologies. Here the designer should be aware that these new materials only
provide a temporary respite of one or two generations, and do not solve the fundamental problem
of the delay of long wires. Innovative design techniques are often the only way of coping with
the latter. Sometimes, it is hard to avoid the use of long polysilicon wires. A good example of
such circumstance are the address lines in memories, which must connect to a large number of
transistor gates. Keeping the wires in polysilicon increases the memory density substantially by
avoiding the overhead of the extra metal contacts. The polysilicon- only option unfortunately
leads to an excessive propagation delay. One possible solution is to drive the word line from both
ends, as shown in Figure. This effectively reduces the worst-case delay by a factor of four.
Another option is to provide an extra metal wire, called a bypass, which runs parallel to the
polysilicon one, and connects to it every k cells as shown in figure. The delay is now dominated
by the much shorter polysilicon segments between the contacts. Providing contacts only every k
cells helps to preserve the implementation density.

Approaches to reduce the word line delay

2 Better Interconnect Strategies:

The length of the wire being a prime factor in both the delay and the energy consumption of an
interconnect wire, any approach that helps to reduce the wire length is bound to have an essential
impact. There are two wiring strategies i.e. the Manhattan- Style Routing and Diagonal- Style
Routing.
 In Manhattan style routing, interconnections are first routed along the one of the preferred
directions, followed by a connection in the other direction as shown.
 In Diagonal style routing less size of the wire length is required, on comparison to
Manhattan 29% in best case. And the use of 45°lines is ironical in integrated circuits. The
main issues of diagonal routing are its complexity, impact on tools and masking
concerns.

Manhattan vs diagonal routing

Earlier Manhattan routing was preferred because of the issues of diagonal routing inspite of its
features. Now diagonal routing is preferred due to its features i.e. less wire length and 45° lines,
its issues of complexity, impact on tools and masking concerns are easily overcomed nowadays
by using CAD tools (Computer Aided Design Tools) like Cadence. Therefore the impact on
wiring is quite tangible, a reduction of 20% in wire length, resulting in higher performance,
lower power dissipation and smaller chip area.

3. Introducing Repeaters/ Buffer Insertion for very long wires:

The most popular design approach to reducing the propagation delay of long wires is to
introduce intermediate buffers, also called repeaters, in the interconnect line as shown below.

Reducing rc interconnect delay by using repeaters

Making an interconnect line m times shorter reduces its propagation delay quadratically, and is
sufficient to offset the extra delay of the repeaters when the wire is sufficiently long. Assuming
that the repeaters have a fixed delay tpbuf , we can derive the delay of the partitioned wire.

4. Optimizing the Interconnect Architecture

When designing computer chips, wire delay—the time it takes for signals to travel along a wire
is a big problem, especially as chips get faster and wires get longer. Even if we use buffers, there
is still a limit to how fast we can send signals down long wires. This delay can slow down the
performance of the entire chip.Chips operate at very high speeds, typically with a clock that
controls how fast everything happens. Some wires, however, are so long that even with
optimizations, the signal may take much longer to travel across them This means that even
though the chip’s clock is fast, the wire itself slows things down. This limits the overall
performance of the chip.

Wire pipelining is a popular performance- improvement technique in this category which

improves the throughput performance of logic modules with long critical paths. Similar approach
can be used to increase the throughput of a wire, as is illustrated in figure below.

Wire pipelining improves the throughput of a wire

The wire is partitioned in k segments by inserting registers or latches. While this does not reduce
the delay through the wire segment, it takes k clock cycles for a signal to proceed through the
wire, it helps to increase its throughput, as the wire is handling k signals simultaneously at any
point in time. The delay of the individual wire segments can further be optimized by repeater
insertion, and should be below a single clock period.

This is only one example of the many techniques that the chip architect has at her disposal to
deal with the wire delay problem. The most important concern from this is that the wires have to
be considered early on in the design process, and can no longer be treated as an afterthought as
was most often the case in the past.
INDUCTIVE PARASITICS:

Interconnect wires also exhibit an inductive parasitic. An important source of parasitic

inductance is introduced by the bonding wires and chip packages. Even for intermediate- speed
CMOS designs, the current through the input- output connections can experience fast transitions
that cause voltage drops as well as ringing and overshooting, phenomena not found in RC
circuits. At higher switching speeds, wave propagation and transmission line effects can come
into the picture.

Inductance and Reliability- L Voltage drop

During each switching action, a transient current is sourced from (or sunk into) the supply rails
to charge (or discharge) the circuit capacitances as shown. Both VDD and VSS connections are
routed to the external supplies through bonding wires and package pins and possess a non
ignorable series inductance. Hence, a change in the transient current creates a voltage difference
between the external and internal supply voltages. This situation is especially severe at the output
pads, where the driving of the large external capacitances generates large current surges. The
deviations on the internal supply voltages affect the logic levels and result in reduced noise
margins.

Inductive coupling between external and internal supply voltages

In an actual circuit, a single supply pin serves a large number of gates or output drivers. A
simultaneous switching of those drivers causes even worse current transients and voltage drops.
As a result, the internal supply voltages deviate in a substantial way from the external ones. For
instance, the simultaneous switching of the 16 output drivers of an output bus would cause a
voltage drop of at least 1.1 V if the supply connections of the buffers were connected to the same
pin on the package. Improvements in packaging technologies are leading to ever- increasing
numbers of pins per package. Packages with up to 1000 pins are currently available.
Simultaneous switching of a substantial number of those pins results in huge spikes on the
supply rails that are bound to disturb the operation of the internal circuits as well as other
external components connected to the same supplies.

Design techniques to address L Voltage drop

1. Separate power pins for I/O pads and chip core

 I/O drivers typically require the largest switching currents, as they handle signals
going in and out of the chip.
 These drivers experience the most significant current changes when they switch states,
leading to large L(di/dt) voltage drops
 To prevent the noise and voltage fluctuations caused by these large current changes
from affecting the core logic of the chip, it is beneficial to isolate the power supplies
for the I/O pads and the chip’s internal logic
 This is done by using separate power and ground pins for:
 The I/O drivers (which handle external communication)
 The chip core (which handles the internal logic operations)
 By separating the power supplies, the switching noise generated by the I/O drivers
does not propagate to the sensitive core logic circuitry
 This isolation reduces the risk of logic errors and ensures more stable operation for the
core logic, especially in high-speed circuits where fast switching occurs.
2. Multiple power and ground pins
 I/O drivers require substantial current to switch, and when multiple drivers switch
simultaneously, it causes large current surges, leading to significant voltage drops
due to parasitic inductance
 To minimize this, designers can reduce the di/dt per supply pin by limiting the
number of I/O drivers connected to each power pin.
 Typical designs connect around five to ten drivers per power pin to distribute the
current load.
 The exact number of drivers connected to a single pin depends on factors such as:
 The switching characteristics of the drivers (how fast they switch and how
much current they draw).
 The number of gates switching simultaneously
 The rise and fall times of the signals
 By distributing the load across multiple power and ground pins, the current per
pin is reduced, lowering the L(di/dt) voltage drop
 This approach helps maintain stable supply voltages, minimizing the risk of noise
and ensuring more reliable circuit operation, particularly during high-speed
switching.
3. Careful selection of the positions of the power and ground pins on the package
  The inductance of the pins on the chip package can vary based on their physical
location
 Pins located at the corners of the package generally have substantially higher
inductance compared to those positioned closer to the center
 This higher inductance at the corners can lead to larger voltage drops due to the
L(di/dt) effect, especially during fast switching events when the current changes
rapidly.
 It is advisable to place power and ground pins closer to the center of the package
rather than at the corners, where inductance is lower
 This helps in reducing the inductive parasitic effects and ensures a more stable
power supply to the chip
 By optimizing the positions of the power and ground pins, the inductive voltage
drop across the pins can be minimized, improving the reliability of the circuit
 This careful pin placement can also help in enhancing performance, especially for
high-speed circuits where the impact of inductance is more significant.
4. Increase the rise and fall times
 When electronic signals travel from a chip to the outside world (off-chip), it's
better to make the signals change (rise and fall) as slowly as possible, within
allowed limits.
 This helps reduce problems, especially when the signals have to travel over long
distances across the chip, like under data buses.
 If you try to make signals change too fast, you need bigger components, which
take up more space on the chip
5. Use advanced packaging technologies
 Advanced packaging technologies, like surface-mount or hybrid techniques, help
make electronic components smaller and more efficient. These methods
significantly reduce the unwanted effects of capacitance and inductance (which
can cause delays or noise in the circuit)
 One example is a flip-chip package, where the chip is mounted directly onto the
circuit board using tiny solder bumps. This setup reduces the inductance (which
slows down the signal) to just 0.1 nano henries (nH), which is 50 to 100 times
smaller compared to traditional packaging methods
 In simple terms, the newer packaging methods make the connections shorter and
cleaner, leading to faster and more reliable electronic devices.
6. Adding decoupling capacitances on the board
 Adding decoupling capacitors to a circuit helps keep the power supply to a chip
steady
 These capacitors act like small energy storage units placed next to the chip
 When the power supply fluctuates (due to fast-changing signals), the capacitors
release energy to smooth out these changes and prevent voltage drops or spikes
  They also help filter out unwanted noise from the power lines, making sure the
chip receives clean, stable power, which improves its performance and reliability
7. Adding decoupling capacitances on the chip
 In high-performance circuits, where signals switch quickly, adding decoupling
capacitors directly on the chip is a common practice to stabilize the power supply
and reduce voltage fluctuations. These on-chip capacitors help ensure that the
chip gets a steady voltage, especially during fast changes in current demand
 For instance, in a typical design, around 12.5 nano farads (nF) of capacitance is
needed for every 50,000 logic gates to keep the voltage ripple (variation) under
0.25 volts. These capacitors are often made using thin layers of material (like thin
gate oxide in transistors). Essentially, a thin-oxide capacitor is like a MOS
transistor, but with both ends (drain and source) connected together to act as a
capacitor, which stores and releases charge when needed to stabilize the voltage.

Inductance and Performance—Transmission Line Effects

When circuits run very fast or when wires become long enough, the inductance of the wire starts
affecting how quickly signals can travel through the circuit. This means that transmission line
effects must be considered. These effects become significant when the time it takes for a signal
to rise or fall is similar to the time it takes the signal to travel across the wire (based on the speed
of light). Initially, these issues mainly affected the fastest digital circuits or specialized
technologies (like GaAs and SiGe). But as modern CMOS circuits become faster and more
complex, transmission line effects are also becoming a concern in CMOS design.

To reduce these effects:

Termination: Properly "terminating" the wire at the ends (with resistors or other techniques) can
help prevent signal reflections, which cause noise and delay.

Current-return path: Ensuring the current has a clear path to return is crucial for effective
termination.

Shielding: Using shields around wires that are prone to transmission line effects helps protect
them from interference and minimizes signal distortion.

These techniques help ensure that signals travel cleanly and quickly without interference.

Termination:

• In circuits where transmission line effects are significant, such as when signals travel
through long wires or at high speeds, proper termination is key to minimizing issues like
ringing and slow signal delays.
• Termination refers to adding a resistor at either the source (where the signal starts) or
the destination (where the signal ends). This resistor should match the characteristic
impedance (Z₀) of the transmission line. When done correctly, termination ensures the
signal travels smoothly along the wire without bouncing back or causing delays.

• There are two common methods of termination:

Series termination: A resistor is placed at the source of the signal. This helps
prevent reflections by slowing the signal just enough so that it matches the impedance of
the line.

Parallel termination: A resistor is placed at the destination, which absorbs any

reflections and prevents them from bouncing back down the line.

Matched termination scenarios for wires behaving as transmission lines: (a) series termination at the source,
(b) parallel termination at the destination

 The two scenarios- series and parallel termination as shown are depicted in figure. Series
termination requires that the impedance of the signal source is matched to the connecting
wire. This approach is appropriate for many CMOS designs, where the destination load is
purely capacitive. The impedance of the driver inverter can be matched to the line by
careful transistor sizing.

• Matching the load impedance to the line’s impedance results in the fastest signal
response, reducing unwanted effects like ringing and improving overall performance.

Signal and Return Path:

When you send a current through a wire, there must be a return path for the current to
complete the circuit. The return current flows in the opposite direction. How this return
current flows is very important because it affects how well the signal travels through the
wire. If it's not managed properly, the signal can get distorted or interfere with other signals.
Shielding

On a circuit board or chip, we can do something similar by placing ground planes or shielding
wires around the signal wires. This helps ensure that the signal behaves predictably and isn’t
affected by other signals or noise.

• Benefit: Shielding makes the signal more reliable and reduces interference.

• Challenge: It takes up more space on the board or chip, which can be expensive. Also, as
circuits get faster and more complex, engineers will need better tools to simulate and
manage these connections to ensure they work correctly. In short, shielding helps keep
signals clean and predictable, but it requires careful planning and extra space.