Machine Translated by Google

SH68F90

Enhanced8051 microcontroller

1.Characteristics _

ÿ 8-bit microcontroller based on 8051 instruction pipeline ÿ Built-in analog circuit power regulator (VDDR) -

structure ÿ Flash ROM: 64K bytes ÿ Output voltage: 3.3V/70mA ÿ

RAM: internal 256 bytes, external 4096 bytes ÿ 5Byte Built-in low voltage reset function (code option) - LVR
voltage: 2.1V - LVR
readable MCU identification code ÿ
voltage: 2.8V - LVR
The maximum CPU frequency
voltage: 3.7V - LVR
is 24M ÿ Working voltage: VUSB = 2.0V - 5.5V
voltage: 4.1V ÿUniversal
ÿ Oscillator (code option): - Internal
Serial Bus (USB) - Compatible with
low frequency RC oscillator: 128KHz -
USB2.0 (full speed 12Mbps) transmission speed -
Internal high frequency RC oscillator:
Supports control, interrupt and batch data
24MHz - PLL oscillator: 4x
transmission - Supports 3 endpoints (EP0, EP1,
ÿ 58 CMOS bidirectional I/O pins,
EP2) ÿ 16 levels of power Optional low voltage detection
- 6 high-current Sink I/O (380mA, GND+1.0V) - 4 PWM
module (LPD) ÿ CPU
(PWM3) high-current sink ports (50mA, GND+0.5V) - 4 groups of PWM
machine cycle: 1 oscillation cycle
(PWM0/PWM1/PWM2/PWM4) large Current drive
ÿ Watchdog timer (WDT) (code option) ÿ Preheat
(25mA, VDD-0.7) - Other
counter ÿ Low power
Normal I/O
operating mode: - Idle mode
ÿ I/O built-in pull-up resistor (30kÿ) ÿ 1 16-
- Power down
bit timer/counter ÿ 4 PWMs, of which
mode ÿ Flash
PWM0, PWM1, and PWM2 each contain 6 comparison units, PWM3 has 4
type ÿ Package:
comparison units, and PWM4 has 3 comparison unit

ÿ SPI interface (master/slave mode)

-LQFP64
ÿ EUART0 -TQFP48
ÿ 13 interrupt sources: -LQFP48
- Timer 2, PWM0, PWM1, PWM2, PWM3, PWM4 - External interrupt INT2, -Wafer

INT3, INT40 - INT47

- SPI, EUART0, SCM, LPD, USB

2. Overview

SH68F90 is a high-speed and high-efficiency 8051 compatible microcontroller. At the same oscillation frequency, it has the advantage of running faster than the traditional 8051 chip.

SH68F90 retains most of the features of the standard 8051 chip. These features include built-in 256 bytes of RAM, external interrupts INT2, INT3 and INT4. also,
SH68F90 also integrates external 4096 bytes of RAM. The microcontroller also includes a 64 Kbyte Flash block suitable for program storage.

SH68F90 not only integrates standard communication modules such as SPI/USB/UART, but also integrates modules such as PWM timer with built-in comparison function. In order

to achieve high reliability and low power consumption, SH68F90 has built-in watchdog timer, low voltage reset function and system clock monitoring function. In addition, SH68F90 also provides 2

low-power power-saving modes.

1 V2.0
Machine Translated by Google

SH68F90

3. Block diagram

VDD
Reset circuit RST
Power Pipelined 8051 architecture

Watch Dog
64K Bytes
Flash ROM

Port 7
Configuration I/Os
Internal 256 Bytes P7.0~P7.7
External 4096Bytes
(Exclude System
Port 6
Register)
Configuration I/Os
P6.0~P6.7
Timer2 (16bit)
Port 5
Configuration I/Os
P5.0~P5.7
PWM0
PWM1 Port 4
PWM2 Configuration I/Os
PWM3 P4.0~P4.7
PWM4
Port 3
Configuration I/Os
External Interrupt P3.0~P3.5

Port 2
Configuration I/Os
P2.0 ~ P2.5

Port 1
Configuration I/Os
P1.0 ~ P1.5

Port 0
Configuration I/Os
P0.0 ~ P0.7

Internal SPI
Oscillator

USB EUART

LPD Jtag ports

(for debug)

2
Machine Translated by Google

SH68F90

4.Pin configuration
4.1 64-pin LQFP package

P4.1/ P4.0/ P3.5/ P3.3/ P3.1/

P3.0/ P2.5/ P2.4/ P2.3/ P2.2/ P2.1/ P2.0/ P1.5/ P1.4/
P3.4/ P3.2/

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

INT42/P4.2 49 32 P1.3/PWM23

INT43/P4.3 50 31 P1.2/PWM22

TCK/P4.4 51 30 P1.1/PWM21

P4.5 52 29 P1.0/PWM20

P4.6 53 28 P0.7/INT3

PWM33/P4.7 54 27 P0.6

TDI/PWM32/P7.7 55 26 P0.5/INT2

TMS/PWM31/P7.6 56 25 P0.4

SWE/PWM30/P7.5 57
SH68F90 twenty four
P0.3

SCK/P7.4 58 twenty three P0.2/RESET

SS/INT45/P7.3 59 twenty two P0.1/D+

MOSI/INT44/P7.2 60 twenty one P0.0/D-

MISO/INT41/P7.1 61 20 VDDR

TDO/INT40/P7.0 62 19 GND

P6.0 63 18 VUSB

NC 64 17 P5.7

12345 6 7 8 9 10 11 12 13 14 15 16

P6.2 P6.3 P6.4 P6.5 P6.6 P6.7

P6.1 GND
GND

TXD/ RXD/

INT46/ INT47/

PWM40/ PWM41/ PWM42/

LQFP64

Note: In the pin naming, the pin function written on the outermost side has the highest priority, and the pin function written on the innermost side has the lowest priority (see the pin configuration diagram). When a pin is occupied by a high-priority function, even if the low-priority function is allowed, it cannot be used as a pin for the low-priority function. Only when software disables the pin's high-priority function can the corresponding pin be released for use as a low-priority port.

3
Machine Translated by Google

SH68F90
4.2 48-pin TQFP package

P3.3/ P3.0/ P2.5/ P2.4/ P2.3/ P2.2/ P2.1/ P2.0/ P1.5/

P3.4/ P3.1/
P3.2/

36 35 34 33 32 31 30 29 28 27 26 25

MISO_M/PWM05/P3.5 37 twenty four

P1.4/PWM24

TCK/P4.4 38 twenty three P1.3/PWM23

PWM33/P4.7 39 twenty two P1.2/PWM22

TDI/PWM32/P7.7 40 twenty one

P1.1/PWM21

TMS/PWM31/P7.6 41 20 P1.0/PWM20

SWE/PWM30/P7.5 42 19 P0.4
SH68F90
SS/INT45/P7.3 43 18 P0.3

MOSI/INT44/P7.2 44 17 P0.2/RESET

MISO/INT41/P7.1 45 16 P0.1/D+

TDO/INT40/P7.0 46 15 P0.0/D-

P6.0 47 14 VDDR

P6.1 48 13 GND

1 2 345 6 7 8 9 10 11 12

P6.2 P6.3 P6.4 P6.5

TXD/ RXD/

INT46/ INT47/

PWM40/ PWM41/ PWM42/

TQFP48

Note: In the pin naming, the pin function written on the outermost side has the highest priority, and the pin function written on the innermost side has the lowest priority (see the pin configuration diagram). When a pin is occupied by a high-priority function, even if the low-priority function is allowed, it cannot be used as a pin for the low-priority function. Only when software disables the pin's high-priority function can the corresponding pin be released for use as a low-priority port.

4
Machine Translated by Google

SH68F90
4.3 48-pin LQFP package

P3.3/ P3.0/ P2.5/ P2.4/ P2.3/ P2.2/ P2.1/ P2.0/ P1.5/

P3.4/ P3.1/
P3.2/

36 35 34 33 32 31 30 29 28 27 26 25

MISO_M/PWM05/P3.5 37 twenty four

P1.4/PWM24

TCK/P4.4 38 twenty three P1.3/PWM23

PWM33/P4.7 39 twenty two P1.2/PWM22

TDI/PWM32/P7.7 40 twenty one

P1.1/PWM21

TMS/PWM31/P7.6 41 20 P1.0/PWM20

SWE/PWM30/P7.5 42 19 P0.4
SH68F90
SS/INT45/P7.3 43 18 P0.3

MOSI/INT44/P7.2 44 17 P0.2/RESET

MISO/INT41/P7.1 45 16 P0.1/D+

TDO/INT40/P7.0 46 15 P0.0/D-

P6.0 47 14 VDDR

P6.1 48 13 GND

1 2 345 6 7 8 9 10 11 12

P6.2 P6.3 P6.4 P6.5

TXD/ RXD/

INT46/ INT47/

PWM40/ PWM41/ PWM42/

LQFP48

Note: In the pin naming, the pin function written on the outermost side has the highest priority, and the pin function written on the innermost side has the lowest priority (see the pin configuration diagram). When a pin is occupied by a high-priority function, even if the low-priority function is allowed, it cannot be used as a pin for the low-priority function. Only when software disables the pin's high-priority function can the corresponding pin be released for use as a low-priority port.

5
Machine Translated by Google

SH68F90

5.Pin description

Pin number type illustrate

I/O port

P0.0 - P0.7 I/O 8-bit bidirectional I/O port

P1.0 - P1.5 I/O 6-bit bidirectional I/O port
P2.0 - P2.5 I/O 6-bit bidirectional I/O port
P3.0 - P3.5 I/O 6-bit bidirectional I/O port
P4.0 - P4.7 I/O 8-bit bidirectional I/O port
P5.0 - P5.7 I/O 8-bit bidirectional I/O port
P6.0 - P6.7 I/O 8-bit bidirectional I/O port
P7.0 - P7.7 I/O 8-bit bidirectional I/O port

timer

T2 I Timer 2 external clock input

T2EX I Timer 2 external event input

PWM controller

PWM0 O 16-bit PWM timer output pin

PWM1 O 16-bit PWM timer output pin
PWM2 O 16-bit PWM timer output pin
PWM3 O 16-bit PWM timer output pin
PWM4 O 16-bit PWM timer output pin

SPI

MOSI I/O SPI master output slave input pin

MISO I/O SPI master input slave output pins
SCK I/O SPI serial clock pin
SS I SPI slave select pin

EUART

RXD I EUART0 data input pin

TxD O EUART0 data output pin

Interrupt&Reset&Clock&Power

INT2-INT3 I External interrupt 2 - 3

INT40-INT47 I External interrupt 40 - 47

If this pin is held low for more than 10µs, the CPU will reset. Since there is a built-in 100kÿ pull-up resistor connected to
RESET I
VDD, so only an external capacitor can be connected to achieve power-on reset.

VDDR P power regulator output (3.3V)

VUSB P Power supply (2.0 - 5.5V)

programming interface

TDO O Debug interface: test data output

TMS I debugging interface: test mode selection
TDI I debugging interface: test data input
TCK I debugging interface: test clock input

Single-wire emulation interface

SWE(P7.5) I/O single-wire emulation interface

Note: when P7.0/ P7.6/ P7.7/ P4.4 When used as a debugging interface, P7.0/ P7.6/ P7.7/ P4.4 The original functionality is disabled.

6
Machine Translated by Google

SH68F90
6. SFR image
SH68F90 has built-in 256 bytes of direct addressing registers, including general-purpose data memory and special function registers (SFR). The SFRs of SH68F90 include the following types:

CPU core registers: ACC, B, PSW, SP, DPL, DPH

CPU core enhancement registers: AUXC, DPL1, DPH1, INSCON, XPAGE

Power supply clock control register: PCON, SUSLO

Flash register: IB_OFFSET, IB_DATA, IB_CON1, IB_CON2, IB_CON3, IB_CON4, IB_CON5, FLASHCON

Data page control register: XPAGE

Watchdog timer register: RSTSTAT

System clock control register: CLKCON, PLLCON

System clock calibration registers: CLKLO, CLKRC0H, CLKRC0L, CLKRC1H, CLKRC1L

Interrupt register: IEN0, IEN1, IEN2, IENC, IPH0, IPL0, IPH1, IPL1, EXF0, EXF1, EXCON

I/O port register: P0, P1, P2, P3, P4, P5, P6, P7
P0CR, P1CR, P2CR, P3CR, P4CR, P5CR, P6CR, P7CR
P0PCR, P1PCR, P2PCR, P3PCR, P4PCR, P5PCR, P6PCR, P7PCR
P1DRV, P2DRV, P3DRV, P5DRV, DRVCON, MAPPING

Timer register: T2CON, TH2, TL2

Power Regulator Register: REGCON

SPI register: SPCON, SPSTA, SPDAT

UART register: SCON, SBUF, SADDR, SADEN, SBRTL, SBRTH, SFINE

PWM register: PWMxyCON, PWMxyPERDH, PWMxyPERDL, PWMxyDUTYH, PWMxyPERDL

LPD register: LPDCON,LPDSEL

USB register: USBCON, USBIF1, USBIF2, USBIE1, USBIE2, USBADDR, EP0CON, EP1CON,
EP2CON, IEP0CNT, IEP1CNT, IEP2CNT, OEP0CNT, OEP1CNT, OEP2CNT

7
Machine Translated by Google

SH68F90
Table 6.1 C51 core SFRs

POR/WDT/LVR
symbolic address name No. 7 No. 6 No. 5 No. 4 No. 3 No. 2 No. 1 No. 0
/PIN reset value

ACC E0H accumulator 00000000 ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0

B F0H B register 00000000 B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0

AUXC F1H C register 00000000 C.7 C.6 C.5 C.4 C.3 C.2 C.1 C.0

PSW D0H program status word 00000000 CY AC F0 RS1 RS0 OV F1 P

SP 81H Stack 00000111 SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0

DPL 82H pointer data pointer low byte 00000000 DPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0

DPH 83H Data pointer high byte 00000000 DPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0

DPL1 84H Data pointer 1 low byte 00000000 DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0

DPH1 85H Data pointer 1 high byte 00000000 DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0

INSCON 86H Data pointer selection ----00-0 - - - - DIV MUL - DPS

Table 6.2 Power supply clock control SFRs

POR/WDT/LVR
symbolic address name No. 7 No. 6 No. 5 No. 4 No. 3 No. 2 No. 1 No. 0
/PIN reset value

PCON 87H power control 000-0000 SMOD SSTAT SSTAT1 - GF1 GF0 PD IDL

SUSLO 8EH Power control protection word 00000000 SUSLO.7 SUSLO.6 SUSLO.5 SUSLO.4 SUSLO.3 SUSLO.2 SUSLO.1 SUSLO.0

Table 6.3 Flash control SFRs

POR/WDT/LVR
symbolic address name No. 7 No. 6 No. 5 No. 4 No. 3 No. 2 No. 1 No. 0
/PIN reset value

IB_OFF FBH 00000000 IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF IB_OFF
Programmable flash low byte offset
SET SET.7 SET.6 SET.5 SET.4 SET.3 SET.2 SET.1 SET.0

IB_DATA FCH Programmable flash data 00000000 IB_DATA.7 IB_DATA.6 IB_DATA.5 IB_DATA.4 IB_DATA.3 IB_DATA.2 IB_DATA.1 IB_DATA.0

IB_CON1 F2H register flash control 00000000 IB_CON1.7 IB_CON1.6 IB_CON1.5 IB_CON1.4 IB_CON1.3 IB_CON1.2 IB_CON1.1 IB_CON1.0

register 1 flash control register 2 ----0000 - - - -

IB_CON2 F3H IB_CON2.3 IB_CON2.2 IB_CON2.1 IB_CON2.0

flash control register 3 ----0000 - - - -

IB_CON3 F4H IB_CON3.3 IB_CON3.2 IB_CON3.1 IB_CON3.0

flash control register 4 ----0000 - - - -

IB_CON4 F5H IB_CON4.3 IB_CON4.2 IB_CON4.1 IB_CON4.0

flash control register 5 ----0000 - - - -

IB_CON5 F6H IB_CON5.3 IB_CON5.2 IB_CON5.1 IB_CON5.0
XPAGE F7H Programming address selection 00000000 XPAGE.7 XPAGE.6 XPAGE.5 XPAGE.4 XPAGE.3 XPAGE.2 XPAGE.1 XPAGE.0

FLASHCON A7H register flash control register -------0 - - - - - - - FAC

8
Machine Translated by Google

SH68F90
Table 6.4 WDT SFR

POR/WDT/LVR
symbolic address name No. 7 No. 6 No. 5 No. 4 No. 3 No. 2 No. 1 No. 0
/PIN reset value

RSTSTAT B1H watchdog timer control register 0-000000* WDOF - PORF LVRF CLRF WDT.2 WDT.1 WDT.0
*
Notice: Indicates reset decisions for different situationsRSTSTAT The reset value in the register, seeWDT chapter

Table 6.5 Clock Control SFR

POR/WDT/LVR
symbolic address name No. 7 No. 6 No. 5 No. 4 No. 3 No. 2 No. 1 No. 0
/PIN reset value

CLKCON B2H System clock selection -11-00-- - CLKS1 CLKS0 - HFON FS - -

PLLCON BCH PLL clock control register -----000 - - - - - PLLSTA PLLON PLLFS

CLKLO BDH Internal RC correction control register 0---0000 CLKRCEN - - - CLKLO.3 CLKLO.2 CLKLO.1 CLKLO.0

CLKRC0H C6H Internal RC correction register -----uuu - - - - - CLKRC0.10 CLKRC0.9 CLKRC0.8

CLKRC0L BEH Internal RC correction register uuuuuuuu CLKRC0.7 CLKRC0.6 CLKRC0.5 CLKRC0.4 CLKRC0.3 CLKRC0.2 CLKRC0.1 CLKRC0.0

CLKRC1H C7H Internal RC correction initial value register -----uuu - - - - - CLKRC1.10 CLKRC1.9 CLKRC1.8

CLKRC1L BFH Internal RC correction initial value register uuuuuuuu CLKRC1.7 CLKRC1.6 CLKRC1.5 CLKRC1.4 CLKRC1.3 CLKRC1.2 CLKRC1.1 CLKRC1.0

Table 6.6 Interrupt SFRs

POR/WDT/LVR
symbolic address name No. 7 No. 6 No. 5 No. 4 No. 3 No. 2 No. 1 No. 0
/PIN reset value

IEN0 A8H Interrupt enable control 0 00000000 EA ESPI ELPD ESCM EX2 EX3 EX4 ET2

IEN1 A9H Interrupt enable control 1 -0000000 - ES0 EPWM4 EPWM3 EPWM2 EPWM1 EPWM0 EUSB

IENC BAH Interrupt channel enable control 00000000 EXS47 EXS46 EXS45 EXS44 EXS43 EXS42 EXS41 EXS40

IPH0 B4H Interrupt priority control high bit 0 -0000000 - PSPIH PLPDH PSCMH PX2H PX3H PX4H PT2H

IPL0 B8H Interrupt priority control low bit 0 -0000000 - PSPIL PLPDL PSCML PX2L PX3L PX4L PT2L

IPH1 B5H Interrupt priority control high bit 1 -0000000 - PS0H PPWM4H PPWM3H PPWM2H PPWM1H PPWM0H PUSBH

IPL1 B9H Interrupt priority control low bit 1 -0000000 - PS0L PPWM4L PPWM3L PPWM2L PPWM1L PPWM0L PUSBL

EXF0 88H External interrupt register 0 00000000 IT4.1 IT4.0 IT3.1 IT3.0 IT2.1 IT2.0 IE3 IE2

EXF1 E8H External interrupt register 1 00000000 IF47 IF46 IF45 IF44 IF43 IF42 IF41 IF40

EXCON 8BH External interrupt sampling control 00000000 I1PS1 I1PS0 I1SN1 I1SN0 I0PS1 I0PS0 I0SN1 I0SN0

9
Machine Translated by Google

SH68F90
Table 6.7 Port SFRs
POR/WDT/LVR
symbolic address name No. 7 No. 6 No. 5 No. 4 No. 3 No. 2 No. 1 No. 0
/PIN reset value

P0 80H 8-bit port 0 00000000 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
P1 90H 8-bit port 1 --000000 - - P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
P2 98H 8-bit port 2 --000000 - - P2.5 P2.4 P2.3 P2.2 P2.1 P2.0

P3 A0H 8-bit port 3 --000000 - - P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
P4 B0H 8-bit port 4 00000000 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0

P5 B6H 8-bit port 5 00000000 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0

P6 C0H 8-bit port 6 00000000 P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0
P7 F8H 8-bit port 7 00000000 P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0

P0CR E1H Port 0 input/output direction control 00000000 P0CR.7 P0CR.6 P0CR.5 P0CR.4 P0CR.3 P0CR.2 P0CR.1 P0CR.0

P1CR E2H Port 1 input/output direction control --000000 - - P1CR.5 P1CR.4 P1CR.3 P1CR.2 P1CR.1 P1CR.0

P2CR E3H Port 2 input/output direction control --000000 - - P2CR.5 P2CR.4 P2CR.3 P2CR.2 P2CR.1 P2CR.0

P3CR E4H Port 3 input/output direction control --000000 - - P3CR.5 P3CR.4 P3CR.3 P3CR.2 P3CR.1 P3CR.0

P4CR E5H Port 4 input/output direction control 00000000 P4CR.7 P4CR.6 P4CR.5 P4CR.4 P4CR.3 P4CR.2 P4CR.1 P4CR.0

P5CR E6H Port 5 input/output direction control 00000000 P5CR.7 P5CR.6 P5CR.5 P5CR.4 P5CR.3 P5CR.2 P5CR.1 P5CR.0

P6CR E7H Port 6 input/output direction control 00000000 P6CR.7 P6CR.6 P6CR.5 P6CR.4 P6CR.3 P6CR.2 P6CR.1 P6CR.0

P7CR D1H Port 7 input/output direction control 00000000 P7CR.7 P7CR.6 P7CR.5 P7CR.4 P7CR.3 P7CR.2 P7CR.1 P7CR.0

P0PCR E9H Port 0 internal pull-up enabled 00000000 P0PCR.7 P0PCR.6 P0PCR.5 P0PCR.4 P0PCR.3 P0PCR.2 P0PCR.1 P0PCR.0

P1PCR EAH Port 1 internal pull-up allows --000000 - - P1PCR.5 P1PCR.4 P1PCR.3 P1PCR.2 P1PCR.1 P1PCR.0

P2PCREBH Port 2 internal pull-up allows --000000 - - P2PCR.5 P2PCR.4 P2PCR.3 P2PCR.2 P2PCR.1 P2PCR.0

P3PCR ECH Port 3 internal pull-up allows --000000 - - P3PCR.5 P3PCR.4 P3PCR.3 P3PCR.2 P3PCR.1 P3PCR.0

P4PCR EDH Port 4 internal pull-up allows 00000000 P4PCR.7 P4PCR.6 P4PCR.5 P4PCR.4 P4PCR.3 P4PCR.2 P4PCR.1 P4PCR.0

P5PCREEH Port 5 internal pull-up allows 00000000 P5PCR.7 P5PCR.6 P5PCR.5 P5PCR.4 P5PCR.3 P5PCR.2 P5PCR.1 P5PCR.0

P6PCREFH Port 6 internal pull-up allows 00000000 P6PCR.7 P6PCR.6 P6PCR.5 P6PCR.4 P6PCR.3 P6PCR.2 P6PCR.1 P6PCR.0

P7PCR D9H Port 7 internal pull-up allows 00000000 P7PCR.7 P7PCR.6 P7PCR.5 P7PCR.4 P7PCR.3 P7PCR.2 P7PCR.1 P7PCR.0

DRVCON 8CH Port driver control register 00--0000 DRVEN.1 DRVEN.0 - - DRVCON.3 DRVCON.2 DRVCON.1 DRVCON.0

P1DRV A5H Port driver selection register -----00 - - - - - - P1DRV.1 P1DRV.0

P2DRV A6H Port driver selection register -----00 - - - - - - P2DRV.1 P2DRV.0

P3DRVBBH Port driver selection register -----00 - - - - - - P3DRV.1 P3DRV.0

P5DRV 8DH Port driver selection register -----00 - - - - - - P5DRV.1 P5DRV.0

MAPPING 8AH Communication port mapping control register 00000000 MACON.7 MACON.6 MACON.5 MACON.4 MACON.3 MACON.2 MACON.1 MACON.0

10