IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO.

7, JULY 2012 3363

Digitally Implemented Average Current-Mode

Control in Discontinuous Conduction Mode
PFC Rectifier
Jong-Won Shin, Student Member, IEEE, and Bo-Hyung Cho, Fellow, IEEE

Abstract—This paper proposes a digital average current-mode and inherent current sharing capability are also advantageous
control method in discontinuous conduction mode (DCM) power when interleaving more than one module [3], [4], while vari-
factor correction rectifier. The proposed control technique does able switching frequency of CRM requires maximum frequency
not estimate, but directly senses the average value of the inductor
current in each switching cycle. It is implemented by means of limitation and sophisticated interleaving technique.
a conventional current sensing circuit and a microcontroller. The Distorted input current, however, can be the major drawback
calculation burden of the microcontroller is the same with that of to DCM if the control method is not properly considered. As
conventional two-loop-controlled converter because the additional a conventional control law for DCM, constant-duty-cycle con-
calculation process is not required. The control method achieves trol (also referred to as open-loop control or voltage follower
lower total harmonic distortion and higher power factor than the
conventional technique. Experimental results with a 200-W proto- control) is widely used for its simplicity because the controller
type verify the feasibility and performance of the proposed control needs a low-bandwidth voltage loop and no current loop, which
method. does not require current sensing and control circuit [5]–[7]. The
Index Terms—Average current-mode control, digital control, average inductor current is naturally distorted with this control
discontinuous conduction mode (DCM), power factor correction method because the duty cycle is virtually fixed and not com-
(PFC), variable-duty-cycle control. pensated within a half line cycle. In addition, nonzero inductor
current at the beginning of the switching cycle, which is per-
turbed by the resonance between the parasitic capacitance of
I. INTRODUCTION the switch and main inductor, is not controlled and may act as
ISTORTED line current from nonresistive load causes another source of input current distortion [8].
D problems such as power loss, noise, line voltage distortion,
and reduced line utilization [1]. Regulations on harmonic current
A typical solution used to reduce the current distortion of
the DCM PFC rectifier is variable-duty-cycle control, which
limit such as IEC61000-3-2 [2] and the internal specifications of is the counterpart of the conventional constant-duty-cycle con-
many electronic equipment manufacturers are generally consid- trol [9]–[14]. The variable-duty-cycle control not only over-
ered to alleviate these problems. Active power factor correction comes the problem of distorted input current [9], but also miti-
(PFC) front-end rectifier based on switch-mode power supply gates the output voltage ripple and rms inductor current [10]. It is
with its input filter is one solution to minimizing the harmonic generally realized by modifying the voltage loop of the constant-
current and meeting the regulations. By employing proper con- duty-cycle control by utilizing an input voltage feedforward and
trol scheme, the active PFC rectifier emulates the resistive load additional calculation circuit. An analog calculation circuitry
and achieves low line current distortion. for square-root operation and multiplication is added in [10]
In low to medium power application, where rms inductor and [11]. As the tradeoff of the decreased current distortion,
current is fairly low, discontinuous conduction mode (DCM) the control circuits become complicated. Ye and Jovanović [12]
as well as critical conduction mode (CRM, also referred to as digitally realized the analog control scheme in [11] and elimi-
boundary conduction mode or transition mode) is widely used nated complicated analog calculation circuits, while the calcu-
due to its low switching loss, low diode reverse recovery cur- lation burden of digital controller is increased. One-cycle con-
rent, and small inductor size. Its constant switching frequency trol method shown in [9] enables the variable-duty-cycle control
with the two resettable integrators and input voltage feedforward
network instead of the square-root operator and multiplier. Syn-
Manuscript received July 28, 2011; revised November 8, 2011; accepted thesizing a certain harmonic component of the line frequency in
December 14, 2011. Date of current version April 3, 2012. This paper was the voltage loop is another modification for variable-duty-cycle
presented at the Applied Power Electronics Conference 2011, Fort Worth, TX, control, which requires additional phase detector and phase-
March 6–10, 2011 and was selected for the Presentation Award. This work was
supported by the New and Renewable Energy Program of the Korea Institute locked loop for line input voltage [13], [14]. The common fea-
of Energy Technology Evaluation and Planning (KETEP) funded by Korea ture of the aforementioned realizations of variable-duty-cycle
Government Ministry of Knowledge Economy under Grant 20104010100490. control for DCM PFC rectifier is that the average value of the
Recommended for publication by Associate Editor T. Suntio.
The authors are with the School of Electrical Engineering and Computer inductor current is not sensed but estimated, which leads to
Science, Seoul National University, Gwanak-gu, Seoul 151-744, Korea (e-mail: complicated control circuits or the calculation algorithm. Fur-
nf84@snu.ac.kr; bhcho@snu.ac.kr). thermore, these implementations cannot eliminate the current
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. distortion caused by the perturbed initial inductor current in a
Digital Object Identifier 10.1109/TPEL.2011.2180927 unit switching period as explained in [8].
0885-8993/$26.00 © 2011 IEEE
3364 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 7, JULY 2012

Instead of modifying the voltage loop, adding a current loop

with an inductor current sensing circuit is considered as an al-
ternative to implementing variable-duty-cycle control of DCM
PFC rectifier. The current loop can effectively suppress current
distortion by the initial inductor current perturbation [15]. How-
ever, digitally sampling the inductor current in DCM operation
is not as straightforward as it is in continuous conduction mode
(CCM) [16]. In DCM, the sampled inductor current needs to be
corrected to properly represent the average inductor current per
switching period [17], [18]. The digital controller should deviate
the sampling instant within the switching period and calculate
a correction factor to determine the average inductor current,
which consumes considerable resources of the controller. Sam-
pling the inductor current more than once in a switching cycle
may help to achieve precise average inductor current, though it
requires a high-performance A/D converter for high-rate sam-
pling [19].
In this paper, an average current-mode control for DCM PFC
rectifier is digitally implemented to realize the variable-duty-
cycle control. With a direct sensing of the average inductor
current, the high-bandwidth current loop dramatically reduces
Fig. 1. Proposed control technique applied to the PFC rectifier for digital
the input current distortion. It uses the conventional sensing average current-mode control.
circuit and fixed sampling instant to sample the average in-
ductor current. The sampling occurs once per switching cycle,
which does not need high-rate sampling A/D converter. The
control algorithm of the proposed control implementation re-
quires the same calculation burden with that of conventional
two-loop-controlled converter, and additional computation such
as correction factor calculation is not necessary.
This paper consists of the following sections. In Section II,
circuit configuration, mode analysis, and operation of the sens-
ing circuit as well as the two-loop control strategy are given.
With the mathematical expression of properly controlled induc-
tor current shape, it is explained how the variable-duty-cycle
control can achieve lower current distortion than constant-duty-
cycle control. Section III illustrates design procedure of the pro-
posed control implementation. It includes the design of boost
inductance, sensing capacitance, and digitally realized control
loops. Experimental results with 200-W prototype hardware are
presented in Section IV. Conclusions are presented in Section V.

II. CONTROL TECHNIQUE FOR DCM PFC RECTIFIER

A. Operation of Average Sensing Circuit
The proposed control technique follows the general structure
of the conventional two-loop control to build an average current-
mode control, as shown in Fig. 1. The average sensing circuit,
the shaded box in Fig. 1, gives the average inductor current
Fig. 2. Average sensing circuit. (a) Circuit structure. (b) Operational
in each switching cycle to establish the current-mode control. waveforms.
The sampling of the average inductor current occurs once in a
switching period like other controller inputs such as rectified
input voltage and output voltage. It does not need high-rate circuit utilized in charge current-mode control [20], but its oper-
sampling, which samples twice or more per switching period; ation differs in the proposed control. In the charge current-mode
thus, it can save the resources of the digital controller. control, the sensing capacitor voltage vC s represents the aver-
Circuit configuration and operational waveform of the aver- age switch current per switching cycle by integrating the switch
age sensing circuit are shown in Fig. 2. As shown in Fig. 2(a), current during ON-time. The voltage is reset to zero right af-
the circuit looks the same as the conventional current sensing ter the main switch turns off by the inversed main gate signal.
SHIN AND CHO: DIGITALLY IMPLEMENTED AVERAGE CURRENT-MODE CONTROL IN DISCONTINUOUS CONDUCTION MODE 3365

Fig. 3. Comparison of current waveform shapes. (a) Average current-mode-controlled CCM. (b) Constant-duty-cycle-controlled DCM. (c) Variable-duty-cycle-
controlled DCM.

In the proposed control, on the other hand, the same circuit is B. Current Waveforms in DCM PFC Rectifier
utilized to integrate not the switch current, but both the switch Fig. 3 compares the inductor current waveforms of average
and the diode current. The integrating interval of the sensing
current-mode-controlled CCM, constant-duty-cycle-controlled
circuit is extended to near the end of the switching cycle by de- DCM, and variable-duty-cycle-controlled DCM over a half line
laying the timing of the reset signal. Fig. 2(b) shows the typical period. The continuous-time-domain current waveforms such
waveform of the proposed average sensing circuit operation in
as ipk (t) and iavg (t) in Fig. 3 are the approximated ones of the
DCM PFC rectifier. vg s , iL , reset, and TS are the gate signal for discrete-time-domain waveforms ipk [k] and iavg [k], assuming
main switch, the inductor current, the gate signal for auxiliary that the switching frequency of the rectifier is much higher
switch Qaux in average sensing circuit, and the switching pe-
than the line frequency. The waveforms of average current-
riod, respectively. d1 and d2 are the duty ratios for the switch mode-controlled CCM PFC rectifier in Fig. 3(a) resemble the
conduction interval and diode conduction interval in the power sinusoid of the line voltage because the switching ripple of
stage. To take advantage of the analog integrating circuit and
iL is relatively small. However, unlike in CCM rectifier, the
avoid the high-rate sampling, the circuit integrates the scaled envelope of the inductor current in DCM PFC rectifier should
inductor current in the sensing capacitor CS and samples vC s
not look like a sinusoid to demonstrate low current distortion.
once in the switching cycle. In the first interval in kth switching
In Fig. 3(b), constant-duty-cycle control constructs the envelope
cycle, kTS < t < t1 , the main switch is in ON-state. iL increases of the inductor current ipk (t) to be sinusoidal. However, the
linearly and vC s increases in parabolic way because the linear
resultant filtered inductor current or the line current iavg (t) is
term of iL is integrated, as expressed in the following:
highly distorted. Analysis of line current distortion according
 t to line voltage in constant-duty-cycle-controlled DCM is given
1
vC s (t) = iL (t)dt. (1) in [4]. In contrast to Fig. 3(b), Fig. 3(c) shows that in variable-
nCS k T S
duty-cycle-controlled DCM, iavg (t) follows the sinusoidal curve
In (1), n is the turn ratio of the current transformer. In the second though ipk (t) does not.
interval, t1 < t < t2 , the main switch is in OFF-state. iL decreases If the average inductor current per switching cycle is con-
and the sign of the parabolic curve of vC s is inverted. In the third trolled to be proportional to the sinusoidal input voltage by the
interval, t2 < t < (k + 1)TS , of which the time duration is d3 TS , variable-duty-cycle control, ipk (t) can be derived from the duty
iL becomes zero and the sampled value vC s [k] fully represents ratios d1 and d2 , as expressed in (3) and (4)
the average inductor current, as follows:
  Lipk (t)
 (k +1)T S d1 = (3)
TS 1 TS |vin (t)| TS
vC s [k] = iL (t)dt = iavg [k]. (2)
nCS TS k T S nCS Lipk (t)
d2 = (4)
(vO − |vin (t)|) TS
The term in the braces in (2) is the average inductor current in the
kth switching cycle iavg . Thus, vC s [k] represents the scaled value where L, vO , and vin (t) are inductance in power stage, output
of the average inductor current. Qaux in the average sensing voltage, and line voltage, respectively. iavg (t) is derived from
circuit turns on after the sampling to discharge CS before the the geometry of the waveform shown in Fig. 2(b) with unknown
next switching period. constant X, as shown in the following:
Sampling vC s [k] in the third interval occurs when the re- 1
maining time of the switching cycle is Tcal . Tcal is the minimum iavg (t) =(d1 + d2 )ipk (t) = X sin ωL t (5)
2
required time that includes A/D conversion and reset of vC s , and
where vin (t) is assumed to be the pure sine wave with peak
calculation and update of the duty cycle for the next switching
value Vpk and line period TL = 2π/ωL , which is expressed in
cycle. Because the resetting time of vC s [k] becomes negligible
the following:
by selecting Qaux with low ON-state resistance, Tcal is effec-
tively fixed by the calculation time according to the control vin (t) = Vpk sin ωL t. (6)
algorithm programmed in the microcontroller. Therefore, the
Substituting (3), (4), and (6) into (5) yields the following:
sampling time can also be fixed within the switching cycle. The  
sampling time and the inductance design to secure sufficient 2TS Vpk X Vpk sin ωL t
Tcal will be explained later. ipk (t) = 1− sin ωL t. (7)
L vO
3366 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 7, JULY 2012

ipk (t) with the pure sinusoid. Low line voltages such as 90 and
115 Vac demonstrate ipk (t) curves, which are slightly changed
from the sine wave. On the contrary, curves for high line voltages
such as 230 and 264 Vac are highly deviated and show the
local minimum in the middle of the half line period. This is
because the second square-root term in (9) is not a constant,
but a function of sin ωL t. The deviation of the term over half
line cycle becomes dominant when the line voltage is high, i.e.,
Vpk /vO is high. Considering that the pure sinusoid is the ipk
waveform of the conventional constant-duty-cycle-controlled
rectifier, the performance improvement of the proposed control
technique may be trivial with low line voltages like 90 or 115
Vac. However, it can be emphasized if the high line voltage such
as 230 or 264 Vac is applied.

III. RECTIFIER DESIGN WITH THE PROPOSED

CONTROL TECHNIQUE
Practical implementation of the proposed average current-
mode variable-duty-cycle control to boost PFC rectifier is shown
in Fig. 5. Loop configuration of the proposed control follows
the general two-loop control with the input voltage feedforward.
Output of the voltage compensator GV and the sensed rectified
input voltage are multiplied together and compared with the
sensed average inductor current. Current compensator GC out-
put is again compared with the counter value of the pulse width
modulation (PWM) generator and provides the gate signals to
the power stage.

A. Inductance Design

Fig. 4. (a) ip k curves of variable-duty-cycle-controlled DCM PFC rectifier for

A large inductance of L is effective because it decreases the
various line voltages. (b) Normalized ip k curves compared with the sine wave. rms current in DCM PFC rectifier. However, the maximum limit
of the inductance Lcrit exists to maintain the DCM operation
throughout the line cycle and load variation. Otherwise, the rec-
The unknown constant X is derived by considering input power. tifier operation may go into CCM and lose control even though
If Pin , PO , and η are input power, output power, and efficiency the control loop is designed to be stable. Specifically, the time
of the rectifier system, respectively, i.e., input filter and rectifier, duration of the third interval d3 TS should be considered in the
the following can be achieved: inductance design because the sampling of vC s and calculation
PO 1 of the next duty cycle is executed in the third interval. Fig. 6
Pin = = Irm s Vrm s = Vpk X. (8) illustrates the shrinkage of d3 TS according to the increase of L.
η 2
Assuming the same level of iavg [k], d3 TS becomes shorter when
Irm s and Vrm s in (8) represent rms of line current and line voltage L is larger because the slopes of iL become more gradual.
in a half line cycle, respectively. Rearranging and substituting Lcrit is derived in the following to properly reset vC s and
(8) into (7) yields the following: obtain sufficient calculation time Tcal : d3m in , the minimum duty
  ratio of the third switching interval, is expressed in (10) by
T S PO Vpk sin ωL t considering (3), (4), (6), and (9)
ipk (t) = 2 1− sin ωL t. (9)
ηL vO 
2 Lcrit PO
Fig. 4(a) compares various ipk (t) curves in case the variable- d3 m i n = 1 − (d1 + d2 ) = 1 −
Vpk ηTS
duty-cycle-controlled DCM rectifier outputs 400 V and 200 W,
assuming that the efficiency of the rectifier system is unity. The 1
maximum inductor current occurs at the midpoint of the half × . (10)
1 − (Vpk /vO ) sin ωL t
line period when line voltage is lower than 188.6 Vac. When the
line voltage is higher than 188.6 Vac, a local minimum forms in Equation (10) notes that d3m in occurs in the middle of the half
the middle of the curve and the maximum current occurs twice line cycle, i.e., sin ωL t = 1. d3m in is plotted as the function of
in the half line period. Detailed derivation of maximum ipk (t) Lcrit for various line voltages and PO in Fig. 7, assuming that
is discussed in Section III-A. Fig. 4(b) shows the normalized TS is 15.385 μs (reciprocal of 65 kHz) and η is a unity. The
SHIN AND CHO: DIGITALLY IMPLEMENTED AVERAGE CURRENT-MODE CONTROL IN DISCONTINUOUS CONDUCTION MODE 3367

Fig. 5. Implementation of the proposed control technique to boost PFC rectifier.

Fig. 7. d3 m in as the function of L to determine the critical inductance Lc rit .

Fig. 6. Decrease of d3 TS according to the increase of L.

worst case for d3m in is high line voltage and full load situation, For 0 < t < (TL /2), one obvious solution for (11) is when
which is represented by the solid curve at the bottom. cos ωL t = 0 or ωL t = π/2. The other solutions exist only
Selection of d3m in affects the design of Lcrit , and conse- when (2/3)(vO /Vpk ) < 1, considering the term in the sec-
quently, the maximum and the rms inductor currents. The max- ond parentheses of the numerator in (11). If vO is 400 V and
imum inductor current in a half line period, Ipk m ax , is derived (2/3)(vO /Vpk ) > 1, i.e., Vrm s < 188.6 V, (9) has the maxi-
by differentiating and equating (9) mum at ωL t = π/4 and does not have any local minimum. If
 Vrm s > 188.6 V, (9) has the local minimum at ωL t = π/4 and
d TS PO (cos ωL t) (2 − (3Vpk /vO ) sin ωL t) sin−1 (2/3)(vO /Vpk ). Substitut-
ipk (t) =  = 0. the maximums occur at ωL t = −1
dωL t ηL 1 − (Vpk /vO ) sin ωL t ing ωL t = π/2 and ωL t = sin (2/3)(vO /Vpk )in (9) accord-
(11) ing to the condition of Vpk , Ipk m ax is mathematically expressed
3368 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 7, JULY 2012

Fig. 8. Ip k m ax versus Vp k for various d3 m in . Fig. 9. Irm s versus Vp k for various d3 m in .

in (12)
  
T S PO Vpk 2 vO
Ipk m ax =2 1− if > 1 (12a)
ηL vO 3 Vpk
 
4 TS PO Vpk 2 vO
Ipk m ax = √ if < 1 . (12b)
3 3 ηL v O 3 Vpk

The rms inductor current in a half line period Irm s should also be
considered in d3m in design. Irm s is expressed, as in the follow-
ing, according to the analysis in [10], assuming that the rectifier
efficiency is a unity

 T L /2
Vpk TS 2 VO d1 (t)3 sin2 ωL t
Irm s = dt (13)
L TL 0 3(VO − Vpk sin ωL t) Fig. 10. Variation of d3 within a half line cycle when L is 88 μH.

where d1 (t) is given in (14) by combining (3), (6), and (9)

 d3m in on the middle of the line cycle, followed by 90, 115, and

2 LPO Vpk 230 Vac curves by the ascending order of d3m in .
d1 (t) = 1− sin ωL t (14)
Vpk ηTS VO
B. Sensing Capacitance and Current Sensing Gain
The critical inductances for several d3m in such as 0.1, 0.2, 0.3,
Sensing capacitance in the average sensing circuit CS is di-
and 0.4 are determined as 62, 88, 112, and 144 μH, respectively,
rectly related to the performance of the proposed control tech-
from the worst-case curve in Fig. 7, the one for 264 Vac and
nique. The range of CS is limited by practical reasons. Small
200 W. Ipk m ax and Irm s for the selected critical inductances and
CS may not be appropriate because vC s may exceed the max-
line voltages are plotted in Figs. 8 and 9, respectively, assuming
imum input voltage of the microcontroller. Large CS is either
that the rectifier outputs maximum power 200 W. Figs. 8 and
not feasible because vC s may not be reset correctly and the A/D
9, respectively, show that Ipk m ax and Irm s are proportional to
conversion resolution for vC s may become insufficient. The ca-
d3m in . Therefore, selecting large d3m in increases the peak and
pacitance is recommended to be within the range from a few
the rms inductor current. However, the effect of d3m in on Irm s is
tens to a few hundreds of nanofarads.
less considerable than that on Ipk m ax . For example, for increase
The minimum boundary of CS is not dependent on the induc-
of d3m in from 0.1 to 0.4, Irm s rises by 0.33 A, while Ipk m ax is
tance L, but on the average inductor current in a unit switching
increased by 2.4 A in 230 Vac operation.
cycle. One can notice from Fig. 6 that vC s at the sampling in-
In this paper, Tcal requires approximately 4 μs to properly
stant is constant though L changes. The boundary is determined
calculate and update the duty cycle, which spends 26% of the
by considering the maximum average inductor current in a half
unit switching cycle. With 4% margin, d3m in is set to be 0.3
line cycle Iavg m ax and the maximum input voltage of the mi-
and Lcrit is determined as 88 μH, as indicated in Fig. 7. Fig. 10
crocontroller VC s m ax as expressed in the following:
shows the variation of d3 throughout the half line cycle with the
resultant L when full load is applied. In correspondence with TS
the curves in Fig. 7, 264 Vac curve demonstrates the smallest Iavg m ax < VC s m ax . (15)
nCS
SHIN AND CHO: DIGITALLY IMPLEMENTED AVERAGE CURRENT-MODE CONTROL IN DISCONTINUOUS CONDUCTION MODE 3369

Fig. 12. Current compensator output and PWM counter to derive the modu-
lator gain FM.

Fig. 11. Small-signal diagram of the proposed control technique.

If power factor of the rectifier is a unity and the waveform

iavg (t) is sinusoidal, Iavg m ax and Irm s have the relationship
shown in the following:
1
Irm s = √ Iavg m ax (16)
2
and substituting (16) into (8) achieves the following:
√
2PO
Iavg m ax = (17)
ηVrm s m in
where Vrm s m in in (12) is the minimum rms line input voltage.
From (15) and (17), the minimum CS can be defined as follows:
√ Fig. 13. Bode plots of the current control loop Ti for 200–264 Vac line voltage.
2TS PO
CS > . (18)
nηVC s m ax Vrm s m in
In this paper, the minimum CS is 293 nF by considering TS , n, is similar to the characteristic of the conventional CCM average
PO , VCs m ax , η, and minimum line voltage as 15.385 μs, 50, current-mode-controlled converter [21], [22].
200 W, 3.3 V, a unity, and 90 Vac, respectively. A/D conversion gain and PWM modulator gain are depen-
The current sensing gain of the average sensing circuit is dent on the characteristic of the microcontroller. By the fea-
constant and does not change in the frequency domain. Though ture of the internal A/D converter and conversion algorithm of
the proposed sensing circuit integrates the inductor current, the dsPIC33FJ16GS502, Kadc is defined as follows:
integrating operation does not continue over consecutive switch- 1
Kadc = = 0.303. (20)
ing cycles. Thus, in contrast to standard analog integrators, the VC s m ax
sensing circuit does not have any frequency-dependent dynam-
PWM modulator gain is only dependent on the maximum value
ics such as analog integrators. The effect of the average sensing
of the counter in PWM generator in microcontroller. In the ana-
circuit on the small-signal modeling appears as the fixed gain Ki ,
log average current-mode control, the modulator gain is the com-
which is the shaded box in Fig. 11. Ki is defined to be TS /nCS
plicated function of switching frequency, current compensator,
as the coefficient of iavg [k] in (2).
modulator ramp slope, and sensed inductor current slope [23].
In the digital control, however, FM is simply a reciprocal of vp
C. Control Loop Implementation
shown in Fig. 12 because the output of GC does not fluctuate
Control loops are realized by the algorithm programmed in the when it is compared with the PWM counter. The unit step of the
microcontroller Microchip dsPIC33FJ16GS502. Current loop counter is set by the PWM clock signal as 1.04 ns and 14 793
gain Ti is defined as in Fig. 11 and the following: steps are required to realize 65-kHz switching frequency. FM is
determined by the following based on Q-15 data format
Ti = Gid Ki He Kadc GC FM (19)
1
where Gid is open-loop control-to-inductor current transfer FM = = 2.215. (21)
ˆ He , Kadc , GC , and FM are sampling effect, 14793/(215 − 1)
function iL /d.
internal A/D conversion gain, current compensator gain, and Gid , which can be derived from the averaged circuit model
PWM modulator gain of the digital controller, respectively. Ti [24], [25], shows flat gain up to half of the switching frequency.
3370 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 7, JULY 2012

Fig. 14. Steady-state waveforms of the proposed and conventional control methods when line voltage is 230 Vac (iL 5 A/div). (a) Proposed control with 50%
load (iav g 1 A/div). (b) Proposed control with 100% load (iav g 2 A/div). (c) Conventional control with 50% load (iav g 2 A/div). (d) Conventional control with
100% load (iav g 2 A/div).

Current compensator GC is first designed in s domain to have an As the voltage loop compensation, GV is designed through the
integrator with single pole to attenuate the HF noise, as shown similar steps of GC design. The rectified input voltage and the
in the following: output voltage are sensed through the resistive voltage divider
shown in Fig. 5. Their sampling instant and A/D conversion gain
ωi 1
GC (s) = . (22) of vO in voltage loop are the same as those of vC s in current loop.
s 1 + (s/ωp ) Capacitors in the resistive dividers are for noise reduction and
GC (s) is interpreted into z domain with zero-order-hold dis- sufficiently small not to affect the dynamic characteristics of the
cretization method with the sampling frequency 65 kHz. Resul- control loops. In Fig. 11, Kv and Kff in the voltage loop represent
tant GC (z) is shown in the following: the divider gain of the output voltage and the feedforward gain
of the input voltage, respectively. GV is designed to let the
a0 + a1 z −1 voltage loop Tv have 10-Hz bandwidth and 90◦ phase margin to
GC (z) = . (23)
1 + b1 z −1 + b2 z −2 attenuate the half-of-line-period ripple.
The calculation procedure for loop compensation algorithm
Integrator gain ω i and single pole ω p in (22) are determined contains only two vector inner products for each loop and sin-
to set the bandwidth and phase margin of Ti to 1 kHz and 75◦ gle multiplying operation for sensed input voltage and voltage
for universal line voltage and entire load range. For example, compensator output. It requires the same calculation burden with
ω i and ω p are 143 Hz and 20 kHz, respectively, in s domain, conventional digitally controlled CCM PFC rectifier. There is
and the corresponding a0 , a1 , b1 , and b2 in (23) are 0.007772, no additional square root, multiplying, or dividing operation,
0.004123, −1.145, and 0.1447, respectively, for 200–264 Vac which spends a lot of the resources of the microcontroller.
line voltage. Resultant Ti curves are shown in Fig. 13.
SHIN AND CHO: DIGITALLY IMPLEMENTED AVERAGE CURRENT-MODE CONTROL IN DISCONTINUOUS CONDUCTION MODE 3371

Fig. 15. Steady-state waveforms of the proposed and conventional control methods when line voltage is 115 Vac (iL 10 A/div, iav g 5 A/div). (a) Proposed control
with 50% load. (b) Proposed control with 100% load. (c) Conventional control with 50% load. (d) Conventional control with 100% load.

IV. EXPERIMENTAL RESULTS

The proposed current control technique is verified by a 200-W
laboratory prototype, as shown in Fig. 5. vO is regulated to be
400 V with the universal line input voltage range and the load
range of 50–200 W. Circuit components and parameters that are
not mentioned in previous sections are stated in the following.
1) Lf : 250 μH.
2) Cf : 1 μF.
3) Dbr : D25XB60.
4) L: 70 μH.
5) Q: STW20NM50.
6) D: FSF10A60.
7) C: 220 μF.
8) DZ : 1N4744.
9) CS : 660 nF.
10) Qaux : FDD8770. Fig. 16. THD comparison between the proposed and the conventional
11) Resistive input voltage sensing gain: 0.0089. constant-duty-cycle control.
3372 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 7, JULY 2012

Fig. 17. Operation of the proposed control technique in load transition when line voltage is 230 Vac (vO ac coupled, 10 V/div). (a) When the load steps from
25% to 100%. (b) When the load steps from 100% to 25%.

12) Resistive output voltage sensing gain: 0.0025. Fig. 17 shows the operation of the proposed control when the
13) Switching frequency: 65 kHz. load steps from 100% to 25% and vice versa when 230 Vac is
14) Gate driver: TC4420. applied. The proposed control shapes the inductor current in the
15) Line frequency: 60 Hz. transient operation as well. From the ac-coupled waveform of
It should be noted that the smaller sensing capacitor CS is vO , the overshoot and undershoot do not exceed 10 V.
preferred considering the efficiency of the rectifier. In case the
line voltage is specified as high range, such as 200–264 Vac, CS V. CONCLUSION
smaller than 660 nF should be selected. A digital average current control method for DCM PFC rec-
Fig. 14 illustrates the current waveforms in steady state when tifier to achieve low current distortion has been proposed. The
the load is 100 W, and 200 W when line voltage is 230 Vac. As main feature of the proposed control method is that the aver-
shown in the Fig. 14(a) and (b), the line current of the proposed age inductor current is directly sensed to eliminate additional
control follows the sinusoidal shape, as analyzed in Section II, calculation in the microcontroller. The control method achieves
and the variable-duty-cycle-controlled inductor current demon- smaller current distortion than the conventional constant-duty-
strates the local minimum in the middle of the half line period. cycle control method by employing a conventional sensing cir-
The reason the inductor current shape in a half line cycle is cuit. Circuit operation, inductor current shaping, and rectifier
not symmetrical is that the output of the voltage compensator design procedure have been analyzed and explained with math-
GV is not fixed. However, the effect of the asymmetry on the ematical expressions. The proposed control technique has been
current distortion is negligible. For comparison, Fig. 14(c) and verified and compared with the conventional approach based
(d) shows the waveforms of the constant-duty-cycle-controlled on the experimental results achieved with a 200 W prototype.
DCM PFC. The inductor current looks like a sinusoid, but the Waveforms and measured data have proven the performance
line current is highly distorted in the middle of the half line improvement of the proposed control method.
period. The same comparison in case the line voltage is 115 Vac
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May 2004. from Virginia Polytechnic Institute and State Uni-
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