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Tea 1995
Tea 1995
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Keywords TEA1916DB1262, TEA19161T, TEA19162T TEA1995T 240 W, LLC,
resonant, half-bridge, PFC, controller, converter, burst mode, power supply,
demo board, high efficiency, 80+ certification
Abstract The TEA19161T is a digital LLC controller. It is used in combination with the
PFC controller TEA19162T.Combining these two ICs with the SR controller
TEA1995T at the secondary side results in a high-efficient resonant converter
over the whole output power range.
This document describes such a resonant power supply design with a 240 W
(12 V/20 A) typical output power.
It operates in normal mode for high and medium power levels, in low-power
mode at medium and low power levels, and in burst mode at (very) low power
levels.
Low-power mode and burst mode operation provide a reduction of power
losses, resulting in a higher efficiency at lower output power levels. Power
levels for switching over from one mode to another mode can be selected by
adjusting component values.
The efficiency at high power levels is well above 90 %.
No-load power consumption is well below 100 mW.
At 250 mW output power, the input power is well below the 500 mW (complies
easily with EUP lot6).
NXP Semiconductors
UM10972
TEA1916DB1262 digital resonant 240 W/12 V power supply demo board
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1 Introduction
Warning
The non-insulated high voltages that are present when operating this
product, constitute a risk of electric shock, personal injury, death and/or
ignition of fire.
This product is intended for evaluation purposes only. It shall be
operated in a designated test area by personnel qualified according
to local requirements and labor laws to work with non-insulated mains
voltages and high-voltage circuits. This product shall never be operated
unattended.
This user manual describes the TEA1916DB1262 240 W power supply board using
the TEA19161T, TEA19162T, and TEA1995T. The user manual contains a functional
description and a set of preliminary measurements to show the main characteristics.
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1.1.1 Pinning
SUPIC 1 16 SNSBOOST
SNSFB 2 15 SNSCAP
SNSOUT 3 14 SNSCUR
GND 4 13 SNSSET
IC
SUPREG 5 12 n.c.
GATEPFC 1 8 SNSAUX
GATELS 6 11 HB GND 2 7 PFCCOMP
IC
n.c. 7 10 SUPHS SNSCUR 3 6 SNSMAINS
aaa-017286 aaa-017287
a. TEA19161T b. TEA19162T
1.2 TEA1995T
The TEA1995T is the first product of a new generation of Synchronous Rectifier (SR)
controller ICs for switched-mode power supplies. It incorporates an adaptive gate drive
method for maximum efficiency at any load.
The TEA1995T is a dedicated controller IC for synchronous rectification on the
secondary side of resonant converters. It includes two driver stages for driving the SR
MOSFETs, which rectify the outputs of the central tap secondary transformer windings.
The two-gate driver stages have their own sensing inputs and operate independently.
GDB 1 8 GDA
GND 2 7 VCC
IC
DSB 3 6 DSA
SSB 4 5 SSA
aaa-016990
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2 Safety warning
The board must be connected to mains voltage. Avoid touching the demo board while
it is connected to the mains voltage. An isolated housing is obligatory when used in
uncontrolled, non-laboratory environments. Galvanic isolation of the mains phase using
a variable transformer is always recommended. Figure 3 shows the symbols that identify
the isolated and non-isolated devices.
019aab173 019aab174
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3 Specifications
Table 2. Specifications
Symbol Description Value Conditions
Input
Vi input voltage 90 V (RMS) to AC
264 V (RMS)
fi input frequency 47 Hz to 63 Hz
Pi(noload) no-load input power < 100 mW at 230 V/50 Hz
Pi(load=250mW) standby power < 450 mW at 230 V/50 Hz
consumption
Output
Vo output voltage 12 V
Io output current 0 A to 20 A continuous
Io(max) maximum output 25 A with OPP
current
Io(peak)max maximum peak output 30 A t < 50 ms
current
thold hold time > 10 ms at 115 V/60 Hz;
full load
tstart start time ≤ 0.5 s at 115 V/60 Hz
η efficiency ≥ 89 % average according to
CoC
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4 Board photographs
a. Top view
b. Bottom view
The board can operate at a mains input voltage between 90 V (RMS) and 264 V (RMS;
universal mains).
The TEA1916DB1262demo board contains two subcircuits:
• A BCM-type PFC converter
• A resonant LLC-type HBC converter
To achieve an optimized resonant power board, the converters are working together.
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The purpose of the TEA1916DB1262 prototype demo board is to evaluate the operation
of the combination of converters (TEA19161T, TEA19162T, and TEA1995T) in a single
output supply, which includes all modes. The performance passes general standards,
including the EuP lot6 requirements. It can be used as a starting point for further
development.
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5 Performance measurements
a. Start-up at 230 V mains and no load (0 A) b. Start-up at 115 V mains and nominal load (20 A)
(1) PFC
(2) HBC
(3) Vout
(4) Iout
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a. Start-up time = 381 ms at Vmains = 230 V (RMS) mains b. Start-up time = 495 ms at Vmains = 115 V (RMS) mains
(Iout = 20 A) (Iout = 20 A)
(1) VSUPIC
(2) Vout
(3) Vbulk
(4) Iout
5.3 Efficiency
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aaa-022160
95
η
(%)
(1)
93
(2)
91
89
87
85
10 25 40 55 70 85 100
Load (%)
aaa-022161
275
Pin
(W) (2)
225 (1)
175
125
75
25
0 50 100 150 200 250
Pout (W)
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Finally, when the output power level is further reduced, the PFC converter enters burst
mode.
The power supply consumes more power without low-power mode and burst mode.
a. PFC continues switching until regulation level is reached, b. FC continues switching until regulation level is reached,
swaps after that to normal mode when Pout is low. The then swaps to burst mode when Pout is very low. The
measurement example shows the result at Pout = 13.8 W. measurement example shows the result at Pout = 6.6 W.
(1) PFC
(2) HBC
(3) Vout
a. The “wait” time increases at lower output power when b. The “wait” time decreases at higher output power when
the HBC operates in low-power mode. The measurement the HBC operates in low-power mode. The measurement
example shows the result at Pout = 22.5 W. example shows the result at Pout = 39.7 W.
(1) PFC
(2) HBC
(3) Vout
(4) Iout
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(1) GATELS
(2) GATEPFC
(3) HBC
(4) Vout(ripple)
(5) Iout
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Figure 12. Maximum output voltage ripple in burst mode at 50 % duty cycle
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a. Basic sequential load step test is done at 1 Hz b. Basic sequential load step test is done at 10 Hz
c. Basic sequential load step test is done at 100 Hz d. Basic sequential load step test is done at 1 kHz
(1) Vout
(2) Iout
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a. OPP protection is triggered at Iout ≈ 27 A (output power is b. OPP is not triggered at Iout ≈ 26 A
lost during a safe restart)
(1) Vout
(2) GATELS
(3) HBC
(4) Iout
The power capability limitation level limits the maximum output power to typically 360 W
as long as the time fits within the selected OPP timer. In this example, the time is shorter
than 50 ms. So, when more output current is requested than accepted by the power
capability limitation level, the output voltage drops.
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(1) Vout
(2) HBC
(3) Iout
(4) GATELS
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(1) Vline
(2) Vout
(3) Iout
(4) HBC
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(1) SUPIC
(2) HBC
(3) SNSCUR
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(1) Vout
(2) Iout
(3) SNSOUT
Figure 18. Overvoltage protection at Vout = 14.1 V (SNSOUT triggers latched protection)
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(1) Vxcap
(2) Vout
(3) GATEPFC
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a. Line b. Neutral
a. Line b. Neutral
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aaa-022069
PG3
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750315374 ETD34
D206 WB203
3
SUPREG
C214 923345-06 C215 D202
MURS160 R204 T1A
U201 1 µF 10 µF 1
C213 Q202
50 V 63 V
330 nF GATEHS SUPHV 10 Ω
BAS316 SPA12N50C3
9 8 PG1 PG1
50 V C202 D203
SUPHS NC1 R205 R203
10 7 WB204 330 pF BAS316
6
180 kΩ
HB GATELS 22 Ω
1 kV
11 6 1%
WB206 NC2 SUPREG 923345-04 T1B
923345-05 12 5 D204
SNSSET TEA1916T GND ES1D
13 4 PG1 PG1 5
PG1 R299 R206
SNSCUR SNSOUT
14 3
WB205
SNSCAP SNSFB 0Ω 56 kΩ, 1 % D205 PG2
15 2 ES1D
SNSBOOST SUPIC 923345-10 R298 4
SNSBOOST 16 1
C218 0Ω C206
C203 C204 R207 47 µF
680 pF R297
47 pF 470 nF 10 kΩ 35 V
50 V 0Ω
50 V 50 V 1% R296
PG1 PG1 PG1
0Ω
R233 R234 WB209 SUPIC C222
PG2 PG2 PG1
180 kΩ 0Ω 923345-05 R209 R208 120 pF
n.m. n.m. n.m. 50 V
2.7 MΩ 2.2 MΩ n.m.
R208
C207 C219 R215
5.1 nF 680 pF 20 kΩ
33 pF C220
50 V 100 V 1% C211
1 kV 47 nF
33 nF
1 kV
PG1 PG1 PG1 C210 C209 1 kV
n.m.
R230 2
27 kΩ
Q203
BS170
R211 R212
6.8 kΩ 61.9 kΩ
1% C212 1%
33 nF
50 V PG1 aaa-022070
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R308 C306
BZX384-C3V3
47 kΩ 47 nF R309
20-2137 U302 50 V 51 Ω
AS431IBNTR-G1
4 R310 R311
47 Ω 10 kΩ
U202B
VOL618A-3X001T
3
wire
AWG18
earth
aaa-022072
Figure 24. Schematic TEA1916DB1262 240 W prototype demo board (synchronous rectifier)
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UM10972 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
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8 Layout
a. Layout
b. Components
Figure 25. Demo board layout and components (copper tracks and areas)
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9 Transformer specifications
A
term numbers
2.5 min dot locates term #1
for reference only
26.5 max 36 max
12 1
11 2
10 3
36 max
9 4
8 5
7 6
Ø 1.6 (x12)
28
3 8
70-120 kHz, N4 N2 12 V, 10 A
360-400 V 1 10 5.5
6 9
18 V, 30 mA N4 N3 12 V, 10 A
5 11
18 V, 30 mA N5
4
dimensions in mm aaa-022216
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A
term numbers
for reference only 2.8 min dot locates term #1
12 1
11 2
10 3
35.56
max
9 4
8 5
7 6
lot code
Ø 0.8 (x12) and date code
part must insert fully to surface A
in recommended grid Ø 1.6 (x12)
30.48
5.08
9 4
primary auxiliary 7.62
10 3
recommended
dimensions in mm P.C. pattern component side
aaa-022217
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10 Abbreviations
Table 15. Abbreviations
Acronym Description
BCM Boundary Conduction Mode
CMP Capacitive Mode Protection
EMC ElectroMagnetic Compatibility
EMI ElectroMagnetic Interference
HBC Half-Bridge Converter
MOSFET Metal-Oxide Semiconductor Field-Effect Transistor
OCP OverCurrent Protection
OPP OverPower Protection
OVP OverVoltage Protection
OLP Open-Loop Protection
PCB Printed-Circuit Board
PFC Power Factor Correction
RMS Root Mean Square
SOI Silicon-On Insulator
ZVS Zero-Voltage Switching
11 References
1 TEA19161T data sheet Digital controller for high-efficiency resonant power supply; 2016,
NXP Semiconductors
2 TEA19162T data sheet PFC controller; 2016, NXP Semiconductors
3 TEA1995T data sheet GreenChip dual synchronous rectifier controller; 2015, NXP
Semiconductors
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12 Legal information
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Contents
1 Introduction ......................................................... 3
1.1 TEA19161T and TEA19162T ............................ 3
1.1.1 Pinning ............................................................... 4
1.2 TEA1995T ..........................................................4
2 Safety warning .................................................... 5
3 Specifications ...................................................... 6
4 Board photographs .............................................7
5 Performance measurements .............................. 9
5.1 Test facilities ......................................................9
5.2 Start-up behavior ............................................... 9
5.3 Efficiency ..........................................................10
5.3.1 Efficiency characteristics ................................. 10
5.3.2 No-load power consumption ............................ 12
5.3.3 Standby load power consumption ....................12
5.3.4 Power factor correction ....................................12
5.4 Low-power mode and burst mode operation ....12
5.5 Operation mode transitions ............................. 14
5.6 Output voltage ripple ....................................... 15
5.7 Dynamic load response ................................... 15
5.8 OverPower Protection (OPP) ...........................17
5.9 Hold time ......................................................... 19
5.10 Short-Circuit Protection (SCP) .........................20
5.11 OverVoltage Protection (OVP) .........................21
5.12 X-capacitor discharge time .............................. 22
5.13 ElectroMagnetic Compatibility (EMC) .............. 22
6 Schematic .......................................................... 24
7 Bill Of Materials (BOM) .....................................27
8 Layout .................................................................32
9 Transformer specifications .............................. 33
9.1 Resonant transformer ...................................... 33
9.2 PFC coil ........................................................... 34
10 Abbreviations .................................................... 36
11 References ......................................................... 36
12 Legal information .............................................. 37
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.