EUP2681

TFT LCD DC-DC Converter with Integrated

Charge Pumps, OP-AMP and HV-Switch

DESCRIPTION FEATURES
The EUP2681 generates power supply rails for thin-film
2.5V to 5.5V Input Supply Range
transistor (TFT) liquid-crystal display (LCD) panels in
1.2MHz Current Mode Step Up Converter
monitors and notebooks operated from 2.5V to 5.5V input - Built-In 20V, 3.5A, 0.16Ω N-MOSFET
supply. The device integrates a step-up converter, positive - High Efficiency Up to 90%
and negative charge pumps, a high speed VCOM buffer and a
- Internal digital Soft-Start
HV-Switch.
- Fast Transient Response to Pulsed Load
The external compensated step-up converter features an
internal power MOSFET and high frequency operation - Over-Temperature Protection
allowing to use small inductors and capacitors. The step up
Regulated Charge pump for TFT gate-on Supply
converter uses fixed-frequency peak current mode control
Regulated Charge pump for TFT gate-off Supply
architecture which provides fast load-transient response and

High Speed High Current 18V VCOM Buffer
easy compensation. A 3.5A peak current limit for the
internal switch protects power supply fault condition. - 20MHz BW
The regulated positive and negative charge pump regulators - 45V/µS Slew Rate
generate the positive and negative supply rails for the TFT - More than 500mA Peak Output Current
LCD gate resistive voltage-divider ICs.
HV-Switch Circuit
The high speed VCOM buffer features 500mA short circuit - Adjustable Falling rate
current, 20MHz bandwidth, fast slew rate 45V/µs, and - Reduction of Coupling Effect between Gate Line
rail-to-rail inputs and outputs.
and Pixel
The HV-Switch circuit control provides the ability to
- Flicker Compensation Circuit
control the slope for the gate drive voltage. It shapes the
TFT gate high voltage to improve image quality.
Input Under Voltage Lockout and Thermal Protection
The EUP2681 is available in a small (4mm× 4mm) 24 pin
24 pin 4mm×4mm TQFN Package
TQFN package and operates over the -40ºC to +85ºC
RoHS Compliant and 100% Lead (Pb)-Free
temperature range. Halogen-Free

APPLICATIONS

LCD Monitors

Notebook Display

LCD TVs

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 EUP2681
Typical Application Circuit

Figure 1. EUP2681 Typical Operating Circuit

Functional Block Diagram

Figure 2. EUP2681 Functional Block Diagram

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 EUP2681
Pin Configurations
Package Type Pin Configurations

TQFN-24

Pin Description
PIN PIN DESCRIPTION
1 POS Operational Amplifier Noninverting Input.
2 NEG Operational Amplifier Inverting Input.
3 OUT Operational Amplifier Output.
Analog Ground for Operational Amplifier and Charge Pump. Connect to AGND underneath
4 BGND
the IC.
Operational Amplifier and Charge-Pump Supply Input. Connect this pin to the output of the
5 SUP
boost Regulator AVDD and bypass to BGND with a minimum 1µF capacitor.
6 DRVP Positive Charge-Pump Driver Output.
7 DRVN Negative Charge-Pump Driver Output.
High-Voltage Switch Control Input. When CTL is high, the switch between GON and SRC
is on and the switch between GON and DRN is off. When CTL is low, the switch between
8 CTL
GON and DRN is on and the switch between GON and SRC is off. CTL is inhibited by
VCC UVLO and when DEL is less than 1.25V.
9 RST Reset Output. RST is an open-drain output.
Positive Charge-Pump Regulator Feedback Input. Connect FBP to the center of a resistive
voltage- divider between the positive charge-pump regulator output and AGND to set the
10 FBP
positive charge-pump regulator output voltage. Place the resistive voltage-divider within
5mm of FBP.
Negative Charge-Pump Regulator Feedback Input. Connect FBN to the center of a resistive
11 FBN voltage- divider between the negative output and REF to set the negative charge-pump
regulator output voltage. Place the resistive voltage-divider within 5mm of FBN.
Reference Output. Connect a 1µF capacitor from REF to AGND. All power outputs are
12 REF
disabled until REF exceeds its UVLO threshold.
Supplies the Internal Reference and Other Internal Circuitry. Connect VCC to the input
13 VCC
supply voltage and bypass to AGND with a minimum 1µFceramic capacitor.

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 EUP2681
Pin Description (continued)
PIN PIN DESCRIPTION
14 AGND Analog Ground for Step-Up Regulator and Linear Regulators.
15 RSTIN VIN Reset Comparator Input. Connect to the center of a resistor-divider from VIN.
16 COMP Compensation Pin for Error Amplifier. Connect a series RC from COMP to AGND.
Step-Up Regulator Feedback Input. Connect FB to the center of a resistive voltage-divider
17 FB between the step-up regulator output and AGND to set the regulator’s output voltage. Place
the resistive voltage- divider within 5mm of FB.
18,19 PGND Power Ground.
Step-Up Regulator Switching Node. Connect inductor and catch diode here and minimize
20 LX
trace area for lowest EMI power ground.
Switch Input. Drain of the internal high-voltage back-to-back p-channel FET connects to
21 DRN
COM.
22 COM Internal High-Voltage MOSFET switch Common Terminal.
Switch Input. Source of the internal high-voltage pFET. Bypass SRC to PGND with a
23 SRC
minimum 0.1µF capacitor closed to the cap.
24 DEL High-Voltage Switch Delay Input. Connect a capacitor from DEL to AGND to set delay.
- EP Exposed Pad. Connect EP to AGND.

Ordering Information
Order Number Package Type Marking Operating Temperature Range
xxxxx
EUP2681JIR1 TQFN-24 -40 °C to 85°C
P2681

EUP2681 □ □ □ □

Lead Free Code

1: Lead Free, Halogen Free

Packing
R: Tape & Reel

Operating temperature range

I: Industry Standard

Package Type
J: TQFN

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 EUP2681
Absolute Maximum Ratings (1)
 VCC, CTL, RSTIN, RST to AGND ---------------------------------------------------- -0.3V to +6V
 DEL, REF, COMP, FB, FBN,FBP to AGND --------------------------------- -0.3V to (VCC+0.3V)
 PGND, BGND to AGND ---------------------------------------------------------------- -0.3V to +0.3V
 LX to PGND ------------------------------------------------------------------------------ -0.3V to +20V
 SUP to PGND ----------------------------------------------------------------------------- -0.3V to +20V
 DRVN, DRVP to PGND ------------------------------------------------------ -0.3V to (VSUP + 0.3V)
 SRC, COM, DRN to AGND ------------------------------------------------------------ -0.3V to + 36V
 DRN to COM ----------------------------------------------------------------------------- -30V to +30V
 SRC to SUP ------------------------------------------------------------------------------- 23V
 REF Short Circuit to AGND ------------------------------------------------------------ Continuous
 POS, NEG, OUT to AGND --------------------------------------------------- -0.3V to (VSUP + 0.3V)
 DRVN, DRVP RMS Current ------------------------------------------------------------ 200mA
 LX, PGND RMS Current Rating ------------------------------------------------------- 2.4A
 Continuous Power Dissipation (T A= +70°C)
24-Pin TQFN (derate 27.8mW/°C above +70°C) ------------------------------------ 2222mW
 Junction Temperature -------------------------------------------------------------------- +150°C
 Storage Temperature Range ------------------------------------------------------------- -65°C to +160°C
 Lead Temp (Soldering, 10sec) ---------------------------------------------------------- 260°C
 Thermal Resistance θJA (TQFN-24) --------------------------------------------------- 45°C/W
 ESD Rating
Human Body Model --------------------------------------------------------------------- 2kV
Recommend Operating Conditions (2)
 Supply Voltage (VIN) ------------------------------------------------------------------ 2.5V to 5.5V
 Operating Temperature Range ------------------------------------------------------- -40°C to +85°C
Note (1): Stress beyond those listed under “Absolute Maximum Ratings” may damage the device.
Note (2): The device is not guaranteed to function outside the recommended operating conditions.

Electrical Characteristics
(VVCC = 5V, Circuit of Figure 1, VAVDD = VSUP = 13V, TA = 0°C to +85°C, unless otherwise noted.
Typical values are at TA = +25°C)
PARAMETER CONDITIONS EUP2681 UNIT
MIN TYP MAX
VCC Input Supply Range 2.5 5.5 V
VCC Undervoltage Lockout Threshold VCC rising, hysteresis(typ)=200mV 2.05 2.25 2.45 V
VCC Shutdown Current VCC = 2V 100 200 µA
VFB = 1.3V, Not switching 1 1.5
VCC Quiescent Current mA
VFB = 1.0V, Switching 4 5
REFERENCE
REF Output Voltage No external load 1.238 1.250 1.262 V
REF Load Regulation 0< ILOAD <50µA 6 mV
REF Sink Current In regulation 10 µA
REF Undervoltage Lockout Threshold Rising edge. Hysteresis(typ)=200mV 1 1.15 V
OSCILLATOR and TIMING
Frequency 1000 1200 1400 kHz
Oscillator Maximum Duty Cycle 87 90 93 %
Duration to Trigger Fault Condition FB or FBP or FBN below threshold 47 55 65 msec

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 EUP2681
Electrical Characteristics (continued)
(VVCC = 5V, Circuit of Figure 1, VAVDD = VSUP = 13V, TA = 0°C to +85°C, unless otherwise noted.
Typical values are at TA = +25°C)
PARAMETER CONDITIONS EUP2681 UNIT
MIN TYP MAX
OSCILLATOR and TIMING
DEL Capacitor Charge Current During startup, VDEL = 1.0V 4 5 6 µA
DEL Turn-On Threshold 1.19 1.25 1.31 V
DEL Discharge Switch on resistance 20 Ω
STEP-UP REGULATOR
Output Voltage Range VVCC 18 V
FB Regulation Voltage FB = COMP, CCOMP = 1nF 1.238 1.250 1.262 V
FB Fault Trip Level Falling Edge 0.96 1 1.04 V
FB Load Regulation 0 < ILOAD < Full, transient only -1 %
FB Line Regulation VCC = 2.5V to 5.5V 0.08 0.15 %/V
FB Input Bias Current VFB = 1.25V 50 125 200 nA
FB Transconductance ∆I = ±2.5µA at COMP, FB = COMP 75 160 280 µS
FB Voltage Gain FB to COMP 2600 V/V
LX Current Limit FB=1.1V, Duty cycle = 75% 2.5 3 3.5 A
LX On-Resistance ILX = 200mA 0.16 0.25 Ω
LX Leakage Current VLX = 19V 10 20 µA
Current Sense Transresistance 0.1 0.2 0.3 V/A
Soft-Start period 7 bit current ramp 14 ms
POSITIVE CHARGE PUMP REGULATOR
VSUP Input Supply Range 6 18 V
VSUP Over Voltage Threshold VSUP = Rising, Hystersis = 200mV 19 20 21 V
Operating Frequency 0.5 × fosc Hz
FBP Regulation Voltage 1.225 1.25 1.275 V
FBP Line Regulation Error VSUP=8V to 18V, VGON=30V, 0.2 %/V
FBP Input Bias Current VFBP=1.5V -50 +50 nA
DRVP Current Limit Not in dropout 400 mA
DRVP PCH ON Resistance 4 6 Ω
DRVP NCH ON Resistance 1.5 3 Ω
FBP fault trip level Falling edge 0.96 1 1.04 V
Positive Charge Pump Soft-Start 7 bit voltage ramp with filtering to
3 5 ms
Period prevent high peak currents
NEGATIVE CHARGE PUMP REGULATOR
VSUP Input Supply Range 6 18 V
Operating Frequency 0.5 × fosc Hz
FBN regulation voltage(VREF-VFBN) VREF -VFBN=1V 0.98 1 1.02 V
FBN Input Bias Current VFBN=0mV -50 +50 nA
FBN Line Regulation Error VSUP=9V to 18V, VGOFF=-7V 0.2 %/V
DRVN PCH On-resistance 4 6 Ω
DRVN NCH On-resistance 1.5 3 Ω
DRVN Current Limit Not in dropout 400 mA
FBN fault trip level Rising edge 450 mV
Negative Charge Pump Soft-Start 7 bit voltage ramp with filtering to
3 5 ms
Period prevent high peak currents

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 EUP2681
Electrical Characteristics (continued)
(VVCC = 5V, Circuit of Figure 1, VAVDD = VSUP = 13V, TA = 0°C to +85°C, unless otherwise noted.
Typical values are at TA = +25°C)
PARAMETER CONDITIONS EUP2681 UNIT
MIN TYP MAX
POSITIVE GATE DRIVER TIMING AND CONTROL SWITCHES
CTL Input Low Voltage 0.6 V
CTL Input High Voltage 2 V
CTL Input Current CTL=0V or VVCC -1 1 µA
CTL to COM Rising Propagation
CLOAD= 100pF 250 ns
Delay
SRC Input Voltage Range 36 V
SRC-to-COM Switch On-Resistance DEL = 1.5V, CTL = VCC 5 10 Ω
DRN-to-COM Switch ON-Resistance DEL = 1.5V, CTL = AGND 30 60 Ω
COM-to-GND Pull Down DEL= 0V 1.5 2.5 KΩ
DEL = 1.5V, CTL = VCC 300 600 µA
SRC Input Current
DEL = 1.5V, CTL = AGND 200 360 µA
OPERATIONAL AMPLIFIERS
SUP Supply Range 6 18 V
VSUP Undervoltage Threshold 3.8 4 4.2 V
Buffer configuration, VPOS= VSUP/2,
SUP Supply Current 4 6.5 mA
no load
Input Offset Voltage VNEG, VPOS = VSUP/2, TA = 25°C 8 mV
Input Bias Current VNEG, VPOS = VSUP/2 -1 +1 µA
Input Common Mode Voltage Range 0 VSUP V
Input Common Mode Rejection Ratio 80 dB
IOUT = 1mA VSUP -50
Output Voltage Swing High mV
IOUT = 50mA VSUP-300
IOUT = -1mA 50
Output Voltage Swing Low mV
IOUT = -50mA 300
Large Signal Voltage Gain VOUT = 1V to (VSUP -1)V 80 dB
Slew Rate 45 V/µs
-3dB Bandwidth 20 MHz
Sourcing 500 mA
Short Circuit Current
Sinking 500
XAO CONTROL
Falling Edge @ VCC=5V 1.225 1.25 1.275 V
RSTIN Threshold
Falling Edge @ VCC=1.8V 1.213 1.25 1.287 V
RSTIN Input Current -1 1 µA
RSTIN Hysteresis 30 50 80 mV
RST Output Voltage ISINK=1mA 0.4 V
RST Blanking Time Counting from VVCC crossing 2.25V 160 220 280 msec
XAO UVLO VVCC rising with hysteresis of 50mV 1.5 1.7 V

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 EUP2681
Electrical Characteristics (continued)
(VCC = 5V, Circuit of Figure 1, VAVDD = VSUP = 13V, TA = -40°C to +85°C, unless otherwise noted.) (Note 3)
PARAMETER CONDITIONS EUP2681 UNIT
MIN TYP MAX
VCC Input Supply Range 2.5 5.5 V
VCC Undervoltage Lockout Threshold VCC rising, hysteresis(typ)=200mV 2.05 2.45 V
VCC Shutdown Current 200 µA
VFB = 1.3V, Not switching 1.5
VCC Quiescent Current mA
VFB = 1.0V, Switching 5
REFERENCE
REF Output Voltage No external load 1.230 1.267 V
REF Load Regulation 0< ILOAD <50µA 6 mV
REF Sink Current In regulation 10 µA
REF Undervoltage Lockout Rising edge. Hysteresis(typ)=200mV 1.15 V
Threshold
OSCILLATOR and TIMING
Frequency 1000 1400 kHz
Oscillator Maximum Duty Cycle 87 93 %
Duration to Trigger Fault Condition FB or FBP or FBN below threshold 47 65 msec
DEL Capacitor Charge Current During startup, VDEL = 1.0V 4 6 µA
DEL Turn-On Threshold 1.19 1.31 V
STEP-UP REGULATOR
Output Voltage Range VIN 18 V
FB Regulation Voltage FB = COMP, CCOMP = 1nF 1.230 1.267 V
FB Fault Trip Level Falling Edge 0.96 1.04 V
FB Line Regulation VCC = 2.5V to 5.5V 0.25 %/V
FB Input Bias Current VFB = 1.25V 50 200 nA
FB Transconductance ∆I = ±2.5µA at COMP, FB = COMP 75 280 µS
LX Current Limit FB=1.1V, Duty cycle = 75% 2.5 3.5 A
LX On-Resistance ILX = 200mA 0.25 Ω
Current Sense Transresistance 0.10 0.30 V/A
POSITIVE CHARGE PUMP REGULATOR
VSUP Input Supply Range 6 18 V
VSUP Over Voltage Threshold VSUP = Rising, Hystersis = 200mV 19 21 V
FBP Regulation Voltage 1.225 1.275 V
FBP Line Regulation Error VSUP=8V to 18V, VGON=30V, 0.2 %/V
FBP Input Bias Current VFBP=1.5V -50 +50 nA
DRVP PCH ON Resistance 6 Ω
DRVP NCH ON Resistance 3 Ω
FBP fault trip level Falling edge 0.96 1.04 V
Positive Charge Pump Soft-Start 7 bit voltage ramp with filtering to
prevent high peak currents 5 ms
Period
NEGATIVE CHARGE PUMP REGULATOR
VSUP Input Supply Range 6 18 V
FBN regulation voltage(VREF -VFBN) VREF - VFBN=1V 0.96 1.04 V
FBN Input Bias Current VFBN=0mV -50 +50 nA
FBN Line Regulation Error VSUP=9V to 18V, VGOFF=-7V 0.2 %/V

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 EUP2681
Electrical Characteristics (continued)
(VCC = 5V, Circuit of Figure 1, VAVDD = VSUP = 13V, TA = -40°C to +85°C, unless otherwise noted.) (Note 3)
PARAMETER CONDITIONS EUP2681 UNIT
MIN TYP MAX
NEGATIVE CHARGE PUMP REGULATOR
DRVN PCH On-resistance 6 Ω
DRVN NCH On-resistance 3 Ω
Negative Charge Pump Soft-Start 7 bit voltage ramp with filtering to
5 ms
Period prevent high peak currents
POSITIVE GATE DRIVER TIMING AND CONTROL SWITCHES
CTL Input Low Voltage 0.6 V
CTL Input High Voltage 2 V
CTL Input Current CTL=0V or VVCC -1 1 µA
SRC Input Voltage Range 36 V
SRC-to-COM Switch On-Resistance DEL = 1.5V, CTL = VCC 10 Ω
DRN-to-COM Switch ON-Resistance DEL = 1.5V, CTL = AGND 60 Ω
COM-to-GND Pull Down DEL= 0V 1.5 2.5 KΩ
DEL = 1.5V, CTL = VCC 600 µA
SRC Input Current
DEL = 1.5V, CTL = AGND 360 µA
OPERATIONAL AMPLIFIERS
SUP Supply Range 6 18 V
VSUP Undervoltage Threshold 3.8 4 4.2 V
Buffer configuration, VPOS=VSUP/2,
SUP Supply Current 6.5 mA
no load
Input Offset Voltage VNEG, VPOS = VSUP/2, TA = 25°C 8 mV
Input Bias Current VNEG, VPOS = VSUP/2 -1 +1 µA
Input Common Mode Voltage Range 0 VSUP V
IOUT = 1mA VSUP -50
Output Voltage Swing High mV
IOUT = 50mA VSUP-300
IOUT = -1mA 50
Output Voltage Swing Low mV
IOUT = -50mA 300
Sourcing 500
Short Circuit Current mA
Sinking 500
XAO CONTROL
RSTIN Threshold Falling Edge 1.225 1.275 V
RSTIN Input Current -1 1 µA
RSTIN Hysteresis Falling Edge 30 80 mV
RST Output Voltage ISINK=1mA 0.4 V
RST Blanking Time Counting from VVCC crossing 2.25V 160 280 msec
VCC rising with typical hysteresis of
XAO UVLO 1.7 V
50mV
Note (3): -40°C specs are guaranteed by design, not production tested.

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 EUP2681
Typical Operating Characteristics

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 EUP2681
Typical Operating Characteristics (continued)

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 EUP2681
Typical Operating Characteristics (continued)

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 EUP2681
Typical Operating Characteristics (continued)

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 EUP2681
Table 1. Component List (Figure 1) Output voltage of Step up Converter can be set according
Designation Description to the following equations:
C1, C2 10µF, 6.3V, X5R ceramic capacitors
 R 
C3, C4 10µF, 25V, X5R ceramic capacitors VSTEP-UP = VFB × 1 + 8 
C5, C7 1µF, 6.3V, X7R ceramic capacitors  R9 
C6 1µF, 25V, X7R ceramic capacitor
C8 10nF, 50V, X7R ceramic capacitor Where the range of R2 is from 10KΩ to 50KΩ, typical
C9 220pF, 50V, X7R ceramic capacitor value of VFB is 1.25V.
C10, C14, C16 1µF, 50V, X7R ceramic capacitors Inductor Selection
C11, C15, C17 0.1µF, 50V, X7R ceramic capacitors
C12 33nF, 50V, X7R ceramic capacitor The output voltage ripple, transient response, capacity and
Schottky diode 30V, 3A efficiency of output current supply are decided by
D1 inductor selection and the inductor value is influenced by
Toshiba CMS02 (TE12L,Q)
Dual diodes 30V, 200mA(3 SOT23) input and output voltage, switching frequency and the
D2, D3, D4 Zetex BAT54S maximum output current. For most application, 3µH
Fairchild BAT54S inductor fits the application of 1.2MHz.
Inductor, 3µH, 3A Moreover, it is noteworthy that the maximum direct
L1
Sumida CDRH6D28-3R0 current of inductor must exceed the peak inductor current
Function Description expected by power MOSFET, the peak current value can
be calculated as：
Step Up Converter I OUT × VSTEP -UP
Step up Converter can operate in continuous conduction
I L(PEAK) = +
VIN
mode and steady state operation, where the inductor
VIN × (VSTEP -UP − VIN )
current is continuously. In the first half cycle, the power 1/2 ×
MOSFET is on and Schottky diodes are reverse biased, L × VSTEP -UP × FS
the output current is provided by output capacitor,
inductor voltage is VIN , and its current increase at the rate
of VIN/L; during the other half cycle, MOSFET is off and
Schottky diodes are forward biased, the energy stored in
the inductor is released. The inductor current ripple is:
VIN − VOUT
∆I L = ∆T2 ×
L
1− D
∆T2 =
FSW
Where L is self-inductance, the energy of inductor is
stored by electromagnetic induction.
In the steady state operation, the energy stored in inductor
must be converted equally, so the inductor current ripples
in two half cycle are identical.
∆I L 1 + ∆I L2 = 0
D VIN 1 - D VIN − VOUT
× + × =0
FSW L FSW L
Figure 3. Step-Up Regulator Functional Diagram
VSTEP -UP 1
= Output Capacitor:
VIN 1− D
Small value of ESR capacitor can minimum the output
Output Voltage voltage ripple. So it is recommended that multi-layer
The output voltage is reduced to a reference voltage ceramic capacitors（X5R or X7R）are used to be output
1.25V by external feedback resistor divider. The resistors capacitor because of its low ESR characteristics and small
maximum value is limited by feedback output biased size in package. Higher ESR tantalum capacitor is also
current and potential coupling noise of feedback pin. preferred. ESR determines the output voltage ripple
according to the equation:
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 EUP2681
I OUT × D I L = current limitation of MOSFET
∆VO = + I OUT × ESR I L -AVG
FS × C O ＝average inductor current
To meet the requirements of output ripple and load ∆I L ＝inductor current ripple
transient response, 10µF~47µF ceramic capacitor is often VIN × (VO + VDIODE − VIN )
selected. In the noise sensitive operation, a 0.1µF parallel ∆I L =
bypass capacitor could be connected to output capacitor L × (VO + VDIODE ) × FS
for reducing the high frequency noise of the LX switching. VDIODE
：forward voltage of Schottky diode (typical value
Schottky Diode is 0.3 V)；
FS
The Schottky diode for a high performance converter must ：switching frequency，1.2MHz；
be chosen correctly depending on some parameters such as I OUT
reverse breakdown voltage, forward current and forward I L-AVG =
voltage drop. Schottky diodes of EUP2681 must follow 1− D
these rules: 3A maximum output current; reverse D：conductive rate of MOSFET，
breakdown voltage must be greater than the peak output VIN
voltage; low forward voltage drop, low dropout current D = 1−
and fast reverse recovery. VSTEP -UP + VDIODE
Input Capacitor Dual Charge-Pump Regulator
Input capacitors, which are decided by input and output The EUP2681 contain two individual low-power charge
voltage, maximum output current, inductor and supply pumps. One charge pump inverts the supply voltage (SUP)
noise, are important in restraining input voltage ripple and and provides a regulated negative output voltage. The
enhancing chip performance. In most application, a 20µF second charge pump triples the supply voltage (SUP) and
capacitor is suitable, but if the output current is close to 3A, provides a regulated positive output voltage. The EUP2681
output capacitor must be set from 22µF to 47µF. Care contain internal p-channel and n-channel MOSFETs to
must be taken to make sure that chip is normal operated, a control the power transfer. The internal MOSFETs switch
20Ω resistor and a 1µF bypass capacitor should be taken at a constant 600 kHz (0.5 x fOSC).
next to the VCC pin to decrease the high frequency noise Negative Charge Pump
of power wire.
Loop Compensation
The feedback loop of EUP2681 contains a trans-
conductance amplifier, which makes the chip achieve
better transient response and regulation. The EUP2681
employs current mode control architecture, which features
rapid current sense loop and slow voltage feedback loop.
Compensation is not required for rapid current sense loop
but is necessary for slow voltage feedback loop to insure
that the device is in the steady state. RC network
connected between the COMP pin and GND is a
compensation network. In the network, resistors play a
decisive role in achieving a high gain of high-frequency
and obtain fast transient response. Capacitor sets the zero
Figure 4. Negative Charge-pump
of the integrator. Assuring about loop stabilization,
capacitor must be chosen between 220pF~10nF and During the first half-cycle, the p-channel MOSFET turns
resistor must be chosen accurately in the range of 2kΩ on and the flying capacitor C11 charges to VSUP minus a
~100kΩ. diode drop. During the second half-cycle, the p-channel
MOSFET turns off, and the n-channel MOSFET turns on,
Maximum Output Current
level shifting C11. This connects C11 in parallel with the
The output current capacity of EUP2681 is influenced by reservoir capacitor C10. If the voltage across C10 minus a
current limitation, input voltage, working frequency and diode drop is higher lower than the voltage across C11,
inductance value, and described as follows： charge flows from C10 to C11 until the diode (D6) turns
I L = I L − AVG + (1/2 × ∆I L ) off. The amount of charge transferred to the output is
controlled by the variable n-channel on-resistance.
where:
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 EUP2681
Positive Charge Pump R 6 ≅ R 7[(VREF − VFBN ) / (VFBN − VGOFF )]

Where VREF=1.25V.VPOS can range from VSUP to 36V and

VNEG can range from 0 to AVDD.
Flying Capacitor
Increasing the flying capacitor’s value reduces the output
current capability. Above a certain point, increasing the
capacitance has a negligible effect because the output
current capability becomes dominated by the internal
switch resistance and the diode impedance. Start with
0.1uF ceramic capacitors. Smaller values can be used for
low-current applications.
Charge-Pump Output Capacitor
Increasing the output capacitance or decreasing the ESR
reduces the output ripple voltage and the peak-to-peak
Figure 5. Positive Charge-pump transient voltage. Use the following equation to
approximate the required capacitor value:
During the first half-cycle, the n-channel MOSFET turns
on and charges the flying capacitor C15 and C17. This C OUT ≥ [I OUT / (600KHz × VRIPPLE )]
initial charge is controlled by the variable n-channel on
Use a bypass capacitor with a value equal to or greater
resistance. During the second half-cycle, the n-channel
than the flying capacitor. Place the capacitor as close to the
MOSFET turns off and the p-channel MOSFET turns on,
IC as possible. Connect directly to GND.
level shifting C15 and C17 by VSUP volts. If the voltage
across C14 plus a diode drop (VPOS +VDIODE) is smaller Charge-Pump Input Capacitor
than the level-shifted flying capacitor voltage (VC17 +VSUP) Use a bypass capacitor with a value equal to or greater
charge flows from C17 to C14 until the diode (D4) turns than the flying capacitor. Place the capacitor as close to the
off. SUP pin as possible. Connect directly to GND.
Efficiency Considerations Rectifier Diode
The efficiency characteristics of the EUP2681 regulated Use Schottky diodes with a current rating equal to or
charge pumps are similar to a linear regulator. They are greater than 4 times the average output current, and a for
dominated by quiescent current at low output currents and the positive voltage rating at least 1.5 times VSUP for the
by the input voltage at higher output currents. So the negative charge pump.
maximum efficiency can be approximated by: VCOM Amplifier
Efficiency ≅ VNEG / [VSUP × N ] VCOM amplifier provides VCOM voltage for LCD monitor.
Its main features are listed as follows: the VCOM
For the negative charge pump
amplifier is capable of ±100mA continuous output current,
Efficiency ≅ VPOS / [VSUP × (N + 1)] 45V/µs slew rate, 20 MHz -3dB bandwidth and rail to rail
input/output voltage.
For the positive charge pump, where N is the number of
charge-pump stages. Limitation and Protection of Short-circuit Current
Output Voltage Selection VCOM amplifier in EUP2681 has a more than 500mA
short-circuit current limitation. The output current of OUT
Adjust the positive output voltage by connecting a
would be limited to around ±500mA to avoid chip damage
voltage-divider from the output (VPOS) to FBP to GND
caused by too large current by connecting OUT to power
Typical Operating Circuit. Adjust the negative output
supply or ground.
voltage by connecting a voltage-divider from the output to
FBN to REF. Higher resistor values improve efficiency at Power Dissipation
low output current but increase output-voltage error due to The power dissipation of VCOM amplifier is mainly
the feedback input bias current. Calculate the remaining decided by the output current, output voltage and the
resistors with the following equations: power voltage; it can be calculated by following equation:
R15 ≅ R16[(VPOS /VREF ) − 1] PDSOURCE = IOUT(SOURCE) × (VDD-VOUT )

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 EUP2681
PD SINK = I OUT(SINK) × VOUT HV-Switch circuit is shown in following figure, the block
is disabled and COM is grounded. When DEL is HIGH,
Where the IOUT(SOURCE) is output current of the amplifier, the output is determined by CTL. When CTL goes high,
the IOUT(SINK) is sink current of amplifier. Typically, the COM is pulled to SRC by a 5Ω switch. When CTL goes
VCOM amplifier’s power supply voltage (SUP) is 13V, low, COM is driven to AVDD, with a slew rate controlled
output voltage is 3V, output current is 20mA and power by resistor on DRN pin. Note that AVDD is used only as a
dissipation is 200mW. reference voltage for HV-Switch.

Figure 6. Op Amp Input Clamp Structure

The operational amplifier is typically used to drive the
LCD backplane (VCOM) or the gamma-correction divider
string. The LCD backplane consists of a distributed series Figure 7. Switch Control
capacitance and resistance, a load that can be easily driven
XAO Voltage Detector
by the operational amplifier. However, if the operational
amplifier is used in an application with a pure capacitive Based upon the input at the RSTIN and VCC pins, the
load, steps must be taken to ensure stable operation. As the XAO controller either pulls the reset pin RST low or sets it
operational amplifier’s capacitive load increases, the to high impedance. RST is an open-drain output. Pull it
amplifier’s bandwidth decreases and gain peaking high to system 3.3V through a 10kΩ resistor. Connect
increases. A 5Ω to 50Ω small resistor placed between OUT through resistor-dividers R11 and R12 RSTIN to VIN
and the capacitive load reduces peaking, but also reduces (Figure 1) to set the proper XAO threshold. Once VCC
the gain. An alternative method of reducing peaking is to voltage exceeds approximately 2.25V, the controller
place a series RC network (snubber) in parallel with the initiates a 220ms blanking period during which the drop on
capacitive load. The RC network does not continuously VCC is ignored and RST is set to high impedance. After
load the output or reduce the gain. Typical values of the this blanking period and if RSTIN goes below
resistor are between 100Ω and 200Ω, and the typical value approximately 1.25V, RST is pulled low indicating low
of the capacitor is 10nF. RSTIN input. RST stays low until VCC falls below
approximately 1V. Then RST cannot be held low any more.
Reference Voltage (REF)
The controller gives up and RST is pulled up by the
The reference voltage is nominally 1.25V, and can source external resister. A 50mV hysteresis is implemented for
at least 50µA (see the Typical Operating XAO threshold.
Characteristics).VCC is the input of the internal reference
Start Up Sequence
block. Bypass REF with a 1µF ceramic capacitor
connected between REF and AGND. The greater bypass The soft-start is motivated by internal digital soft-start,
capacitor is, more stable REF is. which is generated by 7 byte DAC circuit. The MOSFET
peak current is limited by the soft-start circuit. Once the
HV-Switch Circuit
VCC pin exceeds approximately 2.25V, the soft-start
The HV-Switch is used for LCD applications in which initiates.
shaping of the gate high voltage signal improves image Once the voltage on VCC exceeds the XAO UVLO
quality. threshold of approximately 1.5V, the reference turns on
The HV-Switch circuit functions as three ways multiplexer, with a 1µF REF bypass capacitor, the reference reaches its
switching COM between ground, AVDD and SRC. Voltage regulation voltage of 1.25V in approximately 1ms. When
selection is provided by inputs DEL (enable) and CTL the reference voltage exceeds 1V and VCC exceeds its
(control). High to low slew control is provided by external UVLO threshold of approximately 2.25V, the IC enables
components on pins DRN. A block diagram of the the main step-up regulator, the gate-on linear-regulator

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 EUP2681
controller, and the gate-of linear-regulator controller Under-Voltage Lockout (UVLO)
simultaneously.
The UVLO circuit compares the input voltage at VCC
The IC employs soft-start for each regulator to minimize with the VULO threshold (2.25V rising , 2.05V falling, typ)
inrush current and voltage overshoot and to ensure a to insure the input voltage is high enough for reliable
well-defined startup behavior. Each output uses a 7-bit operation . The 200 mV (typ) hysteresis prevents supply
soft-start DAC. For the step-up and the gate-on linear transients from causing a restart. Once the input voltage
regulator, the DAC output is stepped in 128 steps from exceeds the UVLO rising threshold, startup begins.
zero up to the reference voltage. For the gate-off linear
When the input voltage falls below the UVLO falling
regulator, the DAC output steps from the reference down
threshold, the controller turns off the main step-up
to 250mV in 128 steps. The soft-start duration is 10ms (typ)
regulator and disable the switch-control block, the
for step-up regulator and 3ms (typ) for gate-on and
operational amplifier output is high impedance.
gate-off regulators.
A capacitor (CDEL) switch control blocks startup delay. Fault Protection
After the input voltage exceeds the UVLO threshold EUP2681 has over-current protection and over-
(2.25V typ) and the soft-start routine for each regulator is temperature protection. When the chip working, integrated
complete and there is no fault detected, a 5µA current over-temperature protection circuit continuous detects the
source starts. Once the capacitor voltage exceeds DEL chip temperature, and the chip would be turn off if the chip
charging CDEL 1.25V (typ), the switch-control block is temperature exceed the over-temperature protection
enabled as shown in Figure 8. After the switch-control threshold. (the over-temperature protection’s high and low
block is enabled, COM can be connected to SRC or DRN threshold are 160°C and 140°C respectively).
through the internal p-channel switches, depending upon During steady-state operation, if the output of the main
the state of CTL. Before startup and when VCC is less regulator or any of the outputs exceeds their respective
than UVLO, DEL is internally connected to AGND. Select fault-detection thresholds, the EUP2681 activates an
CDEL to set the delay time using the following equation: internal fault timer. If any condition or combination of
5µA conditions indicates a continuous fault for the fault-timer
CDEL = DELAY _ TIME × duration (50ms typ), the EUP2681 sets the fault latch to
1.25V
shut down all the outputs except the reference. Once the
fault condition is removed, cycle the input voltage to clear
the fault latch and reactivate the device. The
fault-detection circuit is disabled during the soft-start time.
PCB Layout
To obtain high performance including good regulation,
high efficiency and stability, high power switching supply,
a good PCB layout is expected. The PCB layout must be
evaluated strictly. Power element should be placed as close
as possible ensuring the traces are short, straight and wide.
Put power element together enough, and connect them by
using asteroid in the element layer, then connect the
asteroid to external Ground using some vias. Do not
connect the GND pin of power element to external Ground.
There are some general guidelines for layout:
 Put inductors, output diodes and output capacitances
beside input capacitor，LX and PGND to minimize
the circle area of high-current. The input loop of
high-current begins with positive of input capacitor,
sequentially through an inductor, the LX pin and
PGND, finally reaches the negative of capacitor. And
the output loop of high-current is consisted with the
positive of input capacitor, through the inductor and
the output terminal of diode and the positive of output
Figure 8. Start Up Sequence capacitor for reconnecting the GND of output
capacitor with the GND of input capacitor .Keep
these traces shot and wide. Meanwhile, avoid using
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 EUP2681
via in the circle area of high-current, otherwise, put
via parallel to reduce resistance and inductance.
 Put all the feedback resistances within the 5mm scope
of the corresponding feedback pin of them and keep
the traces short enough to avoid switching noise.
Keep feedback traces as close as possible to LX
prevent a shield come into being.
 Put the bypass capacitances as close as possible to
VIN and LVIN, the GND pin of bypass capacitances
should be connected to the AGND pin using wide
trace.
 Keep the traces between output capacitance and load
as short and wide as possible to get a best transient
response.
Keep the node area of LX least in the condition of insuring
it is as short and wide as possible. Insure the node of LX
far away from feedback node (FB) and AGND. Shield LX
with DC traces if needed.

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 EUP2681
Packaging Information

TQFN-24

Note: Exposed pad outline drawing is for reference only.

MILLIMETERS INCHES
SYMBOLS
MIN. Normal MAX. MIN. Normal MAX.
A 0.70 0.75 0.80 0.028 0.030 0.031
A1 0.00 - 0.05 0.000 - 0.002
b 0.18 0.25 0.30 0.007 0.010 0.012
E 3.90 4.00 4.10 0.154 0.157 0.161
D 3.90 4.00 4.10 0.154 0.157 0.161
D1 2.50 2.70 2.85 0.098 0.110 0.112
E1 2.50 2.70 2.85 0.098 0.110 0.112
e 0.50 REF 0.020 REF
L 0.30 0.40 0.50 0.012 0.016 0.020

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