NB679

NB679
28V, Low Iq, High Current, Fixed 5V-8A

Synchronous Buck Converter
with 100 mA LDO
DESCRIPTION FEATURES
The NB679 is a fully integrated, high-frequency,  Wide 5.5 V to 28 V Operating Input Range
synchronous, rectified, step-down switch-mode  Fixed 5 V Vout
converter with a fixed 5 V output. It offers a very  Supports 5.5 V-5 V
compact solution to achieve 8 A continuous  Ultrasonic Mode with Fs over 25 kHz
output current and 10 A peak output current  100 μA Low Quiescent Current
over a wide input supply range with excellent  8 A Continous Output Current
load and line regulation.  10 A Peak Output Current
The NB679 operates at high efficiency over a  Adaptive COT for Fast Transient
wide output current load range based on MPS  DC Auto-Tune Loop for Load Regulation
proprietary switching loss reduction technology  Stable with POSCAP and Ceramic Output
and internal low Ron power MOSFETs. Capacitors
Adaptive constant-on-time (COT) control mode  Built-In 5 V, 100 mA LDO with Switch Over
provides fast transient response and eases loop  1% Reference Voltage
stabilization. The DC auto-tune loop provides  Internal Soft Start
good load and line regulation.  Output Discharge
 700 kHZ Switching Frequency
NB679 provides a fixed 5 V LDO, which can be
 OCP, OVP, UVP, and Thermal Shutdown.
used to power the external peripheries.
 Latch-Off Reset via EN or Power Cycle
Full protection features include OC limit, OVP,  QFN-12 (2mm x 3mm) Package
UVP, and thermal shutdown.
APPLICATIONS
The converter requires a minimum number of
 Laptop Computers
external components and is available in QFN
 Tablet PCs
2mm x 3mm package.
 Networking Systems
 Personal Video Recorders
 Flat Panel Television and Monitors
 Distributed Power Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
3.3 Ω
VIN
220 nF
5.5 V-24 V
BST
VOUT
VIN
1.5 μH 5 V/8 A
SW
22 μF ENLDO
ENLDO
NB679 VOUT 88 μF
GND EN EN
PGND
5 V/ 100 LDO AGND
mA PG VCC
100 kΩ
GND
4.7 μF
1μF
NB679 Rev. 1.03 www.MonolithicPower.com 1

7/27/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
NB679— 28V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO
ORDERING INFORMATION
Part Number* Package Top Marking
NB679GD QFN-12 (2mm x 3mm) See Below
* For Tape & Reel, add suffix –Z (e.g. NB679GD–Z)
TOP MARKING
ALT: Product code of NB679GD

Y: Year code
LLL: Lot number
PACKAGE REFERENCE
ENLDO EN AGND VCC
12 11 10 9
Vin 1 8 BST
7 SW
PGND 2
3 4 5 6
PG NC VOUT LDO

(4)
ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance θJA θJC
Supply voltage (VIN) ....................................28 V QFN-12 (2mm x 3mm) ........... 70 ...... 15 ... C/W
VSW (DC) ......................................... -1 V to 26 V NOTES:
VSW (25 ns) .................................. -3.6 V to 28 V 1) Exceeding these ratings may damage the device.
VBST ..................................................VSW +4.5 V 2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
VOUT,VLDO .................................... -0.3 V to 6.5 V ambient thermal resistance θJA, and the ambient temperature
All other pins ............................. -0.3 V to +4.5 V TA. The maximum allowable continuous power dissipation at
(2) any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
Continuous power dissipation (TA=+25°C) TA)/θJA. Exceeding the maximum allowable power dissipation
QFN-12 (2mm x 3mm) ............................. 1.8 W produces an excessive die temperature, causing the regulator
to go into thermal shutdown. Internal thermal shutdown
Junction temperature ............................... 150C circuitry protects the device from permanent damage.
Lead temperature .................................... 260C 3) The device is not guaranteed to function outside of its
operating conditions.
Storage temperature ................ -65C to +150C 4) Measured on JESD51-7, 4-layer PCB.
(3)
Recommended Operating Conditions
Supply voltage .............................. 5.5 V to 24 V
Operating junction temp. (TJ). .. -40°C to +125°C

ELECTRICAL CHARACTERISTICS
VIN = 12 V, TJ = 25C, unless otherwise noted.
Parameters Symbol Condition Min Typ Max Units
Supply current
Supply current (shutdown) IIN VEN = 0 V, VENLDO = 0 V, 1 2 μA
VEN = VENLDO = 3.3 V,
Supply current (quiescent) IIN 110 130 µA
VOUT = 5.5 V
VEN = 0 V, VENLDO = 3.3 V,
Supply current (standby) IIN 60 80 μA
ILDO = 0 A
MOSFET
High-side switch on resistance HSRDS-ON 25 mΩ
Low-side switch on resistance LSRDS-ON 12 mΩ
Switch leakage SW LKG VEN = 0 V, VSW = 0 V 0 1 μA
Current limit
Low-side valley current limit ILIMIT 10 11 12 A
Switching frequency and timer
Switching frequency FS 700 kHz
Constant on timer Ton Vin = 10 V 600 710 820 ns
(6)
Minimum on time TON_Min 50 ns
(6)
Minimum off time TOFF_Min 220 ns
Ultrasonic mode
Ultrasonic mode operation period TUSM 20 30 40 µs
Over-voltage and under-voltage protection
OVP threshold VOVP 117% 122% 127% VREF
UVP-1 threshold VUVP-1 70% 75% 80% VREF
(6)
UVP-1 foldback timer TUVP-1 32 µs
UVP-2 threshold VUVP-2 45% 50% 55% VREF
Reference and soft start
Vout REF voltage VOUT_REF 4.95 5 5.05 V
Soft-start time TSS EN to Vout OK 1.7 2.5 ms

ELECTRICAL CHARACTERISTICS (continued)

VIN = 12V, TJ = 25C, unless otherwise noted.
Parameters Symbol Condition Min Typ Max Units
Enable and UVLO
EN rising threshold VEN_H 1.2 1.3 1.4 V
EN hysteresis VEN-HYS 150 mV
ENLDO rising threshold VEN_H 1.2 1.3 1.4 V
ENLDO hysteresis VEN-HYS 150 mV
EN high limit @ USM VEN_H_USM 1.8 V
EN low limit @ normal VEN_L_Normal 2.6 V
VEN = 2 V 5
EN input current IEN μA
VEN = 0 V 0
VIN under-voltage lockout threshold
VINVTH 4.45 4.7 V
rising
VIN under-voltage lockout threshold
VINHYS 450 mV
hysteresis
LDO regulator
LDO regulator VLDO VEN = 0 V 4.85 4.97 5.12 V
LDO load regulation VEN = 0 V, LDO load =100 mA 2 %
(5)
LDO Iimit ILDO_Limit VEN = 0 V, VLDO = 4.5 V 135 mA
(5)
Switch Rdson RSwitch ILDO = 50 mA 0.9 1.2 Ω
VCC regulator
VCC regulator VCC 3.5 3.6 3.7 V
VCC load regulation Icc = 5 mA 5 %
Power good
PG when FB rising (good) PG_Rising(Good) VFB rising, percentage of VFB 95
PG when FB falling (fault) PG_Falling(Fault) VFB falling, percentage of VFB 85
%
PG when FB rising (fault) PG_Rising(Fault) VFB rising, percentage of VFB 115
PG when FB falling (good) PG_Falling(Good) VFB falling, percentage of VFB 105
Power good low to high delay PGTd 750 μs
EN low to power good low delay PGTd_EN low 5 μs
Power good sink current capability VPG Sink 4 mA 0.4 V
Power good leakage current IPG_LEAK VPG = 3.3 V 5 μA
Thermal protection
(5)
Thermal shutdown TSD 140 °C
(5)
Thermal shutdown hysteresis TSD-HYS 25 °C
NOTE:
5) Guaranteed by design.

PIN FUNCTIONS
NB679
PIN # Name Description
Supply voltage. VIN supplies power for the internal MOSFET and regulator. The NB679
operates from a 5.5 V to 24 V input rail. An input capacitor is needed to decouple the input
1 VIN
rail. Use wide PCB traces and multiple vias to make the connection. Apply at least two
layers for this input trace.
Power ground. Use wide PCB traces and enough vias to handle the load current to make
2 PGND the connection. Make the PGND trace to the Vin decoupling capacitor as wide as
possible.
Power good output. The output of PG is an open-drain signal. It is high if the output
3 PG voltage is higher than 95 percent of the nominal voltage or lower than 105 percent of the
nominal voltage.
4 NC No connection.
VOUT is used to sense the output voltage of the buck regulator. Connect VOUT to
the output capacitor of the regulator directly. Also, VOUT acts as the input of the internal
5 VOUT
LDO switch over power input. Keep the VOUT sensing trace far away from the SW node.
Avoid vias on the VOUT sensing trace. A >25 mil trace is required.
Internal LDO output. Decouple with a minimum 4.7 µF ceramic capacitor as close to
LDO as possible. X7R or X5R grade dielectric ceramic capacitors are recommended for
6 LDO
their stable temperature characteristics. If ENLDO is high, it switches over to the LDO to
buck after PG is ok.
Switch output. Connect SW to the inductor and bootstrap capacitor. SW is driven up to
the VIN voltage by the high-side switch during the on-time of the PWM duty cycle. The
7 SW inductor current drives SW negative during the off-time. The on-resistance of the low-side
switch and the internal diode fixes the negative voltage. Use wide and short PCB traces to
make the connection. Try to minimize the area of the SW pattern.
Bootstrap. A capacitor connected between SW and BS is required to form a floating
8 BST
supply across the high-side switch driver.
Internal VCC LDO output. The driver and control circuits are powered from this voltage.
Decouple with a minimum 1 µF ceramic capacitor as close to VCC as possible. X7R or
9 VCC
X5R grade dielectric ceramic capacitors are recommended for their stable temperature
characteristics.
10 AGND Signal logic ground. Kelvin connection to PGND.
Buck enable. EN is a digital input that turns the buck regulator on or off. When the power
supply of the control circuit is ready, drive EN high to turn on the buck regulator, and drive
it low to turn off the buck regulator. Connect EN to 3V3 through a pull-up resistor or a
11 EN
resistive voltage divider for automatic start-up. Do NOT float this pin. EN can be used to
set USM. When EN is in the range of 1.4 V to 1.8 V, it enters USM. If EN is in the range of
2.6V to 3.6V, it operates in normal mode.
LDO enable pin. ENLDO is pulled up internally to high. Leave ENLDO open to enable the
12 ENLDO
LDO. Drive it low to turn off the LDO.

TYPICAL PERFORMANCE CHARACTERISTICS

VINv= 19 V, VOUT = 5 V, L = 1.5 µH/10 mΩ, Fs = 700 kHz, TJ = +25°C, unless otherwise noted.


VIN = 19 V, VOUT = 5 V, L = 1.5 µH/10 mΩ, Fs = 700 kHz, TJ=+25°C, unless otherwise noted.


VIN= 19 V, VOUT = 5 V, L = 1.5 µH/10 mΩ, Fs = 700 kHz, TJ=+25°C, unless otherwise noted.

FUNCTIONAL BLOCK DIAGRAM

NB679
AGND VCC EN VIN
VIN BSTREG BST

VOUT POR &
Soft Start VIN
Reference
VOUT
FB
On Time One
REF Shot
Min off time SW

Control
Logic
VOUT
DC Error
+
Correction +
Output
Discharge PGND
Vref
SW OC Limit
122% Vref OVP
PG
90% Vref POK
FB Fault
Logic
50% Vref UVP-2
75% Vref UVP-1
VOUT VIN
LDO Switching LDO

Over Control
PG
LDO ENLDO
Figure 1—Functional block diagram of NB679

NB679— 28 V VIN, FIXED 5 V-8 A BUCK CONVERTER WITH LDO
OPERATION
PWM Operation current is always above zero amps (see Figure 2).
When VFB is below VREF, the HS-FET is turned on
The NB679 is a fully integrated, synchronous,
for a fixed interval. When the HS-FET is turned
rectified, step-down, switch-mode converter with
off, the LS-FET is turned on until the next period.
a fixed 5 V output. Constant-on-time (COT)
control provides fast transient response and In CCM operation, the switching frequency is
eases loop stabilization. At the beginning of each fairly constant (PWM mode).
cycle, the high-side MOSFET (HS-FET) is turned
DCM Operation
on when the feedback voltage (VFB) is below the
reference voltage (VREF), which indicates When the load decreases, the inductor current
insufficient output voltage. The on period is will decrease as well. Once the inductor current
determined by the output voltage and the input reaches zero, the part transitions from CCM to
voltage to make the switching frequency fairly discontinuous conduction mode (DCM).
constant over the input voltage range. DCM operation is shown in Figure 3. When VFB is
After the on period elapses, the HS-FET is turned below VREF, the HS-FET is turned on for a fixed
off or enters an off state. It is turned on again interval, which is determined by the one-shot on
when VFB drops below VREF. By repeating timer. See Equation (1). When the HS-FET is
operation this way, the converter regulates the turned off, the LS-FET is turned on until the
output voltage. The integrated low-side MOSFET inductor current reaches zero. In DCM operation,
(LS-FET) is turned on when the HS-FET is in its VFB does not reach VREF when the inductor
off state to minimize the conduction loss. There is current approaches zero. The LS-FET driver
a dead short between the input and GND if both turns into tri-state (high Z) when the inductor
the HS-FET and the LS-FET are turned on at the current reaches zero. A current modulator takes
same time (shoot-through). In order to avoid over the control of the LS-FET and limits the
shoot-through, a dead time (DT) is generated inductor current to less than -1 mA. Hence, the
internally between the HS-FET off and the LS- output capacitors discharge slowly to GND
FET on period or the LS-FET off and the HS-FET through the LS-FET. As a result, the efficiency at
on period. light-load is improved greatly. The HS-FET is not
turned on as frequently during a light-load
Internal compensation is applied for COT control condition as it is during a heavy-load condition
for stable operation even when ceramic (skip mode).
capacitors are used as output capacitors. This
internal compensation improves the jitter At a light-load or no-load condition, the output
performance without affecting the line or load drops very slowly, and the NB679 reduces the
regulation. switching frequency naturally, achieving high
efficiency at light load.
CCM Operation
Figure 3—DCM operation
Figure 2—CCM operation

Continuous conduction mode (CCM) occurs
when the output current is high, and the inductor

NB679, 28 V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO
As the output current increases from the light- USM is selected by the EN voltage level. When
load condition, the time period within which the EN is in the range of 1.4 V to 1.8 V, it enters
current modulator regulates becomes shorter. USM. If EN is in the range of 2.6 V to 3.6 V, it
The HS-FET is turned on more frequently. Hence, operates in normal mode.
the switching frequency increases accordingly. Configuring the EN Control
The output current reaches the critical level when
The NB679 has two enable pins to control the
the current modulator time is zero. The critical
on/off of the internal regulators and LDO.
level of the output current is determined with
Equation (1): For NB679, the buck regulator and LDO are
controlled by EN and ENLDO, respectively. For
(VIN  VOUT )  VOUT
IOUT  (1) example, when the application is only used with
2  L  FSW  VIN the buck regulator, the buck regulator is realized
The device enters PWM mode once the output by pulling ENLDO low, allowing the buck to be
current exceeds the critical level. After that, the controlled by EN.
switching frequency stays fairly constant over the See Table 2 for the NB679 EN logics.
output current range.
Table 2—ENLDO/EN control
DC Auto-Tune Loop
State ENLDO EN VCC VOUT 5V LDO
NB679 applies a DC auto-tune loop to balance
S0 1 1 ON ON ON
the DC error between VFB and VREF by adjusting
the comparator input REF to make VFB always S3 1 0 ON OFF ON
follow VREF. The small DC loop improves the load S5 0 0 OFF OFF OFF
and line regulation without affecting transient Others 0 1 ON ON OFF
performance. The relationship between VFB, VREF,
and REF is shown in Figure.4 For automatic start-up, EN can be pulled up to
VFB VREF
the input voltage through a resistive voltage
DC
Error divider. Refer to the “UVLO Protection” section
REF for more details.
Soft Start (SS)
Figure 4—DC auto-tune loop operation
The NB679 employs a soft-start (SS) mechanism
Large Duty Operation to ensure smooth output during power-up. When
The NB679 supports larger duty operation (5.5 V- EN becomes high, the internal reference voltage
5 V) by its internal Ton extension function. When ramps up gradually; this causes the output
the parts detects its FB is lower than Vref and voltage to ramp up smoothly as well. Once the
Vin - Vo < 2 V, the Ton can be extended, reference voltage reaches the target value, the
extending the duty. If FB > REF or Ton reaches soft start finishes, and the part enters steady-
its limitation, Ton will stop extending. state operation.
Light load Ultrasonic Mode If the output is pre-biased to a certain voltage
Ultrasonic mode (USM) keeps the switching during start-up, the IC disables the switching of
frequency above an audible frequency area both the high-side and low-side switches until the
during light-load or no-load conditions. Once the voltage on the internal reference exceeds the
part detects both the HS-FET and the LS-FET sensed output voltage at the internal FB node.
are off (for about 30 µs), it shrinks the Ton so as
to keep Vout under regulation with optimal
efficiency. If the load continues to reduce, the
part discharges the Vout to make sure FB is
smaller than 102 percent of the internal
reference. The HS-FET turns on again once the
internal FB reaches VREF and then stops
switching.

5 V Linear Regulator Iinductor

IOC  I _ limit  (2)
There is a built-in 100 mA standby linear 2
regulator with a fixed output at 5 V, controlled by In an over-current condition, the current to the
ENLDO. The 5 V LDO is intended mainly for an load exceeds the current to the output capacitor;
auxiliary 5 V supply for the notebook system thus, the output voltage tends to fall off.
during standby mode. Eventually, it ends up crossing the under-voltage
Add a ceramic capacitor with a value between protection threshold and shuts down. Fault
4.7 μF and 22 µF placed close to the LDO pins to latching can be re-set by EN going low or the
stabilize the LDOs. power cycling of VIN.
LDO Switch Over Over/Under-Voltage Protection (OVP/UVP)
When the output voltage becomes higher than NB679 monitors the output voltage to detect over
4.8 V (and the power good is ok), the internal and under voltage. Once the feedback voltage
LDO is switched over to VOUT by the internal becomes higher than 122 percent of the target
MOSFET. This helps reduce the power loss from voltage, the OVP comparator output goes high,
the LDO. and the circuit latches as the HS-FET driver turns
off, and the LS-FET driver turns on, acting as an
Power Good (PG) -1.8 A current source.
The NB679 has power good (PG) output used to When the feedback voltage drops below 75
indicate whether the output voltage of the buck percent of the Vref but remains higher than 50
regulator is ready. PG is the open drain of a percent, the UVP-1 comparator output goes high.
MOSFET. It should be connected to VCC or The part is latched if the FB voltage remains in
another voltage source through a resistor (e.g. this range for about 32 µs (latching the HS-FET
100 k). After the input voltage is applied, the off and the LS-FET on). The LS-FET remains on
MOSFET is turned on so that PG is pulled to until the inductor current hits zero. During this
GND before SS is ready. After the FB voltage period, the valley current limit helps control the
reaches 95 percent of the REF voltage, PG is inductor current.
pulled high after 750 µs. When the FB voltage When the feedback voltage drops below 50
drops to 85 percent of the REF voltage, PG is percent of the Vref, the UVP-2 comparator output
pulled low. goes high, and the part is latched off directly after
Over-Current Protection (OCP) the comparator and logic delay (latching the HS-
NB679 has cycle-by-cycle over-current limiting FET off and the LS-FET on). The LS-FET
control. The current-limit circuit employs a remains on until the inductor current hits zero.
"valley" current-sensing algorithm. The part uses Fault latching can be re-set by EN going low or
the Rds(on) of the LS-FET as a current-sensing the power cycling of VIN.
element. If the magnitude of the current-sense UVLO Protection
signal is above the current-limit threshold, the The part starts up only when the Vin voltage is
PWM is not allowed to initiate a new cycle. higher than the UVLO rising threshold voltage.
The trip level is fixed internally. The inductor The part shuts down when VIN is lower than the
current is monitored by the voltage between GND Vin falling threshold. The UVLO protection is
and SW. GND is used as the positive current non-latch off. Fault latching can be re-set by EN
sensing node, so GND should be connected to going low or the power -cycling of VIN.
the source terminal of the bottom MOSFET.
If an application requires a higher under-voltage
Since the comparison is done during the HS-FET
lockout (UVLO), use EN (see Figure 5) to adjust
off and LS-FET on state, the OC trip level sets
the input voltage UVLO by using two external
the valley level of the inductor current. Thus, the
resistors. It is recommended to use the enable
load current at the over-current threshold (IOC)
resistors to set the Vin falling threshold above 5.5
can be calculated with Equation (2):
V. The rising threshold should be

set to provide enough hysteresis to allow for any

input supply variations.
Figure 5—Adjustable UVLO

To avoid too much sink current on EN, the EN
resistor (Rup) is usually in the range of 1 M-2 MΩ.
A typical pull-up resistor is 2 MΩ.
Thermal Shutdown
Thermal shutdown is employed in the NB679.
The junction temperature of the IC is monitored
internally. If the junction temperature exceeds the
threshold value (140ºC, typically), the converter
shuts off. This is a non-latch protection. There is
about 25ºC hysteresis. Once the junction
temperature drops to about 115ºC, it initiates a
SS.
Output Discharge
NB679 discharges the output when EN is low, or
the controller is turned off by the protection
functions UVP, OCP, OCP, OVP, UVLO, and
thermal shutdown. The part discharges outputs
using an internal 6 Ω MOSFET.

APPLICATION INFORMATION
Input Capacitor
VOUT V 1
The input current to the step-down converter is VOUT   (1  OUT )  (RESR  ) (7)
FSW  L VIN 8  FSW  COUT
discontinuous, and therefore requires a capacitor
to supply the AC current to the step-down When using ceramic capacitors, the impedance
converter while maintaining the DC input voltage. at the switching frequency is dominated by the
Ceramic capacitors are recommended for best capacitance. The output voltage ripple is caused
performance and should be placed as close to mainly by the capacitance. For simplification, the
the VIN pin as possible. Capacitors with X5R and output voltage ripple can be estimated using
X7R ceramic dielectrics are recommended Equation (8):
because they are fairly stable with temperature
fluctuations. VOUT V (8)
VOUT   (1  OUT )
8  FSW  L  COUT
2
VIN
The capacitors must have a ripple-current rating
greater than the maximum input ripple current of
the converter. The input ripple current can be When using POSCAP capacitors, the ESR
estimated with Equation (3) and Equation (4): dominates the impedance at the switching
frequency. The output ripple can be
VOUT V approximated with Equation (9):
ICIN  IOUT   (1  OUT ) (3)
VIN VIN VOUT V
VOUT   (1  OUT )  RESR (9)
FSW  L VIN
The worst-case condition occurs at VIN = 2VOUT,
where: The maximum output capacitor limitation should
I be considered in design application. For a small
ICIN  OUT (4) soft-start time period (if the output capacitor
2
value is too high), the output voltage cannot
For simplification, choose the input capacitor with reach the design value during the soft-start time,
an RMS current rating greater than half of the causing it to fail to regulate. The maximum output
maximum load current. capacitor value (Co_max) can be limited
The input capacitor value determines the input approximately using Equation (10):
voltage ripple of the converter. If there is an input CO _ MAX  (ILIM _ AVG  IOUT )  Tss / VOUT (10)
voltage ripple requirement in the system, choose
an input capacitor that meets the specification. Where, ILIM_AVG is the average start-up current
The input voltage ripple can be estimated using during a soft-start period (it can be equivalent to
Equation (5) and Equation (6): the current limit value), and Tss is the soft-start
time.
IOUT V V
VIN   OUT  (1  OUT ) (5) Inductor
FSW  CIN VIN VIN
The inductor is necessary to supply constant
The worst-case condition occurs at VIN = 2VOUT, current to the output load while being driven by
where: the switched input voltage. A larger value
1 I inductor results in less ripple current, resulting in
VIN   OUT (6) a lower output ripple voltage. However, a larger
4 FSW  CIN value inductor has a larger physical footprint, a
Output Capacitor higher series resistance, and/or a lower
saturation current. A good rule for determining
An output capacitor is required to maintain the the inductance value is to design the peak-to-
DC output voltage. Ceramic or POSCAP peak ripple current in the inductor to be in the
capacitors are recommended. The output voltage range of 30 percent to 50 percent of the
ripple can be estimated using Equation (7): maximum output current, with the peak inductor
current below the maximum switch current limit.

The inductance value can be calculated using as wide as possible (This should be the
Equation (11): number one priority).
VOUT V 2. Place the input capacitors as close to IN and
L  (1  OUT ) (11)
FSW  IL VIN GND as possible on the same layer as the IC.
3. Place the decoupling capacitor as close to
Where ΔIL is the peak-to-peak inductor ripple VCC and GND as possible. Keep the
current. switching node (SW) short and away from the
The inductor should not saturate under the feedback network.
maximum inductor peak current (including short 4. Keep the BST voltage path as short as
current), so it is suggested to choose Isat > 10 A. possible with >50 mil trace.
PCB Layout Guidelines 5. Keep the IN and GND pads connected with a
large copper plane to achieve better thermal
Efficient PCB layout is critical for optimum IC performance. Add several vias with 8 mil
performance. For best results, refer to Figure 6 drill/16 mil copper width close to the IN and
and follow the guidelines below. For more GND pads to help thermal dissipation.
information, refer to AN087.
6. A 4-layer layout is strongly recommended to
1. Place the high-current paths (GND, IN, and achieve better thermal performance.
SW) very close to the device with short, direct,
and wide traces. The PGND trace should be
PG
0402
ENLDO EN AGND VCC

VIN
12 11 10 9
Vin 1 8 BST
7 SW
PGND 2
SW
3 4 5 6
PG NS VOUT LDO
PGND
L
VOUT
7mm*6.6mm
Vout
Vout VOUT
0805
Figure 6—Recommended PCB layout

NB679, 28V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO
TYPICAL APPLICATION
3.3 Ω
VIN
220 nF
5.5 V-24 V
BST
VOUT
VIN
1.5 μH 5 V/8 A
SW
22 μF ENLDO
ENLDO
NB679 VOUT 88 μF
GND EN EN
PGND
5 V/ 100 LDO AGND
mA
PG VCC
100 kΩ
GND
4.7 μF
1 μF
Figure 7— Typical application schematic with ceramic output capacitors
3.3 Ω
VIN
220 nF
5.5 V-24 V
BST
VOUT
VIN
1.5 μH 5 V/8 A
SW
22 μF ENLDO
ENLDO
NB679 VOUT 150 μF
GND EN EN
PGND
5V/100 LDO AGND
mA PG VCC
100 kΩ
GND
4.7 μF
1 μF
Figure 8— Typical application schematic with POSCAP output capacitors—recommended for large duty
operation only.

NB679, 28V VIN, FIXED 5V-8A BUCK CONVERTER WITH LDO
PACKAGE OUTLINE DRAWING FOR 12L FCQFN (2X3MM) -6

PACKAGE INFORMATIONMF-PO-D-0212 revision 0.0
QFN-12 (2mm x 3mm)
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
TOP VIEW BOTTOM VIEW
SIDE VIEW
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.

2) EXPOSED PADDLE SIZE DOES NOT
INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.


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NB679

28V, Low Iq, High Current, Fixed 5V-8A

NB679 Rev. 1.03 www.MonolithicPower.com 1

* For Tape & Reel, add suffix –Z (e.g. NB679GD–Z)

ALT: Product code of NB679GD

NB679 Rev. 1.03 www.MonolithicPower.com 2

NB679 Rev. 1.03 www.MonolithicPower.com 3

NB679 Rev. 1.03 www.MonolithicPower.com 4

ELECTRICAL CHARACTERISTICS (continued)

NB679 Rev. 1.03 www.MonolithicPower.com 5

NB679 Rev. 1.03 www.MonolithicPower.com 6

TYPICAL PERFORMANCE CHARACTERISTICS

NB679 Rev. 1.03 www.MonolithicPower.com 7

TYPICAL PERFORMANCE CHARACTERISTICS

NB679 Rev. 1.03 www.MonolithicPower.com 8

TYPICAL PERFORMANCE CHARACTERISTICS

NB679 Rev. 1.03 www.MonolithicPower.com 9

FUNCTIONAL BLOCK DIAGRAM

VIN BSTREG BST

Min off time SW

122% Vref OVP

50% Vref UVP-2

75% Vref UVP-1

LDO Switching LDO

Figure 1—Functional block diagram of NB679

NB679 Rev. 1.03 www.MonolithicPower.com 10

Figure 3—DCM operation

Figure 2—CCM operation

NB679 Rev. 1.03 www.MonolithicPower.com 11

NB679 Rev. 1.03 www.MonolithicPower.com 12

5 V Linear Regulator Iinductor

NB679 Rev. 1.03 www.MonolithicPower.com 13

set to provide enough hysteresis to allow for any

Figure 5—Adjustable UVLO

NB679 Rev. 1.03 www.MonolithicPower.com 14

NB679 Rev. 1.03 www.MonolithicPower.com 15

ENLDO EN AGND VCC

Figure 6—Recommended PCB layout

NB679 Rev. 1.03 www.MonolithicPower.com 16

Figure 7— Typical application schematic with ceramic output capacitors

NB679 Rev. 1.03 www.MonolithicPower.com 17

PACKAGE OUTLINE DRAWING FOR 12L FCQFN (2X3MM) -6

TOP VIEW BOTTOM VIEW

1) ALL DIMENSIONS ARE IN MILLIMETERS.

RECOMMENDED LAND PATTERN

NB679 Rev. 1.03 www.MonolithicPower.com 18

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